TWI885365B - Measuring apparatus and failure detection method of semiconductor chip - Google Patents
Measuring apparatus and failure detection method of semiconductor chip Download PDFInfo
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Description
本揭露是有關一種量測機台以及一種半導體晶片的故障偵測方法。The present disclosure relates to a measuring machine and a semiconductor chip fault detection method.
手機、筆記型電腦以及平板電腦在這幾年來的需求成長十分迅速,使消費者對於記憶體的需求急遽上升。在這些電子裝置中,動態隨機存儲記憶體(Dynamic Random Access Memory, DRAM)作為連接中央處理器與快閃記憶體的橋樑,扮演非常重要的角色。因此,動態隨機存儲記憶體的信號完整性必須符合系統的要求,否則會造成電子裝置無法運作。The demand for mobile phones, laptops, and tablet computers has grown rapidly in recent years, causing consumers' demand for memory to rise sharply. In these electronic devices, dynamic random access memory (DRAM) plays a very important role as a bridge connecting the central processor and flash memory. Therefore, the signal integrity of the dynamic random access memory must meet the requirements of the system, otherwise the electronic device will not be able to operate.
通常在生產一個記憶體晶片時,會採用測試機台或探針台(probe station)來做測試,然而此兩種機台的體積非常大且成本高昂。若不以測試機台的方式,則可在一個類似主機板的主板上接上記憶體,以主板內部的程式做測試,但這種整機測試的方式會受限於主板內部程式,無法對記憶體測試所有的參數。Usually when a memory chip is produced, a test machine or a probe station is used for testing, but these two machines are very large and expensive. If a test machine is not used, the memory can be connected to a motherboard similar to a motherboard and tested using the program inside the motherboard, but this whole machine testing method is limited by the program inside the motherboard and cannot test all parameters of the memory.
本揭露之一技術態樣為一種量測機台。One technical aspect of the present disclosure is a measuring machine.
根據本揭露之一實施方式,一種量測機台包含光學桌、顯微鏡、開發板以及兩探針。顯微鏡位於光學桌上方。開發板位於光學桌上且位於顯微鏡的鏡頭下,配置以電性連接半導體晶片及提供半導體晶片檢查訊號,其中半導體晶片定位於顯微鏡的鏡頭的正下方。兩探針位於光學桌上方,兩探針配置以分別接觸半導體晶片的兩內部接點。According to an embodiment of the present disclosure, a measuring machine includes an optical table, a microscope, a development board, and two probes. The microscope is located above the optical table. The development board is located on the optical table and under the lens of the microscope, and is configured to electrically connect to a semiconductor chip and provide a semiconductor chip inspection signal, wherein the semiconductor chip is positioned directly under the lens of the microscope. The two probes are located above the optical table, and the two probes are configured to contact two internal contacts of the semiconductor chip respectively.
在本揭露之一實施方式中,量測機台更包含電路板。電路板位於開發板與半導體晶片之間,電性連接開發板。In one embodiment of the present disclosure, the measuring machine further comprises a circuit board. The circuit board is located between the development board and the semiconductor chip and is electrically connected to the development board.
在本揭露之一實施方式中,量測機台更包含插槽。插槽位於電路板上且電性連接電路板,插槽配置以供半導體晶片插入。In one embodiment of the present disclosure, the measuring machine further comprises a slot. The slot is located on the circuit board and electrically connected to the circuit board, and the slot is configured for inserting a semiconductor chip.
在本揭露之一實施方式中,插槽與顯微鏡的鏡頭在垂直方向對齊。In one embodiment of the present disclosure, the slot is vertically aligned with the lens of the microscope.
在本揭露之一實施方式中,量測機台更包含至少一氣墊腳,氣墊腳位於光學桌下,配置以使光學桌維持水平。In one embodiment of the present disclosure, the measuring machine further includes at least one air cushion foot, which is located under the optical table and configured to keep the optical table level.
本揭露之另一技術態樣為一種半導體晶片的故障偵測方法。Another technical aspect of the present disclosure is a semiconductor chip fault detection method.
根據本揭露之一實施方式,一種半導體晶片的故障偵測方法包含將半導體晶片電性連接至開發板;將開發板置於光學桌上,其中光學桌具有顯微鏡,顯微鏡位於光學桌上方,半導體晶片位於顯微鏡的鏡頭的正下方;使用開發板對半導體晶片提供檢查訊號;根據顯微鏡對半導體晶片取得的影像定位兩探針的位置,其中兩探針位於光學桌上方;以及使用兩探針對半導體晶片量測量測訊號。According to one embodiment of the present disclosure, a semiconductor chip fault detection method includes electrically connecting the semiconductor chip to a development board; placing the development board on an optical table, wherein the optical table has a microscope, the microscope is located above the optical table, and the semiconductor chip is located directly below the lens of the microscope; using the development board to provide an inspection signal to the semiconductor chip; locating the positions of two probes based on the image of the semiconductor chip obtained by the microscope, wherein the two probes are located above the optical table; and using the two probes to measure the measurement signal of the semiconductor chip.
在本揭露之一實施方式中,半導體晶片的故障偵測方法更包含將半導體晶片電性連接至開發板前,將半導體晶片開蓋。In one embodiment of the present disclosure, the semiconductor chip fault detection method further includes opening the semiconductor chip cover before electrically connecting the semiconductor chip to the development board.
在本揭露之一實施方式中,半導體晶片的故障偵測方法更包含將半導體晶片插入插槽,其中插槽電性連接至電路板;以及將電路板設置於開發板上使電路板電性電性連接至開發板。In one embodiment of the present disclosure, the semiconductor chip fault detection method further includes inserting the semiconductor chip into a socket, wherein the socket is electrically connected to a circuit board; and placing the circuit board on a development board so that the circuit board is electrically connected to the development board.
在本揭露之一實施方式中,半導體晶片的故障偵測方法更包含使用兩探針分別接觸半導體晶片的兩內部接點,其中兩內部接點的每一者的邊長在0.9微米至1.1微米的範圍中。In one embodiment of the present disclosure, the semiconductor chip fault detection method further includes using two probes to contact two internal contacts of the semiconductor chip respectively, wherein the side length of each of the two internal contacts is in the range of 0.9 microns to 1.1 microns.
在本揭露之一實施方式中,半導體晶片的故障偵測方法更包含使用位於光學桌下的至少一氣墊腳維持光學桌的水平。In one embodiment of the present disclosure, the semiconductor chip fault detection method further includes using at least one air cushion foot located under the optical table to maintain the level of the optical table.
在本揭露上述實施方式中,由於在半導體晶片的故障偵測方法中,使用了光學桌跟開發板,因此大幅度減小了測試用機台的體積,也減少了其成本。由於可根據顯微鏡取得的影像來定位探針,再使用探針直接量測訊號,因此僅需調整顯微鏡與半導體晶片之間的相對位置便可獲取清晰影像。如此一來,顯微鏡與半導體晶片並不需要在平行光學桌桌面的方向移動,操作方式簡單,測試的可重複性高,且測試的彈性也增加,可以廣泛地應用在晶片故障分析、新產品測試或產品失效測試等。In the above-mentioned embodiments disclosed herein, since an optical table and a development board are used in the semiconductor chip fault detection method, the size of the test machine is greatly reduced and its cost is also reduced. Since the probe can be positioned according to the image obtained by the microscope, and the signal is directly measured using the probe, a clear image can be obtained by simply adjusting the relative position between the microscope and the semiconductor chip. In this way, the microscope and the semiconductor chip do not need to move in a direction parallel to the optical table top, the operation is simple, the test repeatability is high, and the test flexibility is also increased. It can be widely used in chip failure analysis, new product testing, or product failure testing.
以下揭示之實施方式內容提供了用於實施所提供的標的之不同特徵的許多不同實施方式,或實例。下文描述了元件和佈置之特定實例以簡化本案。當然,該等實例僅為實例且並不意欲作為限制。此外,本案可在各個實例中重複元件符號及/或字母。此重複係用於簡便和清晰的目的,且其本身不指定所論述的各個實施方式及/或配置之間的關係。The embodiments disclosed below provide many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these examples are only examples and are not intended to be limiting. In addition, the present invention may repeat component symbols and/or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and/or configurations discussed.
諸如「在……下方」、「在……之下」、「下部」、「在……之上」、「上部」等等空間相對術語可在本文中為了便於描述之目的而使用,以描述如附圖中所示之一個元件或特徵與另一元件或特徵之關係。空間相對術語意欲涵蓋除了附圖中所示的定向之外的在使用或操作中的裝置的不同定向。裝置可經其他方式定向(旋轉90度或以其他定向)並且本文所使用的空間相對描述詞可同樣相應地解釋。Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for descriptive purposes to describe the relationship of one element or feature to another element or feature as illustrated in the accompanying figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
第1圖繪示根據本揭露之一實施方式的量測機台100的示意圖。第2圖繪示第1圖的量測機台100的顯微鏡120的鏡頭122附近的局部放大示意圖。參照第1圖及第2圖,量測機台100包含光學桌110、顯微鏡120、開發板130以及兩探針140a、140b。顯微鏡120位於光學桌110上方。顯微鏡120可以直接放置在光學桌110上,也可以透過架子懸空於光學桌110上。在一些實施方式中,顯微鏡120可為光學顯微鏡,其可包含複式顯微鏡,擁有不同的放大倍率的鏡頭。開發板130位於光學桌110上且位於顯微鏡120的鏡頭122下。當測試半導體晶片150時,開發板130配置以電性連接半導體晶片150及提供半導體晶片150檢查訊號。為求圖式清楚,第1圖的顯微鏡120用虛線表示以避免遮擋其下方元件,舉例來說,半導體晶片150定位於顯微鏡120的鏡頭122的正下方。兩探針140a、140b位於光學桌110上方,兩探針140a、140b配置以分別接觸半導體晶片150的兩內部接點152a、152b(將於第6圖詳述)。FIG. 1 is a schematic diagram of a
量測機台100更包含電路板160。電路板160電性連接開發板130。當測試半導體晶片150時,電路板160位於開發板130與半導體晶片150之間。量測機台100更包含插槽170。插槽170位於電路板160上且電性連接電路板160,插槽170配置以供半導體晶片150插入。插槽170與顯微鏡120的鏡頭122在垂直方向對齊。根據不同種類的半導體晶片150,會有不同種類的插槽170供半導體晶片150插入。舉例來說,若待量測的半導體晶片150為單顆第五代雙倍資料率同步動態隨機存取記憶體(double data rate fifth-generation synchronous DRAM, DDR5 SDRAM),則會有專屬於此種記憶體晶片的插槽170。插槽170電性連接電路板160,在一些實施方式中,電路板160可為印刷電路板(printed circuit board, PCB),但本揭露並不侷限於此。開發板130上會有未定義的腳位(undefine pins),在準備將半導體晶片150電性連接至開發板130時,會先透過開發板130內的人機介面定義這些未定義的腳位,以分別對應半導體晶片150的各個腳位。再根據不同種類的半導體晶片150,設計不同的電路板160,使得半導體晶片150能透過電路板160與插槽170電性連接至開發板130。The
應瞭解到,已敘述過的元件連接關係、材料與功效將不再重複贅述,合先敘明。在以下敘述中,將說明使用量測機台100之半導體晶片的故障偵測方法。It should be understood that the connection relationship, materials and functions of the components described above will not be repeated, and are described first. In the following description, a method for detecting a semiconductor chip failure using the
第3圖繪示根據本揭露之一實施方式的半導體晶片的故障偵測方法的流程圖。參照第3圖,半導體晶片的故障偵測方法包含下列步驟。首先在步驟S1中,將半導體晶片電性連接至開發板;接著在步驟S2中,將開發板置於光學桌上,其中光學桌具有顯微鏡,顯微鏡位於光學桌上方,半導體晶片位於顯微鏡的鏡頭的正下方;接著在步驟S3中,使用開發板對半導體晶片提供檢查訊號;接著在步驟S4中,根據顯微鏡對半導體晶片取得的影像定位兩探針的位置,其中兩探針位於光學桌上方;以及在步驟S5中,使用兩探針對半導體晶片量測量測訊號。FIG. 3 is a flow chart of a semiconductor chip fault detection method according to one embodiment of the present disclosure. Referring to FIG. 3, the semiconductor chip fault detection method includes the following steps. First, in step S1, the semiconductor chip is electrically connected to the development board; then, in step S2, the development board is placed on an optical table, wherein the optical table has a microscope, the microscope is located above the optical table, and the semiconductor chip is located directly below the lens of the microscope; then, in step S3, the development board is used to provide an inspection signal to the semiconductor chip; then, in step S4, the positions of two probes are located according to the image of the semiconductor chip obtained by the microscope, wherein the two probes are located above the optical table; and in step S5, the two probes are used to measure the measurement signal of the semiconductor chip.
在一些實施方式中,半導體晶片的故障偵測方法並不限於上述步驟S1至步驟S5,舉例來說,在一些實施方式中,步驟S1至步驟S5可在兩前後步驟之間進一步包括其他步驟,也可在步驟S1前進一步包括其他步驟,在步驟S5後進一步包括其他步驟。在以下敘述中,將詳細說明上述步驟。In some embodiments, the semiconductor chip fault detection method is not limited to the above steps S1 to S5. For example, in some embodiments, steps S1 to S5 may further include other steps between two preceding and following steps, or may further include other steps before step S1 and further include other steps after step S5. In the following description, the above steps will be described in detail.
第4圖繪示第1圖的半導體晶片150開蓋前的示意圖。第5圖繪示第4圖的半導體晶片150開蓋後的示意圖。第6圖繪示第5圖的半導體晶片150在開蓋後的局部放大俯視圖。參照第4圖至第6圖,在一些實施方式中,半導體晶片的故障偵測方法更包含將半導體晶片150電性連接至開發板130前,將半導體晶片150開蓋。在量測半導體晶片150時,會先將半導體晶片150做開蓋(decap)的動作,至少剝除半導體晶片150頂部的封裝膠(如第4圖所繪示虛線以上的部分),讓內部的電路裸露出來。這個開蓋的步驟可以施以乾蝕刻法或濕蝕刻法,但並不侷限於此。開蓋之後的半導體晶片150會裸露出內部的電路,內部電路包含內部接點(internal pad)152a、152b。在後續的量測步驟中,探針140a、140b便會接觸內部接點152a、152b,以獲取量測訊號。FIG. 4 is a schematic diagram of the
參照第1圖及第2圖,將半導體晶片150開蓋後,可將半導體晶片150插入插槽170,其中插槽170電性連接至電路板160。接著,將電路板160設置於開發板130上使電路板160電性電性連接至開發板130。如此一來,半導體晶片150可經由插槽170與電路板160電性連接至開發板130。在執行上述步驟之後,便可將半導體晶片150電性連接的開發板130放置於光學桌110上,使半導體晶片150位於顯微鏡120的鏡頭122的正下方。Referring to FIG. 1 and FIG. 2, after opening the
在開發板130置於光學桌110上後,可使用開發板130對半導體晶片150提供檢查訊號。具體而言,在開發板130對半導體晶片150提供檢查訊號時,可以藉由調整開發板130中的人機介面來更改欲提供的訊號。After the
參照第1圖及第6圖,接著,可根據顯微鏡120對半導體晶片150取得的影像來定位兩探針140a、140b的位置。如此一來,便可使用兩探針140a、140b對半導體晶片150量測量測訊號,例如使用兩探針140a、140b分別接觸半導體晶片150的兩內部接點152a、152b。舉例來說,可以提供一組全部為高位(即全部為1)的訊號,再以探針140a、140b量測。若是探針140a、140b量測到某個內部接點(假設為內部接點152a)的訊號為0,則可判定為異常。另外,也可以使用開發板130內部的時脈產生器(clock generator)產生高頻訊號,並同樣以探針140a、140b分別接觸內部接點152a、152b來探測是否有異常。若是波形與預期不同,出現雜訊,則可判定為異常。Referring to FIG. 1 and FIG. 6, the positions of the two
在一些實施方式中,半導體晶片150的兩內部接點152a、152b的每一者的邊長在0.9微米至1.1微米的範圍中,例如可為一邊長為1微米的正方形金屬接點。在使用探針140a、140b接觸半導體晶片150的內部接點152a、152b時,可以先以較小的放大倍率獲取影像,並以此影像大略定位探針140a、140b,再慢慢將放大倍率調大,以最終精確將探針140a、140b分別定位至內部接點152a、152b,例如探針140a接觸內部接點152a、探針140b接觸內部接點152b,但本揭露並不侷限於此方面。在定位探針140a、140b時,是利用顯微鏡120所獲取的影像判斷,並以此影像定位探針140a、140b,因此在定位的過程中,會調整顯微鏡120與半導體晶片150之間的距離,使得影像能夠聚焦以獲取清晰影像。探針140a、140b可包含毛細探針,其尖端直徑大約為微米等級,以接觸尺寸同樣為微米等級的內部接點152a、152b並量測量測訊號。In some embodiments, the side length of each of the two
由於在半導體晶片的故障偵測方法中,使用了光學桌跟開發板,因此大幅度減小了測試用機台的體積,也減少了其成本。由於可根據顯微鏡取得的影像來定位探針,再使用探針直接量測訊號,因此僅需調整顯微鏡與半導體晶片之間的相對位置便可獲取清晰影像。如此一來,顯微鏡與半導體晶片並不需要在平行光學桌桌面的方向移動,操作方式簡單,測試的可重複性高,且測試的彈性也增加,可以廣泛地應用在晶片故障分析、新產品測試或產品失效測試等。Since an optical table and a development board are used in the semiconductor chip fault detection method, the size of the test machine is greatly reduced and its cost is also reduced. Since the probe can be positioned according to the image obtained by the microscope, and the signal is directly measured using the probe, a clear image can be obtained by simply adjusting the relative position between the microscope and the semiconductor chip. In this way, the microscope and the semiconductor chip do not need to move in a direction parallel to the optical table surface. The operation is simple, the test repeatability is high, and the test flexibility is increased. It can be widely used in chip failure analysis, new product testing, or product failure testing.
第7圖繪示第1圖的量測機台100的光學桌110的側視圖。同時參照第1圖與第7圖,量測機台100更包含至少一氣墊腳180,且氣墊腳180位於光學桌110下。如此一來,可使用氣墊腳180維持光學桌110的水平。在本實施例中,氣墊腳180直接設置在地上作為光學桌110的桌腳,但實際應用上,可以以其他方式設置氣墊腳180,例如設置於光學桌110的桌腳與光學桌110的平台之間。在第7圖中,僅繪示光學桌110一個角落的氣墊腳180,但實際應用上,氣墊腳180的數量根據光學桌110的形狀而定,例如當光學桌110的俯視形狀為矩形時,可在光學桌110的四個角落各設置一個氣墊腳180。氣墊腳180的設置除了使光學桌110能夠在整個偵測測試的過程中保持完全水平之外,亦有隔絕外部雜訊的功效。當使用開發板130內部的時脈產生器產生高頻訊號時,此高頻訊號容易受到環境低頻雜訊的影響,因而產生波形的疊加。在沒有設置氣墊腳180的狀態下,會難以判斷量測到的異常原因是半導體晶片150的內部電路異常,亦或是環境雜訊的影響。透過氣墊腳180的設置,隔絕了外部的低頻雜訊,使得量測能夠更準確地進行。FIG. 7 shows a side view of the optical table 110 of the measuring
前述概述了幾個實施方式的特徵,使得本領域技術人員可以更好地理解本揭露的態樣。本領域技術人員應當理解,他們可以容易地將本揭露用作設計或修改其他過程和結構的基礎,以實現與本文介紹的實施方式相同的目的和/或實現相同的優點。本領域技術人員還應該認識到,這樣的等效構造不脫離本揭露的精神和範圍,並且在不脫離本揭露的精神和範圍的情況下,它們可以在這裡進行各種改變,替換和變更。The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications here without departing from the spirit and scope of the present disclosure.
100:量測機台
110:光學桌
120:顯微鏡
122:鏡頭
130:開發板
140a、140b:探針
150:半導體晶片
152a、152b:內部接點
160:電路板
170:插槽
180:氣墊腳
S1、S2、S3、S4、S5:步驟
100: Measuring machine
110: Optical table
120: Microscope
122: Lens
130:
當與隨附圖示一起閱讀時,可由後文實施方式最佳地理解本揭露內容的態樣。注意到根據此行業中之標準實務,各種特徵並未按比例繪製。實際上,為論述的清楚性,可任意增加或減少各種特徵的尺寸。 第1圖繪示根據本揭露之一實施方式的量測機台的示意圖。 第2圖繪示第1圖的量測機台的顯微鏡的鏡頭附近的局部放大示意圖。 第3圖繪示根據本揭露之一實施方式的半導體晶片的故障偵測方法的流程圖。 第4圖繪示第1圖的半導體晶片開蓋前的示意圖。 第5圖繪示第4圖的半導體晶片開蓋後的示意圖。 第6圖繪示第5圖的半導體晶片在開蓋後的局部放大俯視圖。 第7圖繪示第1圖的量測機台的光學桌的側視圖。 The disclosure is best understood from the following embodiments when read in conjunction with the accompanying illustrations. Note that various features are not drawn to scale in accordance with standard practice in the industry. In fact, the sizes of various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a schematic diagram of a measuring machine according to one embodiment of the disclosure. FIG. 2 is a partial enlarged schematic diagram of the vicinity of the lens of the microscope of the measuring machine of FIG. 1. FIG. 3 is a flow chart of a fault detection method for a semiconductor chip according to one embodiment of the disclosure. FIG. 4 is a schematic diagram of the semiconductor chip of FIG. 1 before the cover is opened. FIG. 5 is a schematic diagram of the semiconductor chip of FIG. 4 after the cover is opened. FIG. 6 shows a partially enlarged top view of the semiconductor chip in FIG. 5 after the cover is opened. FIG. 7 shows a side view of the optical table of the measuring machine in FIG. 1.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None
100:量測機台 100: Measuring machine
110:光學桌 110:Optical table
120:顯微鏡 120:Microscope
130:開發板 130: Development board
140a、140b:探針 140a, 140b: Probe
150:半導體晶片 150: Semiconductor chip
160:電路板 160: Circuit board
Claims (10)
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| TW112117017A TWI885365B (en) | 2023-05-08 | 2023-05-08 | Measuring apparatus and failure detection method of semiconductor chip |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW344877B (en) * | 1996-05-03 | 1998-11-11 | Mos Electronics Taiwan Inc | Method for simultaneously measuring the accuracy and critical dimension of overlay of wafer metrology pattern |
| JP2003107119A (en) * | 2001-07-26 | 2003-04-09 | Nidec-Read Corp | Electrical characteristic display device for wiring and wiring inspection method |
| CN1662839A (en) * | 2002-06-17 | 2005-08-31 | 塞威公司 | Modular manipulation system for manipulating a sample under study with a microscope |
| JP5555633B2 (en) * | 2007-10-10 | 2014-07-23 | カスケード・マイクロテク・ゲゼルシャフト・ミト・ベシュレンクテル・ハフツング | Method for inspecting a test substrate under a predetermined temperature condition and an inspection apparatus capable of setting the temperature condition |
| CN110879510A (en) * | 2018-09-05 | 2020-03-13 | 美光科技公司 | Wafer registration and overlay measurement system and related methods |
-
2023
- 2023-05-08 TW TW112117017A patent/TWI885365B/en active
- 2023-06-13 CN CN202310698717.7A patent/CN118914803A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW344877B (en) * | 1996-05-03 | 1998-11-11 | Mos Electronics Taiwan Inc | Method for simultaneously measuring the accuracy and critical dimension of overlay of wafer metrology pattern |
| JP2003107119A (en) * | 2001-07-26 | 2003-04-09 | Nidec-Read Corp | Electrical characteristic display device for wiring and wiring inspection method |
| CN1662839A (en) * | 2002-06-17 | 2005-08-31 | 塞威公司 | Modular manipulation system for manipulating a sample under study with a microscope |
| JP5555633B2 (en) * | 2007-10-10 | 2014-07-23 | カスケード・マイクロテク・ゲゼルシャフト・ミト・ベシュレンクテル・ハフツング | Method for inspecting a test substrate under a predetermined temperature condition and an inspection apparatus capable of setting the temperature condition |
| CN110879510A (en) * | 2018-09-05 | 2020-03-13 | 美光科技公司 | Wafer registration and overlay measurement system and related methods |
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| CN118914803A (en) | 2024-11-08 |
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