TWI871615B - Measuring appratus and failure detection method of semiconductor chip - Google Patents

Abstract

A measuring apparatus includes a chamber, an evaluation board, a probe station, a microscope, a circuit board and two probes. The evaluation board is located outside the chamber. The probe station is located in the chamber. The microscope is located in the chamber and above the probe station. The circuit board is located on the probe station, and is configured to electrically connect a semiconductor chip and the evaluation board, in which the semiconductor chip is located directly below a lens of the microscope. The two probes are located above the probe station, and are configured to contact the semiconductor chip.

Description

Fault detection method for measuring equipment and semiconductor chip

The present disclosure relates to a measuring machine and a semiconductor chip fault detection method.

The demand for mobile phones, computers, and tablet computers has grown rapidly in recent years, causing consumers' demand for memory to rise sharply. In these electronic devices, dynamic random access memory (DRAM) plays a very important role as a bridge connecting the central processing unit (CPU) and flash memory. Therefore, the signal integrity of the dynamic random access memory must meet the requirements of the system, otherwise the above electronic devices will not be able to operate.

Usually when doing fault analysis tests on memory chips, there is a test link that uses a test machine (such as MOSAID test machine) with a chamber (such as THEMOS, PHEMOS, etc.) to perform physical failure analysis (PFA) to find abnormal temperature rise phenomena when the memory chip is running at high speed. However, the test rate of the current test machine is about 416 million bytes per second, which is lower than the speed of normal memory operation. For physical failure analysis of abnormal hot spots, the higher the data transmission speed, the more abnormal hot spots can be found.

One technical aspect of the present disclosure is a measuring machine.

According to an embodiment of the present disclosure, a measuring machine includes a chamber, a development board, a probe stage, a microscope, a circuit board, and two probes. The development board is located outside the chamber. The probe stage is located inside the chamber. The microscope is located inside the chamber and above the probe stage. The circuit board is located on the probe stage and is configured to electrically connect a semiconductor chip and the development board, wherein the semiconductor chip is located directly below the lens of the microscope. The two probes are located above the probe stage and are configured to contact the semiconductor chip.

In one embodiment of the present disclosure, the measuring machine further includes a cable. The cable extends from the circuit board in the cavity to the development board outside the cavity, and the cable electrically connects the development board and the circuit board.

In one embodiment of the present disclosure, the measuring machine further comprises a slot. The slot is located on the circuit board and electrically connected to the circuit board, and the slot is configured for inserting a semiconductor chip.

In one embodiment of the present disclosure, the slot is vertically aligned with the lens of the microscope.

In one embodiment of the present disclosure, the two probes are temperature probes.

Another technical aspect of the present disclosure is a semiconductor chip fault detection method.

According to one embodiment of the present disclosure, a semiconductor chip fault detection method includes electrically connecting the semiconductor chip to a circuit board; placing the circuit board on a probe stage in a cavity, wherein a microscope is located in the cavity and above the probe stage, and the semiconductor chip is located directly below the lens of the microscope; electrically connecting the circuit board to a development board through a cable, wherein the development board is located outside the cavity; using the development board to provide an inspection signal to the semiconductor chip; locating the positions of two probes according to an image of the semiconductor chip obtained by the microscope, wherein the two probes are located above the probe stage; and using the two probes to measure a measurement signal of the semiconductor chip.

In one embodiment of the present disclosure, the semiconductor chip fault detection method further includes opening the semiconductor chip cover before electrically connecting the semiconductor chip to the development board.

In one embodiment of the present disclosure, the semiconductor chip fault detection method further includes inserting the semiconductor chip into a socket, wherein the socket is electrically connected to a circuit board.

In one embodiment of the present disclosure, locating the positions of two probes according to an image of a semiconductor chip obtained by a microscope includes using a microscope to observe at least one hot spot of the semiconductor chip; and locating the positions of the two probes according to the hot spot in the image observed by the microscope.

In one embodiment of the present disclosure, using two probes to measure a measurement signal on a semiconductor chip includes using the two probes to perform temperature measurement on a hot spot.

In the above-mentioned embodiments of the present disclosure, since a development board is used as a source of measurement signals in the fault detection method of the measuring machine and the semiconductor chip, the clock generator in the development board can generate faster signals, so more abnormal hot spots can be found in the physical property fault analysis. These abnormal hot spots can be observed through a microscope and their temperature can be measured by a probe. The operation method is simple and can more effectively find the failure area that may appear when the semiconductor chip is operating than the traditional method.

The embodiments disclosed below provide many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these examples are only examples and are not intended to be limiting. In addition, the present invention may repeat component symbols and/or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and/or configurations discussed.

Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for descriptive purposes to describe the relationship of one element or feature to another element or feature as illustrated in the accompanying figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1 is a schematic diagram of a measuring machine 100 according to one embodiment of the present disclosure. FIG. 2 is a side view of the vicinity of the lens 142 of the microscope 140 when the measuring machine 100 of FIG. 1 is in use. Referring to FIG. 1 and FIG. 2, the measuring machine 100 includes a chamber 110, a development board 120, a probe stage 130, a microscope 140, a circuit board 150, and two probes 160a and 160b. The development board 120 is located outside the chamber 110. The probe stage 130 is located inside the chamber 110. The microscope 140 is located inside the chamber 110 and above the probe stage 130. The circuit board 150 is located on the probe stage 130 and is electrically connected to the development board 120. When measuring the semiconductor chip 170, the circuit board 150 can be electrically connected to the semiconductor chip 170, and the semiconductor chip 170 is located directly below the lens 142 of the microscope 140. Two probes 160a and 160b are located above the probe stage 130, and the two probes 160a and 160b are configured to contact the semiconductor chip 170. Through the above configuration, the circuit board 150 and the semiconductor chip 170 are located in the chamber 110. The circuit board 150 and the development board 120 are electrically connected through the cable 190, and the cable 190 extends from the circuit board 150 in the chamber 110 to the development board 120 outside the chamber 110.

The measuring machine 100 further includes a slot 180. The slot 180 is located on the circuit board 150 and electrically connected to the circuit board 150, and the slot 180 is configured for inserting the semiconductor chip 170. According to different semiconductor chips 170, there will be different slots 180 for inserting the semiconductor chip 170. For example, when the semiconductor chip is a fourth-generation double data rate synchronous dynamic random access memory (Double Data Rate Fourth-generation Synchronous DRAM, DDR4 SDRAM), there will be a slot 180 dedicated to this semiconductor chip 170. In addition, there are undefined pins on the development board 120. Before the measurement begins, these undefined pins are defined through the human-machine interface in the development board 120 to correspond to the pins of the semiconductor chip 170, and then the development board 120 and the semiconductor chip 170 are electrically connected through the circuit board 150 and the cable 190. In some embodiments, the socket 180 is aligned with the lens 142 of the microscope 140 in the vertical direction.

In some embodiments, the two probes 160a and 160b are temperature probes that can measure the temperature of abnormal hot spots (abnormal hot spots, see FIG. 6 ) generated when the semiconductor chip 170 is operated at high speed. When in use, a probe (such as probe 160a) is used to contact an abnormal hot spot, or an area suspected of an abnormal hot spot, to obtain a temperature signal to determine whether it is overheated. During measurement, since the brightness and temperature of abnormal hot spots are easily affected by the surrounding environment, and the development board 120 itself has a light source, and the development board 120 may generate heat source interference during operation, the development board 120 is placed outside the cavity 110 and then electrically connected to the semiconductor chip 170 through the cable 190, the circuit board 150 and the slot 180. This can isolate the interference from the light source and heat source of the development board 120, and improve the accuracy of observing the abnormal hot spots of the semiconductor chip 170.

It should be understood that the connection relationship, materials and functions of the components described above will not be repeated, and are described first. In the following description, a method for detecting a semiconductor chip failure using the measuring apparatus 100 will be described.

FIG. 3 is a flow chart of a semiconductor chip fault detection method according to one embodiment of the present disclosure. Referring to FIG. 3, the semiconductor chip fault detection method includes the following steps: First, in step S1, the semiconductor chip is electrically connected to the circuit board. Then, in step S2, the circuit board is placed on a probe stage in the cavity, wherein the microscope is located in the cavity and above the probe stage, and the semiconductor chip is located directly below the lens of the microscope. Then, in step S3, the circuit board is electrically connected to a development board via a cable, wherein the development board is located outside the cavity. Next, in step S4, the development board is used to provide an inspection signal to the semiconductor chip. Then in step S5, the positions of the two probes are located according to the image of the semiconductor chip obtained by the microscope, wherein the two probes are located above the probe stage. And finally in step S6, the two probes are used to measure the measurement signal of the semiconductor chip.

In some embodiments, the semiconductor chip fault detection method is not limited to the above steps S1 to S6. For example, each of steps S1 to S6 may include other more detailed steps. In some embodiments, steps S1 to S6 may further include other steps between two preceding and following steps, or may further include other steps before step S1 and further include other steps after step S6. In the following description, the above steps will be described in detail.

FIG. 4 is a schematic diagram of the semiconductor chip 170 of FIG. 2 before the cover is opened. FIG. 5 is a schematic diagram of the semiconductor chip 170 of FIG. 4 after the cover is opened. Referring to FIG. 2, FIG. 4 and FIG. 5, before the semiconductor chip 170 is electrically connected to the development board 120, the semiconductor chip 170 will be first decapped, at least the packaging glue on the top 174 of the semiconductor chip 170 (as shown in FIG. 4 The portion above the dotted line) is stripped off to expose the internal circuit. This decapping step can be performed by dry etching or wet etching, but is not limited to this. The semiconductor chip 170 after the cover is opened will then be inserted into the socket 180, wherein the socket 180 is electrically connected to the circuit board 150. In this way, the semiconductor chip 170 is electrically connected to the circuit board 150 .

Referring to FIG. 1 and FIG. 2, the circuit board 150 is then placed on the probe stage 130 in the chamber 110, wherein the microscope 140 is located in the chamber 110 and above the probe stage 130, and the semiconductor chip 170 is located directly below the lens 142 of the microscope 140. Then, the circuit board 150 is electrically connected to the development board 120 through the cable 190, wherein the development board 120 is located outside the chamber 110. In this way, the semiconductor chip 170 is electrically connected to the development board 120 through the cable 190, the circuit board 150 and the socket 180. In the next step, the development board 120 can be used to provide an inspection signal to the semiconductor chip 170.

Referring to FIGS. 1, 2, and 6, the positions of the two probes 160a and 160b are then positioned based on the image of the semiconductor chip 170 obtained by the microscope 140, wherein the two probes 160a and 160b are located above the probe stage 130. This step is to observe the hot spots 172a and 172b of the semiconductor chip 170 using the microscope 140, and to position the two probes 160a and 160b respectively based on the hot spots 172a and 172b in the image observed by the microscope 140. The above-mentioned "positioning" may mean moving the probes 160a and 160b to positions where they can contact the hot spots 172a and 172b respectively. After the positions of the two probes 160a and 160b are positioned, the two probes 160a and 160b can be used to measure the measurement signal. The measurement signal is, for example, a temperature signal of the hot spots 172a and 172b. By measuring the temperature signals of the hot spots 172a and 172b, a fail location near the hot spots 172a and 172b can be found.

Since the development board is used as the source of the measurement signal in the fault detection method of the measuring machine and semiconductor chip, the clock generator in the development board can generate faster signals, so more abnormal hot spots can be found in the physical property failure analysis. These abnormal hot spots can be observed through a microscope and their temperature can be measured by a probe. The operation is simple and can more effectively find the failure area that may appear when the semiconductor chip is operating than the traditional method.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications here without departing from the spirit and scope of the present disclosure.

100: measuring machine 110: chamber 120: development board 130: probe station 140: microscope 142: lens 150: circuit board 160a, 160b: probe 170: semiconductor chip 172a, 172b: hot spot 174: top 180: slot 190: cable S1, S2, S3, S4, S5, S6: steps

The disclosure is best understood from the following embodiments when read in conjunction with the accompanying illustrations. Note that various features are not drawn to scale in accordance with standard practice in the industry. In fact, the sizes of various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a schematic diagram of a measuring machine according to one embodiment of the disclosure. FIG. 2 is a side view of the vicinity of the lens of a microscope when the measuring machine of FIG. 1 is in use. FIG. 3 is a flow chart of a method for fault detection of a semiconductor chip according to one embodiment of the disclosure. FIG. 4 is a schematic diagram of the semiconductor chip of FIG. 2 before the cover is opened. FIG. 5 is a schematic diagram of the semiconductor chip of FIG. 4 after the cover is opened. Figure 6 shows a partially enlarged top view of the semiconductor chip in Figure 2 after the cover is opened.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100: measuring machine 110: chamber 120: development board 130: probe station 140: microscope 150: circuit board 160a, 160b: probe 170: semiconductor chip 190: cable

Claims (9)

A measuring machine includes: a chamber; a development board located outside the chamber; a probe stage located in the chamber; a microscope located in the chamber and above the probe stage and configured to obtain an image of a semiconductor chip and observe at least one hot spot of the semiconductor chip; a circuit board located on the probe stage and configured to electrically connect the semiconductor chip and the development board, wherein the semiconductor chip is located directly below a lens of the microscope; and two probes located above the probe stage and configured to contact the semiconductor chip, wherein the positions of the two probes are located according to the image obtained by the microscope on the semiconductor chip, and the positions of the two probes are located according to the hot spot observed by the microscope. The measuring machine as described in claim 1 further comprises: a cable extending from the circuit board in the cavity to the development board outside the cavity, and electrically connecting the development board and the circuit board. The measuring machine as described in claim 1 further comprises: a slot located on the circuit board and electrically connected to the circuit board, the slot being configured for inserting the semiconductor chip. A measuring machine as described in claim 3, wherein the slot is vertically aligned with the lens of the microscope. The measuring machine as described in claim 1, wherein the two probes are temperature probes. A semiconductor chip fault detection method includes: electrically connecting the semiconductor chip to a circuit board; placing the circuit board on a probe stage in a cavity, wherein a microscope is located in the cavity and above the probe stage, and the semiconductor chip is located directly below a lens of the microscope; electrically connecting the circuit board to a development board through a cable, wherein the development board is located outside the cavity; using the development board to provide an inspection signal to the semiconductor chip; locating the positions of two probes according to an image of the semiconductor chip obtained by the microscope, including: using the microscope to observe at least one hot spot of the semiconductor chip; and locating the positions of the two probes according to the hot spot in the image observed by the microscope, wherein the two probes are located above the probe stage; and using the two probes to measure a measurement signal of the semiconductor chip. The semiconductor chip fault detection method as described in claim 6 further comprises: Before electrically connecting the semiconductor chip to the development board, the semiconductor chip is uncovered. The semiconductor chip fault detection method as described in claim 6 further comprises: inserting the semiconductor chip into a slot, wherein the slot is electrically connected to the circuit board. A semiconductor chip fault detection method as described in claim 6, wherein using the two probes to measure the measurement signal on the semiconductor chip includes using the two probes to perform temperature measurement on the hot spot.

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