TWI884015B - Electrostatic discharge protection structure and circuit - Google Patents

Abstract

An electrostatic discharge protection structure including a substrate, a deep well, a gate structure, and an interconnect structure is provided. The deep well is disposed in the substrate. A first well, a second well, and a third well are disposed on the deep well. A first doped region, a second doped region, and a third doped region are disposed in the first well. The gate structure is disposed on the substrate and between the first and second doped regions. A fourth doped region is disposed in the second well. A fifth doped region and a sixth doped region are disposed in the third well. The interconnect structure is electrically connected to the gate structure, the second doped region, the third doped region, and the fourth doped regions. Each of the substrate, the first well, the third well, the third doped region, and the sixth doped region has a first conductivity type. Each of the deep well, the second well, the first doped region, the second doped region, the fourth doped region, and the fifth doped region has a second conductivity type.

Description

Electrostatic discharge protection structure and electrostatic discharge protection circuit

The present invention relates to an electrostatic discharge protection structure, and more particularly to an electrostatic discharge protection structure for reducing negative current.

Component damage caused by electrostatic discharge (ESD) has become one of the most important reliability issues for integrated circuit products. In particular, as the size continues to shrink to the sub-micron level, the gate oxide layer of metal oxide semiconductors is becoming thinner and thinner, making integrated circuits more susceptible to damage due to ESD.

In general industrial standards, the I/O pins of integrated circuit products must be able to pass the human body model electrostatic discharge test of more than 2000 volts and the mechanical model electrostatic discharge test of more than 200 volts. Therefore, in integrated circuit products, electrostatic discharge protection components must be installed near all input and output pads to protect the internal core circuit from electrostatic discharge current.

An embodiment of the present invention provides an electrostatic discharge protection structure, including a substrate, a deep well region, a first well region, a second well region, a third well region, a first doped region, a second doped region, a third doped region, a fourth doped region, a fifth doped region, a sixth doped region, a gate structure and an internal connection structure. The substrate has a first conductivity type. The deep well region is arranged in the substrate and has a second conductivity type. The first well region is arranged on the deep well region and has a first conductivity type. The second well region is arranged on the deep well region and has a second conductivity type. The third well region is arranged on the deep well region and has a first conductivity type. The first doped region is arranged in the first well region and has a second conductivity type. The second doped region is disposed in the first well region and has a second conductivity type. The third doped region is disposed in the first well region and has a first conductivity type. The gate structure is disposed on the substrate and is located between the first and second doped regions. The fourth doped region is disposed in the second well region and has a second conductivity type. The fifth doped region is disposed in the third well region and has a second conductivity type. The sixth doped region is disposed in the third well region and has a first conductivity type. The internal connection structure electrically connects the gate structure, the second, third, and fourth doped regions. The first doped region, the second doped region, the third doped region, and the gate structure constitute a metal oxide semiconductor field effect transistor. The fourth doped region, the fifth doped region and the sixth doped region form a bipolar junction transistor.

The present invention provides another electrostatic discharge protection circuit for protecting a core circuit, and includes a substrate, an N-type metal oxide semiconductor field effect transistor and a bipolar junction transistor. The N-type metal oxide semiconductor field effect transistor is formed on the substrate. The drain of the N-type metal oxide semiconductor field effect transistor is coupled to a first input-output pad. The bipolar junction transistor is formed on the substrate. The collector of the bipolar junction transistor is coupled to the gate, source and base of the N-type metal oxide semiconductor field effect transistor. The emitter and base of the bipolar junction transistor are coupled to a second input-output pad. The core circuit is coupled between the first and second input-output pads.

In order to make the purpose, features and advantages of the present invention more clearly understood, the following is a detailed description of the embodiments and the accompanying drawings. The present invention specification provides different embodiments to illustrate the technical features of different embodiments of the present invention. The configuration of each component in the embodiments is for illustration purposes only and is not intended to limit the present invention. In addition, the repetition of some of the figure numbers in the embodiments is for the purpose of simplifying the description and does not mean the correlation between different embodiments.

FIG. 1 is a schematic diagram of the electrostatic discharge protection structure of the present invention. As shown in the figure, the electrostatic discharge protection structure 100 includes a substrate 110, a deep well region 120, well regions W1-W3, doped regions 131-136 and a gate structure 140. The substrate 110 has a first conductivity type. The deep well region 120 is disposed in the substrate 110 and has a second conductivity type. The second conductivity type is different from the first conductivity type. In one possible embodiment, the first conductivity type is P type and the second conductivity type is N type. In another possible embodiment, the first conductivity type is N type and the second conductivity type is P type.

Well region W1 is disposed above deep well region 120 and has a first conductivity type. In one possible embodiment, the impurity concentration of well region W1 is higher than the impurity concentration of substrate 110. Well region W2 is disposed above deep well region 120 and is located between well regions W1 and W3. In this embodiment, well region W2 has a second conductivity type. The impurity concentration of well region W2 is greater than the impurity concentration of deep well region 120. Well region W3 is disposed above deep well region 120 and has a first conductivity type. In one possible embodiment, the impurity concentration of well region W3 is similar to the impurity concentration of well region W1.

Doped regions 131 and 132 are disposed in the well region W1 and have the second conductivity type. In this embodiment, the impurity concentration of doped region 131 is similar to the impurity concentration of doped region 132 and is higher than the impurity concentration of well region W2. Doped region 133 is disposed in the well region W1 and has the first conductivity type. In a possible embodiment, the impurity concentration of doped region 133 is greater than the impurity concentration of well region W1.

The gate structure 140 is located on the substrate 110 and between the doped regions 131 and 132. In the present embodiment, the gate structure 140 includes a gate electrode layer 141 and a gate interface layer 142. The gate interface layer 142 is formed on a portion of the surface of the substrate 110. The gate electrode layer 141 is disposed on the gate interface layer 142. In other embodiments, the ESD protection structure 100 further includes a resistive protective oxide (RPO) layer 150. The resistive protective oxide layer 150 overlaps a portion of the upper surface of the gate structure 140 and a portion of the upper surface of the doped region 131.

In some embodiments, the ESD protection structure 100 further includes lightly doped drain regions (LDD) LDD_1 and LDD_2. The lightly doped drain regions LDD_1 and LDD_2 are located in the well region W1 and have the second conductivity type. The lightly doped drain region LDD_1 surrounds the doped region 131. The lightly doped drain region LDD_2 surrounds the doped region 132. In a possible embodiment, the impurity concentration of the lightly doped drain region LDD_1 is similar to the impurity concentration of the lightly doped drain region LDD_2. In this example, the impurity concentration of the lightly doped drain region LDD_1 is lower than the impurity concentration of the doped region 131 , and the impurity concentration of the lightly doped drain region LDD_2 is lower than the impurity concentration of the doped region 132 .

In a possible embodiment, the doped regions 131-133 and the gate structure 140 form a metal-oxide-semiconductor field-effect transistor (MOSFET) T1. The doped region 131 serves as a drain of the metal-oxide-semiconductor field-effect transistor T1. The doped region 132 serves as a source of the metal-oxide-semiconductor field-effect transistor T1. The doped region 133 serves as a base of the metal-oxide-semiconductor field-effect transistor T1. The gate structure 140 serves as a gate of the metal-oxide-semiconductor field-effect transistor T1.

The present invention does not limit the type of the metal oxide semiconductor field effect transistor T1. In one possible embodiment, when the first conductivity type is P type and the second conductivity type is N type, the metal oxide semiconductor field effect transistor T1 is an N type metal oxide semiconductor field effect transistor. In another possible embodiment, when the first conductivity type is N type and the second conductivity type is P type, the metal oxide semiconductor field effect transistor T1 is a P type metal oxide semiconductor field effect transistor.

The doping region 134 is disposed in the well region W2 and has the second conductivity type. In the present embodiment, the impurity concentration of the doping region 134 is similar to the impurity concentration of the doping region 132 and is higher than the impurity concentration of the well region W2. The doping region 135 is disposed in the well region W3 and has the second conductivity type. In the present embodiment, the impurity concentration of the doping region 135 is similar to the impurity concentration of the doping region 134. The doping region 136 is disposed in the well region W3 and has the first conductivity type. In this embodiment, the impurity concentration of the doped region 136 is similar to the impurity concentration of the doped region 133 and higher than the impurity concentration of the well region W3.

In one possible embodiment, the doped regions 134-136 form a bipolar junction transistor (BJT) T2. The doped region 134 may serve as a collector of the BJT T2, the doped region 135 may serve as an emitter of the BJT T2, and the doped region 136 may serve as a base of the BJT T2. In some embodiments, when the first conductivity type is P-type and the second conductivity type is N-type, the BJT T2 is an NPN-type BJT.

In some embodiments, the ESD protection structure 100 further includes interconnect structures 161-164. The interconnect structure 161 electrically connects the doped region 131 and the input-output pad IO_1. The interconnect structure 162 electrically connects the gate structure 140 and the doped regions 132-134. In this embodiment, the interconnect structure 162 is not coupled to any input-output pad. Therefore, the voltage level of the gate structure 140 and the doped regions 132-134 is a floating level. The interconnect structure 163 electrically connects the doped regions 135, 136 and the input-output pad IO_2. In one possible embodiment, the input-output pad IO_1 receives a first operating voltage, and the input-output pad IO_2 receives a second operating voltage. In this example, the first operating voltage is greater than the second operating voltage. In some embodiments, the second operating voltage is a ground voltage.

In other embodiments, the ESD protection structure 100 further includes well regions W4, W5 and doped regions 137, 138. Well region W4 is disposed above the deep well region 120 and has a second conductivity type. Doped region 137 is disposed in well region W4 and has a second conductivity type. In a possible embodiment, the impurity concentration of doped region 137 is higher than the impurity concentration of well region W4 and is similar to the impurity concentration of doped region 131. The impurity concentration of well region W4 is similar to the impurity concentration of well region W2. In some embodiments, doped region 137 is electrically connected to the interconnect structure 162.

The well region W5 is disposed in the substrate 110 and has a first conductivity type. In one possible embodiment, the impurity concentration of the well region W5 is similar to the impurity concentration of the well region W3. The doped region 138 is disposed in the well region W5 and has a first conductivity type. In one possible embodiment, the impurity concentration of the doped region 138 is higher than the impurity concentration of the well region W5 and is similar to the impurity concentration of the doped region 136.

In some embodiments, the ESD protection structure 100 further includes an interconnect structure 164. The interconnect structure 164 electrically connects the doped region 138 and the input-output pad IO_3. In this example, the input-output pad IO_3 receives a third operating voltage. The third operating voltage may be equal to or less than the second operating voltage. In a possible embodiment, the third operating voltage is a ground voltage.

In other embodiments, the ESD protection structure 100 further includes isolation structures 171-176. The isolation structure 171 is located in the well region W1 and separates the doped regions 132 and 133. The isolation structure 172 overlaps a portion of the well region W1 and a portion of the well region W2 and separates the doped regions 133 and 134. The isolation structure 173 overlaps a portion of the well region W2 and a portion of the well region W3 and separates the doped regions 134 and 135. The isolation structure 174 is located in the well region W3 and separates the doped regions 135 and 136. The isolation structure 175 overlaps a portion of the well region W3 and a portion of the well region W4 and separates the doped regions 136 and 137. The isolation structure 176 overlaps a portion of the well region W4 and a portion of the well region W5, and separates the doped regions 137 and 138. In one possible embodiment, the isolation structures 171-176 are field oxide layers, but this is not intended to limit the present invention. In other embodiments, the isolation structures 171-176 may be other types of isolation structures, such as shallow trench isolation structures.

In the present embodiment, there is a distance S between the region R1 of the substrate 110 mapped to the doped region 135 and the region R2 of the substrate 110 mapped to the well region W2. The distance S is related to the breakdown voltage of the ESD protection structure 100. For example, when the distance S decreases, the breakdown voltage of the ESD protection structure 100 also decreases. In another possible embodiment, the distance S is related to the performance of the human body model (HBM) and the machine model (MM) of the ESD protection structure 100. When the distance S decreases, the HBM and MM performance of the ESD protection structure 100 are enhanced. In one possible embodiment, the distance S is greater than 0.7 micrometers (um). In another possible embodiment, the distance S is greater than or equal to 1 micrometer.

In this embodiment, the PN interface between the well region W1 and the doped region 131 is equivalent to a diode D1, the PN interface between the well regions W3 and W2 is equivalent to a diode D2, and the PN interface between the well regions W5 and W4 is equivalent to a diode D3. When a first electrostatic discharge voltage occurs at the input-output pad IO_1, and the input-output pads IO_2 and IO_3 receive a ground voltage, a first electrostatic discharge current flows from the input-output pad IO_1 into the doped region 131. Therefore, the diode D1 is reversely conducted. At this time, the voltage of the well region W1 rises, causing the metal oxide semiconductor field effect transistor T1 to conduct. The first electrostatic discharge current flows from the doped region 131, through the well region W1, the doped region 132, and the interconnect structure 162, into the doped region 134 and the well region W2. When the diode D2 is reversely conducted, the voltage of the well region W3 rises, causing the bipolar junction transistor T2 to conduct. Therefore, the first electrostatic discharge current flows from the well region W2, through the doped region 135, and is released to the input-output pad IO_2. In this embodiment, the doped region 131, the well region W1, the doped region 132, the interconnect structure 162, the doped region 134, the well regions W2, W3, and the doped region 135 constitute a discharge path (or a first discharge path). In this example, the first electrostatic discharge voltage is greater than the ground voltage.

When a second electrostatic discharge voltage occurs at the input-output pad IO_1, and the input-output pads IO_2 and IO_3 receive a ground voltage, a second electrostatic discharge current may be released to the input-output pad IO_2 through the diodes D1 and D2, or released to the input-output pad IO_3 through the diodes D1 and D3. In this example, the second electrostatic discharge voltage is less than the ground voltage.

For example, when a second electrostatic discharge voltage occurs at the input-output pad IO_1, and the input-output pads IO_2 and IO_3 receive a ground voltage, the second electrostatic discharge current enters the doped region 131 from the input-output pad IO_1. Therefore, the diode D1 is forward-conducted. The second electrostatic discharge current passes through the well region W1, the doped region 133, and the interconnect structure 162, and enters the doped region 134 and the well region W2. Since the diode D2 is forward-conducted, the second electrostatic discharge current enters the well region W3, passes through the doped region 131, and enters the input-output pad IO_2. In this example, the doped region 131, the well region W1, the doped region 133, the interconnect structure 162, the doped region 134, the well regions W2 and W3, and the doped region 136 form a discharge path (or a second discharge path).

In another possible embodiment, the second electrostatic discharge current may enter the doped region 137 and the well region W4 through the interconnect structure 162. At this time, since the diode D3 is forward-conducted, the second electrostatic discharge current enters the well region W5, passes through the doped region 138, and enters the input-output pad IO_3. In this example, the doped region 131, the well region W1, the doped region 133, the interconnect structure 162, the doped region 137, the well regions W4, W5, and the doped region 138 constitute another discharge path (or a third discharge path).

Since the ESD protection structure 100 includes the metal oxide semiconductor field effect transistor T1 and the bipolar junction transistor T2, the leakage current of the ESD protection structure 100 can be reduced under normal operation (no ESD event occurs). In addition, even if the input-output pad IO_1 receives a negative voltage, or the ESD protection structure 100 is in a high temperature environment, the leakage current of the ESD protection structure 100 can be reduced by integrating the metal oxide semiconductor field effect transistor T1 and the bipolar junction transistor T2.

FIG. 2A is a possible top view of the electrostatic discharge protection structure of the present invention. In this embodiment, FIG. 1 is a cross-sectional view of the semiconductor structure of FIG. 2A along the dotted line AA'. In FIG. 2, the doped region 133 is a ring-shaped structure surrounding the doped regions 131, 132, the gate electrode layer 141 and the impedance protection oxide layer 150. The doped regions 134-138 are strip structures located on the left periphery of the doped region 133.

FIG. 2B is another possible top view of the ESD protection structure of the present invention. In this embodiment, doped regions 134 to 138 are all ring-shaped structures, surrounding the metal oxide semiconductor field effect transistor T1. As shown in the figure, doped region 134 surrounds doped region 133. Doped region 135 surrounds doped region 134. Doped region 136 surrounds doped region 135. Doped region 137 surrounds doped region 136. Doped region 138 surrounds doped region 137.

FIG. 2C is another possible top view of the electrostatic discharge protection structure of the present invention. FIG. 2C is similar to FIG. 2A, except that the doped region 133 of FIG. 2A surrounds a single metal oxide semiconductor field effect transistor (i.e., T1), while the doped region 133 of FIG. 2C surrounds a plurality of metal oxide semiconductor field effect transistors. In one possible embodiment, the metal oxide semiconductor field effect transistors in the doped region 133 of FIG. 2C are connected in parallel to each other. In other embodiments, the structure of the multi-metal oxide semiconductor field effect transistor of FIG. 2C can be applied to FIG. 2B. In other words, the doped region 133 of FIG. 2C may be surrounded by doped regions 134 to 138.

FIG. 3 is a schematic diagram of the operating circuit of the present invention. As shown in the figure, the operating circuit 300 includes an electrostatic discharge protection circuit 310 and a core circuit 320. The electrostatic discharge protection circuit 310 and the core circuit 320 are connected in parallel between the input and output pads IO_1 and IO_2. The electrostatic discharge protection circuit 310 protects the core circuit 320 to prevent the electrostatic discharge current from the input and output pads IO_1 or IO_2 from entering the core circuit 320. In this embodiment, the electrostatic discharge protection circuit 310 is an equivalent circuit of the electrostatic discharge protection structure 100 of FIG. 1.

The electrostatic discharge protection circuit 310 includes a substrate 311, a metal oxide semiconductor field effect transistor T1 and a bipolar junction transistor T2. The metal oxide semiconductor field effect transistor T1 and the bipolar junction transistor T2 are formed on the substrate 311. In this embodiment, the input-output pad IO_3 serves as an electrical contact terminal of the substrate 311.

The drain of the metal oxide semiconductor field effect transistor T1 is coupled to the input-output pad IO_1. In the present embodiment, the metal oxide semiconductor field effect transistor T1 is an N-type metal oxide semiconductor field effect transistor. The collector of the bipolar junction transistor T2 is coupled to the gate, source and base of the metal oxide semiconductor field effect transistor T1. In a possible embodiment, the gate, source and base of the metal oxide semiconductor field effect transistor T1 are directly electrically connected to the collector of the bipolar junction transistor T2. In some possible embodiments, the gate, source and base of the MOSFET T1 and the collector of the BJT T2 are at a floating level. In addition, the emitter and base of the BJT T2 are coupled to the input/output pad IO_2. In this embodiment, the BJT T2 is an NPN BJT.

In one possible embodiment, the collector of the bipolar junction transistor T2 is disposed in an N-type well region (such as the well region W2 in FIG. 1). In this example, there is a distance between the region where the N-type well region is mapped to the substrate 310 and the region where the emitter of the bipolar junction transistor T2 (such as the doped region 135 in FIG. 1) is mapped to the substrate 310. The distance may be between 0.7 and 1 micron. In another possible embodiment, the distance is greater than or equal to 1 micron. In addition, the resistor R in FIG. 3 represents the equivalent impedance of the well region W3 in FIG. 1.

When the input-output pad IO_1 receives a first electrostatic discharge voltage and the input-output pad IO_2 receives a ground voltage, a first electrostatic discharge current passes through the diode D1 between the drain and the base of the metal oxide semiconductor field effect transistor T1. Therefore, the metal oxide semiconductor field effect transistor T1 is turned on. At this time, the first electrostatic discharge current flows through the diode D2 between the collector and the base of the bipolar junction transistor T2. Therefore, the bipolar junction transistor T2 is turned on, and the first electrostatic discharge current enters the input-output pad IO_2 from the input-output pad IO_1. In this embodiment, the first electrostatic discharge voltage is greater than the ground voltage.

When the input-output pad IO_1 receives a second electrostatic discharge voltage and the input-output pads IO_2 and IO_3 receive a ground voltage, a second electrostatic discharge current passes through a diode string. In one possible embodiment, the diode string is a diode D1 between the drain and the base of the metal oxide semiconductor field effect transistor T1 and a diode D2 between the collector and the base of the bipolar junction transistor T2. In another possible embodiment, the diode string is a diode D1 between the drain and the base of the metal oxide semiconductor field effect transistor T1 and a diode D3 between the collector of the bipolar junction transistor T2 and the substrate 311. In some embodiments, the second electrostatic discharge voltage is less than a ground voltage.

In other embodiments, the input-output pad IO_3 is directly electrically connected to the input-output pad IO_2. In another possible embodiment, the operating circuit 300 further includes a processing circuit 330. The processing circuit 330 is coupled between the input-output pads IO_2 and IO_3 to prevent the voltages of the input-output pads IO_2 and IO_3 from interfering with each other. In a possible embodiment, the processing circuit 330 includes diodes 331 and 332. The cathode of the diode 331 is coupled to the input-output pad IO_3, and the anode of the diode 331 is coupled to the input-output pad IO_2. The cathode of the diode 332 is coupled to the input-output pad IO_2, and the anode of the diode 332 is coupled to the input-output pad IO_3. In another possible embodiment, the processing circuit 330 includes at least one resistor. In this example, the resistor is coupled between the input-output pads IO_2 and IO_3.

It should be understood that when an element or layer is referred to as being "coupled" to another element or layer, it may be directly coupled or connected to the other element or layer, or have other elements or layers interposed therebetween. Conversely, if an element or layer is "connected" to another element or layer, there will be no other elements or layers interposed therebetween.

Unless otherwise defined, all terms herein (including technical and scientific terms) are generally understood by persons of ordinary skill in the art to which the present invention belongs. In addition, unless expressly stated, the definitions of terms in general dictionaries should be interpreted as being consistent with the meanings in articles in the relevant art, and should not be interpreted as ideal or overly formal. Although terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another. In the scope of the patent application, terms such as "first" and "second" are used as markers and are not intended to impose numerical requirements on their objects.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field may make some changes and modifications without departing from the spirit and scope of the present invention. For example, the system, device or method described in the embodiments of the present invention can be implemented in the form of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: ESD protection structure 110, 311: substrate 120: deep well area W1~W5: well area 131~138: doped area 140: gate structure 141: gate electrode layer 142: gate interface layer 150: impedance protection oxide layer LDD_1, LDD_2: lightly doped drain area T1: metal oxide semiconductor field effect transistor T2: bipolar junction transistor 161~164: interconnect structure IO_1~IO_3: input and output pads 171~176: isolation structure R1, R2: region S: distance D1~D3, 331, 332: diodes 300: operating circuit 310: electrostatic discharge protection circuit 320: core circuit 330: processing circuit

FIG. 1 is a schematic diagram of the electrostatic discharge protection structure of the present invention. FIG. 2A is a possible top view of the electrostatic discharge protection structure of the present invention. FIG. 2B is another possible top view of the electrostatic discharge protection structure of the present invention. FIG. 2C is another possible top view of the electrostatic discharge protection structure of the present invention. FIG. 3 is a schematic diagram of the operating circuit of the present invention.

100: Electrostatic discharge protection structure

110: Base

120: Sham Tseng District

W1~W5: Well area

131~138: Mixed area

140: Gate structure

141: Gate electrode layer

142: Gate interface layer

150: Impedance protection oxide layer

LDD_1, LDD_2: lightly doped drain region

T1: Metal oxide semiconductor field effect transistor

T2: Bipolar Junction Transistor

161~164: Internal link structure

IO_1~IO_3: Input and output pads

171~176: Isolation structure

R1, R2: Area

S: distance

D1~D3: diode

Claims (20)

An electrostatic discharge protection structure includes: a substrate having a first conductivity type; a deep well region disposed in the substrate and having a second conductivity type; a first well region disposed on the deep well region and having the first conductivity type; a second well region disposed on the deep well region and having the second conductivity type; a third well region disposed on the deep well region and having the first conductivity type; a first doped region disposed in the first well region and having the second conductivity type; a second doped region disposed in the first well region and having the second conductivity type; a third doped region disposed in the first well region and having the first conductivity type; a gate structure disposed on the substrate and between the first and second doped regions; A fourth doped region, disposed in the second well region and having the second conductivity type; A fifth doped region, disposed in the third well region and having the second conductivity type; A sixth doped region, disposed in the third well region and having the first conductivity type; and A first interconnect structure, electrically connecting the gate structure, the second, third and fourth doped regions, wherein: The first doped region, the second doped region, the third doped region and the gate structure constitute a metal oxide semiconductor field effect transistor, The fourth doped region, the fifth doped region and the sixth doped region constitute a bipolar junction transistor. The electrostatic discharge protection structure as described in claim 1, wherein there is a distance between the area where the fifth doped region is mapped to the substrate and the area where the second well region is mapped to the substrate. An electrostatic discharge protection structure as described in claim 2, wherein the distance is greater than 1 micron. The electrostatic discharge protection structure as described in claim 1 further includes: A second interconnect structure electrically connecting the fifth and sixth doping regions. The electrostatic discharge protection structure as described in claim 4, wherein: The fourth doped region is a first annular structure, the first annular structure surrounds the metal oxide semiconductor field effect transistor, The fifth doped region is a second annular structure, the second annular structure surrounds the fourth doped region, The sixth doped region is a third annular structure, the third annular structure surrounds the fifth doped region. The electrostatic discharge protection structure as described in claim 5 further includes: a fourth well region disposed on the deep well region and having the second conductivity type; a fifth well region disposed in the substrate and having the first conductivity type; a seventh doped region disposed in the fourth well region and having the second conductivity type; and an eighth doped region disposed in the fifth well region and having the first conductivity type, wherein the first interconnect structure is electrically connected to the seventh doped region. The electrostatic discharge protection structure as described in claim 6, wherein: The seventh doping region is a fourth annular structure, and the fourth annular structure surrounds the sixth doping region, The eighth doping region is a fifth annular structure, and the fifth annular structure surrounds the seventh doping region. The electrostatic discharge protection structure as described in claim 6, wherein: The first doped region is coupled to a first input-output pad, and the eighth doped region is coupled to a second input-output pad, When a first electrostatic discharge voltage occurs at the first input-output pad, and the second input-output pad and the second interconnect structure receive a ground voltage, a first electrostatic discharge current enters the first doped region from the first input-output pad, and is released to the second interconnect structure through a first discharge path, When a second electrostatic discharge voltage occurs at the first input-output pad, and the second input-output pad and the second interconnect structure receive the ground voltage, a second electrostatic discharge current is discharged to the second interconnect structure through a second discharge path or to the second input-output pad through a third discharge path. The first electrostatic discharge voltage is greater than the ground voltage, and the second electrostatic discharge voltage is less than the ground voltage. The electrostatic discharge protection structure as described in claim 8, wherein the first doped region, the first well region, the second doped region, the first interconnect structure, the fourth doped region, the second well region, the third well region and the fifth doped region constitute the first discharge path. The electrostatic discharge protection structure as described in claim 9, wherein the first doped region, the first well region, the third doped region, the first interconnect structure, the fourth doped region, the second well region, the third well region and the sixth doped region constitute the second discharge path. The electrostatic discharge protection structure as described in claim 9, wherein the first doped region, the first well region, the third doped region, the first interconnect structure, the seventh doped region, the fourth well region, the fifth well region and the eighth doped region constitute the third discharge path. An electrostatic discharge protection circuit is used to protect a core circuit, and includes: a substrate; an N-type metal oxide semiconductor field effect transistor formed on the substrate, the drain of the N-type metal oxide semiconductor field effect transistor is coupled to a first input-output pad; and a bipolar junction transistor formed on the substrate, the collector of the bipolar junction transistor is coupled to the gate, source and base of the N-type metal oxide semiconductor field effect transistor, the emitter and base of the bipolar junction transistor are coupled to a second input-output pad, wherein the core circuit is coupled between the first and second input-output pads. An electrostatic discharge protection circuit as described in claim 12, wherein when the first input-output pad receives a first electrostatic discharge voltage and the second input-output pad receives a ground voltage, a first electrostatic discharge current passes through a first diode between the drain and the base of the N-type metal oxide semiconductor field effect transistor and a second diode between the collector and the base of the bipolar junction transistor. An electrostatic discharge protection circuit as described in claim 13, wherein the first electrostatic discharge voltage is greater than the ground voltage. An electrostatic discharge protection circuit as described in claim 14, wherein the collector of the bipolar junction transistor is disposed in an N-type well region, and there is a distance between the region where the N-type well region is mapped to the substrate and the region where the emitter of the bipolar junction transistor is mapped to the substrate. An electrostatic discharge protection circuit as described in claim 15, wherein the distance is greater than 1 micron. An electrostatic discharge protection circuit as described in claim 15, wherein when the first input-output pad receives a second electrostatic discharge voltage and the second input-output pad and the substrate receive the ground voltage, a second electrostatic discharge current passes through the first diode and the second diode or a third diode between the collector of the bipolar junction transistor and the substrate. An electrostatic discharge protection circuit as described in claim 17, wherein the second electrostatic discharge voltage is less than the ground voltage. An electrostatic discharge protection circuit as described in claim 12, wherein the levels of the gate, source and base of the N-type metal oxide semiconductor field effect transistor and the collector of the bipolar junction transistor are at a floating level. An electrostatic discharge protection circuit as described in claim 19, wherein the gate, source and base of the N-type metal oxide semiconductor field effect transistor are directly electrically connected to the collector of the bipolar junction transistor.

Images