CN1324705C - Integrated circuits that avoid latch-up - Google Patents

Abstract

An integrated circuit capable of avoiding latch-up effect comprises an internal circuit arranged on a substrate and including at least one parasitic SCR structure; at least one ESD protection component and at least one active region, which are arranged on the substrate and coupled with a bonding pad; at least one first shunt diode having an anode coupled to the bonding pad and a cathode coupled to a first voltage source; at least one second shunt diode having a cathode coupled to the bonding pad and an anode coupled to a second voltage source, wherein the distance between the first and second shunt diodes and the internal circuit and the ESD protection device and the active region connected to the bonding pad is not less than 150 μm; and a guard ring surrounding the first and second shunt diodes.

Description

Integrated circuits that avoid latch-up

technical field

The invention relates to an integrated circuit, especially an integrated circuit which can avoid latch-up effect.

Background technique

Latchup is a very important reliability problem in CMOS IC, and it is a low-impedance state formed by the conduction of a parasitic PNPN (silicon-controlled rectifier, SCR) structure. Since there is a low parallel impedance between the power line and ground when latch-up occurs, a large amount of power line current will exist between the power lines. If this current is not limited, this will cause logic errors, circuit malfunctions, or irreversible damage to the IC. Unfortunately, because P+ of PMOS, NWELL of NMOS, P substrate, N+ will form the structure of PNPN SCR, and this parasitic SCR structure will be generated in the CMOS process.

There are many factors that can cause latch-up in CMOS, however, the most obvious are substrate currents generated by hot-carrier effects during IC operation, and/or by The forward current of the parasitic diode caused by noise.

Most of the substrate current generated by the latch-up effect is injected through the parasitic diode Dp formed by the on-chip electrostatic discharge (ESD) protection circuit 14 , as shown in FIG. 1 . The parasitic SCR structure 12 is turned on due to the conduction of the parasitic p+/nwe11/p-sub and nwe11/psub/n+ transistors. And if the voltage vbe across the base-emitter junction is greater than 0.7v, the two transistors will be turned on, and this voltage depends on the voltage drop (IR drop) on the well/sub resistor. Therefore, in order to prevent the occurrence of the latch-up effect, it is necessary to reduce the parasitic resistance of the well/substrate or the gain of the parasitic pnp/npn transistor.

Traditional solutions to latch-up and their disadvantages:

1. The process technology prevents the latch-up effect. The epitaxial CMOS can provide a smaller parasitic resistance of the well region/substrate, and the trench isolation and SOI can reduce the coupling effect of the parasitic NPN/PNP transistor, so it can Used to prevent latch-up. However, this process will increase process complexity and manufacturing cost.

2. The layout technology prevents the latch-up effect. The guard ring is the most commonly used method to increase the resistance of the latch-up effect. It can also decouple the parasitic bicarrier transistors, and it can be used inside the CMOS Before the latch-up effect occurs in the circuit, the injected carriers are gathered. In other words, increasing the potential contact (well/sub pickup contact) of the well region/substrate and reducing the distance between the doped region of the component and the potential contact (pickup contact) can also reduce the well/sub pickup contact that will increase the latch-up effect capability. The parasitic resistance of the substrate. However, they occupy wafer layout area and increase chip size, and under certain layout constraints, adding guard rings or adding pickup contacts may be difficult. In addition, another method is to increase the distance between the I/O injector and the internal circuit, but this will greatly increase the size of the entire chip, and is often limited in use.

3. Prevent the latch-up effect by circuit technology, propose a latch-up effect detection circuit in US Patent No. 5,942,932 proposed by shen, to measure the change of the voltage level of the well region/substrate (well/sub), and Activation is used to pull the well/substrate voltage level back to its original level when latch-up occurs. This approach still increases circuit complexity and layout space.

Therefore, a practical and easy-to-implement protection method is needed to reduce the occurrence of the latch-up effect under special circumstances where it is impossible to add a protection ring or increase the potential contact near the internal circuit.

Contents of the invention

In view of this, the primary objective of the present invention is to provide an integrated circuit capable of avoiding latch-up effect, and reduce the occurrence of latch-up effect by reducing the influence of the trigger source of the latch-up effect.

To achieve the above object, the present invention provides an integrated circuit that can avoid latch-up effect. In this circuit, an internal circuit, disposed on a substrate, contains at least one parasitic SCR structure. At least one ESD protection component and active area are arranged on the substrate and coupled to the bonding pad; at least one first shunt diode has an anode coupled to the bonding pad, and a cathode coupled to a first voltage source. At least one second shunt diode has a cathode coupled to the bonding pad, and an anode coupled to a second voltage source, and the first and second shunt diodes are connected to the internal circuit, and the ESD protection components connected to the bonding pad and have The distance between the source regions is not less than 150 microns. A guard ring is used to surround the first and second shunt diodes.

The advantage of the present invention is that the trigger level for triggering the latch-up effect is increased, thereby reducing the chance of the latch-up effect occurring.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, a preferred embodiment will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a conventional integrated circuit.

FIG. 2 is a schematic diagram of the latch-up-avoiding integrated circuit of the present invention.

Detailed ways

There are many factors that can cause latch-up in CMOS, however, the most obvious ones are substrate currents generated by hot carrier effects during IC operation, and/or caused by noise present on pads The forward current of the parasitic diode. And most of the substrate current generated by the latch-up effect is injected through the parasitic diode formed by the electrostatic discharge (ESD) protection circuit on the chip.

Unlike the prior art, the present invention uses a passive method of prohibiting conduction of the parasitic SCR to prevent the occurrence of latch-up effect. The spirit of the present invention is to reduce the influence of the trigger source of the latch-up effect by adding a shunt diode as the shunt path of the substrate current without changing the layout of the original internal circuit and ESD protection components, thereby reducing the chance of the latch-up effect occurring .

FIG. 2 is used to illustrate the method for avoiding the latch-up effect of the internal circuit of the present invention. The present invention arranges shunt diodes (D1, D2) on a substrate 26 having an internal circuit 20, active region 18, a first external circuit 24, and an ESD protection component 14; wherein the shunt diodes (D1, D2) are connected to the internal The distance (eg X1, X2) between the circuit 20 and the active area 18 connected to the bond pad 16 and the ESD protection device 14 is not less than 150 microns. When an overcurrent occurs on the bonding pad 16, the shunt diodes (D1, D2) serve as an additional current path to effectively reduce the substrate current injected by the ESD protection device 14, thus avoiding the occurrence of parasitic SCR structures 12 in the internal circuit. the latch-up effect.

In the present invention, the "trigger level" is defined as the maximum current level injected from the bonding pad 16 into the internal circuit 20 before the latch-up effect occurs. Furthermore, according to Kirchhoff's law, when there are shunt diodes ( D1 , D2 ), the injected current on the bonding pad 16 will be shared by the ESD protection device 14 and the shunt diodes ( D1 , D2 ). Therefore, the substrate current injected by the ESD protection device 14 into the internal circuit 20 will be effectively reduced, that is, the trigger level for triggering the latch-up effect will increase as the number of shunt diodes increases. In other words, the present invention increases the trigger level for triggering latch-up, thereby reducing the chance of latch-up occurring.

And in the present invention, the shunt diodes (D1, D2) can be arranged on the free space far away from the bonding pad 16, even in the special case where the layout space near the bonding pad 16 is not enough to increase the guard ring, it can still The chance of latch-up effect is reduced.

In addition, the shunt diodes ( D1 , D2 ) are not conducting during normal circuit operation time, but are conducting when noise or overshoot/undershoot voltages appear on the bonding pad 16 . In the present invention, the shunt diode ( D1 , D2 ) is a low voltage diode (diode) or a high voltage diode (diode) with a double-diffused-drain structure to increase the breakdown voltage. Alternatively, the shunt diodes ( D1 , D2 ) can be parasitic diodes formed by an external ESD protection component 14 , such as NMOS or PMOS transistors with gates grounded, floating or connected to an RC circuit. To avoid inducing latch-up of parasitic SCRs in the first external circuit 24 adjacent to the shunt diodes (D1, D2), the shunt diodes (D1, D2) are connected to the first external circuit 24 on the substrate that is not connected to the bonding pad 16. The distance X3 is more than 80 micrometers (μm).

Furthermore, in the present invention a suitable guard ring 22 is used to surround the shunt diodes (D1, D2). Due to the presence of the guard ring 22, the carriers injected by the shunt diodes (D1, D2) are collected and removed before they can cause a latch-up effect of another nearby parasitic SCR. In the presence of the surrounding guard ring 22, in order to avoid inducing latch-up of parasitic SCRs in the first external circuit 24 adjacent to the shunt diodes (D1, D2), the shunt diodes (D1, D2) are connected to the unconnected The distance between the first external circuit 24 of the bond pads 16 is at least greater than 40 micrometers (μm).

As shown in FIG. 2 , the present invention is an integrated circuit that can avoid latch-up effect. In this integrated circuit, an internal circuit 20 , disposed on a substrate 26 , includes a parasitic SCR structure 12 . The ESD protection device 14 and the active region 18 are disposed on the substrate 26 and coupled to the bonding pad 16 . The first shunt diode D1 has an anode electrically coupled to the bonding pad 16 and a cathode electrically coupled to a first voltage source Vdd. The second shunt diode D2 has a cathode electrically coupled to the bonding pad 16 and an anode coupled to a second voltage source Vss, and the first and second shunt diodes D1, D2 are connected to the internal circuit 20 and the bonding pad 16 The distance (X1, X2) between the ESD protection component 14 and the active region 18 is not less than 150 microns (μm). A guard ring 22 surrounds the first and second shunt diodes D1, D2, before the carriers injected by the shunt diodes (D1, D2) cause a latch-up effect of another parasitic SCR in a first external circuit 24 , gather and remove the carriers injected by the shunt diodes (D1, D2). The shunt diodes ( D1 , D2 ) can be low-voltage diodes or high-voltage diodes with a double-diffused-drain structure to increase breakdown voltage. Alternatively, the shunt diodes ( D1 , D2 ) can be parasitic diodes formed by an external ESD protection device 14 , such as NMOS or PMOS with a gate grounded, floating or connected to an RC circuit. To avoid inducing latch-up of parasitic SCRs in the first external circuit 24 adjacent to the shunt diodes (D1, D2), the shunt diodes (D1, D2) are connected to the first external circuit 24 on the substrate that is not connected to the bonding pad 16. The distance X3 is more than 40 micrometers (μm).

According to Kirchhoff's law, when the shunt diodes ( D1 , D2 ) exist, the current injected on the bonding pad 16 will be shared by the ESD protection device 14 and the shunt diodes ( D1 , D2 ). Therefore, the substrate current injected by the ESD protection device 14 into the internal circuit 20 will be effectively reduced, that is, the trigger level for triggering the latch-up effect will increase as the number of shunt diodes increases. In other words, the present invention increases the trigger level for triggering latch-up, thereby reducing the chance of latch-up occurring.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The protection scope of the invention should be determined by the scope defined in the claims.

Claims (9)

1, a kind of integrated circuit of avoiding latch-up is characterized in that comprising:

One internal circuit is arranged on the substrate, contains at least one parasitic SCR structure;

At least one active area is arranged on this substrate, is coupled to a joint sheet; And

At least one shunt diode couples this joint sheet, and this shunt diode and this internal circuit and the distance that is connected between the active area of this joint sheet are not less than 150 microns; Wherein this shunt diode as a shunt paths, produces latch-up so as to avoiding this parasitism SCR structure when a big electric current comes across this joint sheet.

2, the integrated circuit of avoiding latch-up according to claim 1, it is characterized in that: comprise that more one first external circuit is arranged on this substrate, be not connected, and the distance between this shunt diode and this first external circuit is not less than 80 microns with this joint sheet.

3, the integrated circuit of avoiding latch-up according to claim 1 is characterized in that: more comprise a protective ring, around this shunt diode.

4, the integrated circuit of avoiding latch-up according to claim 3, it is characterized in that: comprise that more one first external circuit is arranged on this substrate, be not connected, and the distance between this shunt diode and this first external circuit is not less than 40 microns with this joint sheet.

5, the integrated circuit of avoiding latch-up according to claim 1 is characterized in that: wherein this shunt diode is one to have the diode of two-step diffusion structure.

6, the integrated circuit of avoiding latch-up according to claim 1 is characterized in that: wherein this shunt diode is a parasitic diode.

7, a kind of integrated circuit of avoiding latch-up is characterized in that comprising:

One internal circuit is arranged on the substrate, contains at least one parasitic SCR structure;

At least one esd protection assembly is arranged on this substrate, and is coupled to a joint sheet;

At least one active area is arranged on this substrate, couples this joint sheet;

At least one first shunt diode has an anode and couples this joint sheet, and a negative electrode couples one first voltage source;

At least one second shunt diode, have a negative electrode and couple this joint sheet, and one anode couple one second voltage source, and this first, second shunt diode and this internal circuit and the esd protection assembly and the distance between the active area that are connected to this joint sheet are not less than 150 microns; And

One protective ring is around above-mentioned first, second shunt diode.

8, the integrated circuit of avoiding latch-up according to claim 7, it is characterized in that: comprise that more at least one first external circuit is arranged on this substrate, and be not connected with this joint sheet, the distance between this first, second shunt diode and this first external circuit is not less than 40 microns.

9, the integrated circuit of avoiding latch-up according to claim 7 is characterized in that: wherein this first, second shunt diode respectively is one to have the diode of two-step diffusion structure.

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