TWI886865B - Electrostatic discharge protection circuit and structure - Google Patents

Abstract

An electrostatic discharge protection circuit including a first PNP BJT, a first resistor, a second PNP BJT, a diode, a specifit BJT and a second resistor is provided. The first PNP BJT is coupled to a first power pad and a second pad. The first resistor is coupled between the first power pad and the base of the first PNP BJT. The emitter of the second PNP BJT is coupled to the second power pad. The collector of the second PNP BJT is coupled to a third power pad. The cathode of the diode is coupled to the first power pad and the base of the second PNP BJT. The anode of the diode is coupled to the third power pad. The specific BJT is coupled between the first and second power pads. The second resistor is coupled between the emitter and the base of the specific BJT. When an ESD event occurs, the first PNP BJT and the specific BJT are turned on so that an ESD current passes through the first PNP BJT and the specific BJT.

Description

Electrostatic discharge protection circuit and electrostatic discharge protection structure

The present invention relates to an electrostatic discharge protection circuit, in particular to an electrostatic discharge protection circuit having a PNP type bipolar junction transistor.

Component damage caused by electrostatic discharge (ESD) has become one of the most important reliability issues for integrated circuit products. In particular, as the size continues to shrink to the sub-micron level, the gate oxide layer of metal oxide semiconductors is becoming thinner and thinner, and integrated circuits are more likely to be damaged by electrostatic discharge. In general industrial standards, the input and output pins (I/O pins) of integrated circuit products must be able to pass human body model electrostatic discharge tests of more than 2000 volts and mechanical model electrostatic discharge tests of more than 200 volts.

An embodiment of the present invention provides an electrostatic discharge protection circuit for protecting a core circuit, and includes a first PNP bipolar junction transistor, a first resistor, a second PNP bipolar junction transistor, a diode, a specific bipolar junction transistor, and a second resistor. The emitter of the first PNP bipolar junction transistor is coupled to a first power pad, and the collector thereof is coupled to a second power pad. The first resistor is coupled between the first power pad and the base of the first PNP bipolar junction transistor. The emitter of the second PNP bipolar junction transistor is coupled to the second power pad, and the collector thereof is coupled to a third power pad. The cathode of the diode is coupled to the first power pad and the base of the second PNP type bipolar junction transistor, and the anode thereof is coupled to the third power pad. The specific bipolar junction transistor is coupled between the first and second power pads. The second resistor is coupled between an emitter and a base of the specific bipolar junction transistor. When an electrostatic discharge event occurs, the first PNP type bipolar junction transistor and the specific bipolar junction transistor are turned on, so that an electrostatic discharge current flows through the first PNP type bipolar junction transistor and the specific bipolar junction transistor.

The present invention further provides an electrostatic discharge protection structure, including a P-type substrate, a deep N-type well region, a first well region, a first P-type doped region, a second well region, a second P-type doped region, a third well region, a third P-type doped region, a fourth well region, a fourth P-type doped region, a fifth well region, a specific doped region and an N-type doped region. The deep N-type well region is arranged in the P-type substrate. The first well region is arranged on the deep N-type well region. The first P-type doped region is arranged in the first well region. The second well region is arranged on the deep N-type well region. The second P-type doped region is arranged in the second well region. The third well region is arranged on the deep N-type well region. The third P-type doped region is arranged in the third well region. The fourth well region is arranged on the deep N-type well region. The fourth P-type doped region is disposed in the fourth well region. The fifth well region is disposed on the deep N-type well region. The specific doped region is disposed in the fourth or fifth well region. The N-type doped region is disposed in the fifth well region. The conductivity type of the first, third and fourth well regions is P type. The conductivity type of the second and fifth well regions is N-type.

100, 200: Operating system

110, 210: Electrostatic discharge protection circuit

120, 220: core circuit

121~123: Circuit

PD_1~PD_3: Power pad

VH, VL, VSUB: operating voltage

PNP_1~PNP_5: PNP type bipolar junction transistor

NPN_1, NPN_2: NPN type bipolar junction transistor

R_1~R_3: resistance

DD: diode

111, 211: Specific bipolar junction transistor

400A, 400B, 600A, 600B, 800A, 800B: Electrostatic discharge protection structure

DS1~DS4: distance

P1~P7, P4_1, P4_2: P-type doping area

N1~N3, N3_1, N3_2: N-type doped region

W1~W12: Well area

300: P-type substrate

310: Deep N-type well area

330, 340, 350, 610, 620, 630: internal link structure

S_1~S_13: Insulation structure

Figure 1 is a schematic diagram of the operating system of the present invention.

Figure 2 is another schematic diagram of the operating system of the present invention.

Figure 3A is a top view of the electrostatic discharge protection structure of the electrostatic discharge protection circuit of the present invention.

Figure 3B is another top view of the electrostatic discharge protection structure of the electrostatic discharge protection circuit of the present invention.

Figure 4A is a cross-sectional view of the ESD protection structure in Figure 3A along the dotted lines AA’ and BB’.

Figure 4B is another cross-sectional view of the ESD protection structure in Figure 3B along the dotted lines AA’ and BB’.

Figure 5A is another top view of the electrostatic discharge protection structure of the electrostatic discharge protection circuit of the present invention.

Figure 5B is another top view of the electrostatic discharge protection structure of the electrostatic discharge protection circuit of the present invention.

Figure 6A is a cross-sectional view of the ESD protection structure of Figure 5A along the dotted lines CC’ and DD’.

Figure 6B is another cross-sectional view of the ESD protection structure in Figure 5B along the dotted lines CC’ and DD’.

Figure 7A is another top view of the electrostatic discharge protection structure of the electrostatic discharge protection circuit of the present invention.

Figure 7B is another top view of the electrostatic discharge protection structure of the electrostatic discharge protection circuit of the present invention.

Figure 8A is a cross-sectional view of the ESD protection structure of Figure 7A along the dotted lines EE’ and FF’.

Figure 8B is another cross-sectional view of the ESD protection structure in Figure 7B along the dotted lines EE’ and FF’.

In order to make the purpose, features and advantages of the present invention more clearly understandable, the following examples are specifically cited and detailed descriptions are made in conjunction with the attached drawings. This invention specification provides different examples to illustrate the technical features of different implementations of the present invention. Among them, the configuration of each component in the embodiment is for illustrative purposes and is not used to limit the present invention. In addition, the partial repetition of the figure numbers in the embodiment is for the purpose of simplifying the description and does not mean the correlation between different embodiments.

FIG. 1 is a schematic diagram of the operating system of the present invention. As shown in the figure, the operating system 100 includes an electrostatic discharge protection circuit 110 and a core circuit 120. The electrostatic discharge protection circuit 110 and the core circuit 120 are coupled to the power pads PD_1~PD_3. In this embodiment, the electrostatic discharge protection circuit 110 is used to protect the core circuit 120 to prevent the electrostatic discharge current from any of the power pads PD_1~PD_3 from entering and damaging the core circuit 120.

In one possible embodiment, the core circuit 120 includes circuits 121 to 123. Circuit 121 is coupled between power pads PD_1 and PD_2. Circuit 122 is coupled between power pads PD_2 and PD_3. Circuit 123 is coupled between power pads PD_1 and PD_3. The present invention does not limit the number of circuits in the core circuit 120. In one possible embodiment, the core circuit 120 has more or fewer circuits. Each circuit is coupled between at least two power pads.

When an electrostatic discharge event does not occur, the operating system 100 operates in a normal mode. In the normal mode, the electrostatic discharge protection circuit 110 does not operate. At this time, the power pad PD_1 may receive an operating voltage VH, the power pad PD_2 may receive an operating voltage VL, and the power pad PD_3 may receive an operating voltage VSUB. The circuit 121 operates according to the operating voltage VH and the operating voltage VL. The circuit 122 operates according to the operating voltage VL and the operating voltage VSUB. The circuit 123 operates according to the operating voltage VH and the operating voltage VSUB. In a possible embodiment, the operating voltage VH is greater than the operating voltage VL, and the operating voltage VL is greater than the operating voltage VSUB.

When an electrostatic discharge event occurs, the operating system 100 operates in a protection mode. In the protection mode, the electrostatic discharge protection circuit 110 releases the electrostatic discharge current from any one of the power pads PD_1 to PD_3 to prevent the electrostatic discharge current from entering the core circuit 120. For example, when an electrostatic discharge event occurs at the power pad PD_1, and the power pads PD_2 and PD_3 are coupled to the ground, the electrostatic discharge protection circuit 110 provides a conduction path so that the electrostatic discharge current starts from the power pad PD_1, passes through the electrostatic discharge protection circuit 110, and enters the power pads PD_2 and PD_3.

In this embodiment, the electrostatic discharge protection circuit 110 includes PNP type bipolar junction transistors PNP_1, PNP_2, resistors R_1, R_2, a diode DD and a specific bipolar junction transistor 111. In some embodiments, the PNP type bipolar junction transistors PNP_1, PNP_2, resistors R_1, R_2, a diode DD and the specific bipolar junction transistor 111 share the same substrate.

The emitter of the PNP bipolar junction transistor PNP_1 is coupled to the power pad PD_1. The collector of the PNP bipolar junction transistor PNP_1 is coupled to the power pad PD_2. The resistor R_1 is coupled between the power pad PD_1 and the base of the PNP bipolar junction transistor PNP_1.

The emitter of the PNP bipolar junction transistor PNP_2 is coupled to the power pad PD_2. The collector of the PNP bipolar junction transistor PNP_2 is coupled to the power pad PD_3. The base of the PNP bipolar junction transistor PNP_2 is coupled to the power pad PD_1. The cathode of the diode DD is coupled to the power pad PD_1. The anode of the diode DD is coupled to the power pad PD_3.

The specific bipolar junction transistor 111 is coupled between power pads PD_1 and PD_2. In the present embodiment, the specific bipolar junction transistor 111 is a PNP type bipolar junction transistor PNP_3. In this example, the emitter of the PNP type bipolar junction transistor PNP_3 is coupled to the power pad PD_1. The collector of the PNP type bipolar junction transistor PNP_3 is coupled to the power pad PD_2. The resistor R_2 is coupled between the emitter and the base of the PNP type bipolar junction transistor PNP_3.

When an electrostatic discharge event occurs at power pad PD_1 and power pads PD_2 and PD_3 are coupled to ground, the parasitic diode between the base and collector of PNP-type bipolar junction transistor PNP_1 and the parasitic diode between the base and collector of PNP-type bipolar junction transistor PNP_3 are reversely conducted, so PNP-type bipolar junction transistors PNP_1 and PNP_3 are turned on, causing an electrostatic discharge current to start from power pad PD_1, flow through PNP-type bipolar junction transistors PNP_1 and PNP_3, and enter power pads PD_2 and PD_3.

In some embodiments, when the PNP bipolar junction transistor PNP_1 is turned on, the PNP bipolar junction transistor PNP_1 is equivalent to a first on-resistance. Similarly, when the PNP bipolar junction transistor PNP_3 is turned on, the PNP bipolar junction transistor PNP_3 is equivalent to a second on-resistance. Since the first on-resistance is connected in parallel with the second on-resistance, the impedance of the overall on-resistance of the electrostatic discharge protection circuit 110 is reduced. Since the electrostatic discharge current flows into the electrostatic discharge protection circuit 110, it can be ensured that the core circuit 120 will not be damaged by the electrostatic discharge current.

In other embodiments, the electrostatic discharge protection circuit 110 further includes a parasitic PNP bipolar junction transistor PNP_4. The parasitic PNP bipolar junction transistor PNP_4 shares the same substrate with the PNP bipolar junction transistor PNP_1. The base of the parasitic PNP bipolar junction transistor PNP_4 is coupled to the base of the PNP bipolar junction transistor PNP_1. The emitter of the parasitic PNP bipolar junction transistor PNP_4 is coupled to the power pad PD_1. The collector of the parasitic PNP bipolar junction transistor PNP_4 is coupled to the power pad PD_2.

When an electrostatic discharge event occurs, the parasitic diode between the base and collector of the parasitic PNP type bipolar junction transistor PNP_4 is reversely conducted, so the parasitic PNP type bipolar junction transistor PNP_4 is turned on. Therefore, the electrostatic discharge current passes through the parasitic PNP type bipolar junction transistor PNP_4, the PNP type bipolar junction transistor PNP_1 and PNP_3. At this time, the parasitic PNP type bipolar junction transistor PNP_4 is equivalent to a third conduction resistor. Since the first to third conduction resistors are connected in parallel to each other, the impedance of the overall conduction resistor of the electrostatic discharge protection circuit 110 can be greatly reduced to ensure that the electrostatic discharge current does not flow into the core circuit 120.

FIG. 2 is another schematic diagram of the operating system of the present invention. The operating system 200 includes an electrostatic discharge protection circuit 210 and a core circuit 220. The electrostatic discharge protection circuit 210 and the core circuit 220 are coupled to the power pads PD_1 to PD_3. In this embodiment, the electrostatic discharge protection circuit 210 protects the core circuit 220 to prevent the electrostatic discharge current from the power pads PD_1 to PD_3 from entering the core circuit 220. Since the characteristics of the core circuit 220 are similar to those of the core circuit 120, they will not be described in detail.

The electrostatic discharge protection circuit 210 includes PNP type bipolar junction transistors PNP_1, PNP_2, resistors R_1, R_2, a diode DD and a specific bipolar junction transistor 211. Since the characteristics of the PNP type bipolar junction transistors PNP_1, PNP_2, resistors R_1, R_2 and diode DD have been described above, they will not be described in detail.

In the present embodiment, the specific bipolar junction transistor 211 is an NPN bipolar junction transistor NPN_1. The collector of the NPN bipolar junction transistor NPN_1 is coupled to the power pad PD_1. The emitter of the NPN bipolar junction transistor NPN_1 is coupled to the power pad PD_2. The resistor R_2 is coupled between the base and the emitter of the NPN bipolar junction transistor NPN_1. In some embodiments, the NPN bipolar junction transistor NPN_1 and the PNP bipolar junction transistor PNP_1 share the same substrate.

In some embodiments, the electrostatic discharge protection circuit 210 further includes a parasitic PNP bipolar junction transistor PNP_5, a parasitic NPN bipolar junction transistor NPN_2, and a parasitic resistor R_3. The base of the parasitic PNP bipolar junction transistor PNP_5 is coupled to the base of the PNP bipolar junction transistor PNP_2. The emitter of the parasitic PNP bipolar junction transistor PNP_5 is coupled to the power pad PD_1. The collector of the parasitic PNP bipolar junction transistor PNP_5 is coupled to the base of the NPN bipolar junction transistor NPN_1. The parasitic resistor R_3 is coupled between the collector of the parasitic PNP bipolar junction transistor PNP_5 and the power pad PD_2.

The base of the parasitic NPN bipolar junction transistor NPN_2 is coupled to the base of the NPN bipolar junction transistor NPN_1. The emitter of the parasitic NPN bipolar junction transistor NPN_2 is coupled to the power pad PD_2. The collector of the parasitic NPN bipolar junction transistor NPN_2 is coupled to the base of the PNP bipolar junction transistor PNP_1. In the present embodiment, the parasitic PNP bipolar junction transistor PNP_5 and the parasitic NPN bipolar junction transistor NPN_2 form a silicon controlled rectifier (SCR). In some embodiments, the parasitic PNP bipolar junction transistor PNP_5, the parasitic NPN bipolar junction transistor NPN_2, the PNP bipolar junction transistor PNP_1, and the NPN bipolar junction transistor NPN_1 share the same substrate.

When an electrostatic discharge event occurs at the power pad PD_1, and the power pads PD_2 and PD_3 are coupled to the ground, a first parasitic diode between the base and the collector of the PNP bipolar junction transistor PNP_1, a second parasitic diode between the base and the collector of the NPN bipolar junction transistor NPN_1, and a third parasitic diode between the base and the collector of the parasitic PNP bipolar junction transistor PNP_5 are reversely conducted, so the PNP bipolar junction transistor PNP_1, the NPN bipolar junction transistor NPN_1, the parasitic PNP bipolar junction transistor PNP_5, and the parasitic NPN bipolar junction transistor NPN_2 are turned on. Therefore, an electrostatic discharge current is discharged from the power pad PD_1 to the ground.

FIG. 3A is a top view of the ESD protection structure of the ESD protection circuit 110 of the present invention. FIG. 4A is a cross-sectional view of the ESD protection structure of FIG. 3A along the dotted lines AA’ and BB’. FIG. 4A shows that the ESD protection structure 400A includes a P-type substrate 300, a deep N-type well region (DNW) 310, well regions W1~W5, doped regions P1~P5 and N1. The deep N-type well region 310 is disposed in the P-type substrate 300. The well regions W1~W5 are disposed on the deep N-type well region 310. In this embodiment, the conductivity type of the well regions W1, W3 and W4 is P-type, and the conductivity type of the well regions P2 and P5 is N-type. In this example, the impurity concentrations of well regions W1, W3, and W4 are similar and higher than the impurity concentration of the P-type substrate 300, and the impurity concentrations of well regions W2 and W5 are similar and higher than the impurity concentration of the deep N-type well region 310.

Doping region P1 is disposed in well region W1. Doping region P2 is disposed in well region W2. Doping region P3 is disposed in well region W3. Doping region P4 is disposed in well region W4. Doping region P5 is disposed in well region W5. In this embodiment, the conductivity type of doping regions P1~P5 is P type. The impurity concentrations of doping regions P1~P5 are similar and higher than the impurity concentration of well region W1. Doping region N1 is disposed in well region W5. In this embodiment, the conductivity type of doping region N1 is N type. The impurity concentration of doping region N1 is higher than the impurity concentration of well region W5.

In other embodiments, the ESD protection structure 400A further includes a well region W6 and a doped region P6. The well region W6 is disposed in the P-type substrate 300. The doped region P6 is disposed in the well region W6. In this example, the conductivity type of the well region W6 and the doped region P6 is P-type. The impurity concentration of the doped region P6 is higher than the impurity concentration of the well region W6. The impurity concentration of the well region W6 is similar to the impurity concentration of the well region W1. The impurity concentration of the doped region P6 is similar to the impurity concentration of the doped region P1.

The present invention does not limit the type of well regions W1~W6. When the impurity concentration of well regions W1~W6 is relatively low (such as lower than a threshold value), well regions W1~W6 serve as high voltage well regions (high voltage well). At this time, the maximum value of the operating voltage VH of the electrostatic discharge protection structure 400A can reach a first value. When the impurity concentration of well regions W1~W6 is relatively high (such as higher than the threshold value), well regions W1~W6 serve as low voltage well regions (low voltage well). At this time, the maximum value of the operating voltage VH of the electrostatic discharge protection structure 400A can reach a second value. In this example, the first value is greater than the second value. In other embodiments, the types of well regions W1~W6 are different. For example, at least one of the well regions W1~W6 is a low-voltage well region, and the remaining well regions are high-voltage well regions. In this example, the maximum value of the operating voltage VH may be between the first and second values.

In some embodiments, the ESD protection structure 400A further includes well regions W7 to W12. Well region W7 is disposed in well region W1 and has a P-type conductivity. The impurity concentration of well region W7 is higher than the impurity concentration of well region W1 and lower than the impurity concentration of doping region P1. Well region W8 is disposed in well region W2 and has an N-type conductivity. The impurity concentration of well region W8 is higher than the impurity concentration of well region W2 and lower than the impurity concentration of doping region N1. Well region W9 is disposed in well region W3 and has a P-type conductivity. The impurity concentration of the well region W9 is higher than the impurity concentration of the well region W3 and lower than the impurity concentration of the doping region P3. The well region W10 is arranged in the well region W4 and has a P-type conductivity. The impurity concentration of the well region W10 is higher than the impurity concentration of the well region W4 and lower than the impurity concentration of the doping region P4. The well region W11 is arranged in the well region W5 and has an N-type conductivity. The impurity concentration of the well region W11 is higher than the impurity concentration of the well region W5 and lower than the impurity concentration of the doping region N1. The well region W12 is arranged in the well region W6 and has a P-type conductivity. The impurity concentration of well area W12 is higher than that of well area W6 and lower than that of doped area P6.

Well regions W7, W9, W10 and W12 have similar impurity concentrations, and well regions W8 and W11 have similar impurity concentrations. In one possible embodiment, well regions W7, W9, W10 and W12 are referred to as low-voltage P-type well regions (LVPW), and well regions W8 and W11 are referred to as low-voltage N-type well regions (LVNW). In this example, well regions W1, W3, W4 and W6 are referred to as high-voltage P-type well regions (HVPW), and well regions W2 and W5 are referred to as high-voltage N-type well regions (HVNW).

In some embodiments, when the well regions W7-W12 are respectively disposed in the well regions W1-W6, the maximum value of the operating voltage VH of the electrostatic discharge protection structure 400A can reach a third value. In this example, the third value is greater than the first value. For example, the third value may be 20V.

In this embodiment, the doped region P1, the well region W1 and W7 constitute the emitter of the PNP type bipolar junction transistor PNP_2. The deep N-type well region 310, the well regions W5, W11 and the doped region N1 constitute the base of the PNP type bipolar junction transistor PNP_2. The P-type substrate 300, the well regions W6, W12 and the doped region P6 constitute the collector of the PNP type bipolar junction transistor PNP_2.

In addition, the deep N-type well region 310, well regions W5, W11 and doped region N1 serve as the cathode of the diode DD. The P-type substrate 300, well regions W6, W12 and doped region P6 serve as the anode of the diode DD.

The doped region P1, the well region W7 and W1 constitute the collector of the PNP bipolar junction transistor PNP_1. The deep N-type well region 310, the well region W2 and W8 constitute the base of the PNP bipolar junction transistor PNP_1. The doped region P2 serves as the emitter of the PNP bipolar junction transistor PNP_1. The equivalent resistance of the deep N-type well region 310 serves as the resistor R_1.

The doped region P2 serves as the emitter of the parasitic PNP bipolar junction transistor PNP_4. The well regions W8, W2 and the deep N-type well region 310 constitute the base of the parasitic PNP bipolar junction transistor PNP_4. The well regions W3, W9 and the doped region P3 serve as the collector of the parasitic PNP bipolar junction transistor PNP_4.

The doped region P5 serves as the emitter of the PNP bipolar junction transistor PNP_3. The well regions W11, W15 and the deep N-type well region 310 serve as the base of the PNP bipolar junction transistor PNP_3. The well regions W4, W10 and the doped region P4 serve as the collector of the PNP bipolar junction transistor PNP_4. The equivalent resistance of the deep N-type well region 310, the well regions W5 and W11 serves as the resistor R_2.

In some embodiments, the ESD protection structure 400A further includes a resistive protective oxide (RPO) 320. The resistive protective oxide 320 is located on the surface of the doped regions P3 and P4 to cut off the conductive layer on the surface of the doped regions P3 and P4. In addition, the ESD protection structure 400A further includes insulating structures S_1~S_7. The insulating structures S_1~S_7 may be field oxide layers or shallow trench isolation (STI) structures.

The doped region P1 is located between the insulating structures S_1 and S_2. The insulating structure S_2 separates the doped regions P1 and P2. In this embodiment, the insulating structure S_2 further separates the well regions W7 and W8. The insulating structure S_3 separates the doped regions P2 and P3. In this embodiment, the insulating structure S_3 further separates the well regions W8 and W9. The insulating structure S_4 separates the doped regions P4 and P5. In this embodiment, the insulating structure S_4 further separates the well regions W10 and W11. The insulating structure S_5 separates the doped regions P5 and N1. In this embodiment, the insulating structure S_5 is located in the well region W11. The insulating structure S_6 separates the doped regions N1 and P6. In this embodiment, the insulating structure S_6 further separates the well regions W11 and W12. In addition, the doped region P6 is located between the insulating structures S_6 and S_7.

In some embodiments, the width DS1 of the insulating structure S_5 is related to the performance of the electrostatic discharge protection structure 400A. For example, when the width DS1 of the insulating structure S_5 is larger, the electrostatic discharge protection structure 400A has better human body discharge mode (HBM) performance and mechanical discharge mode (MM) performance, and has a lower on-resistance, which is conducive to the electrostatic discharge current entering the electrostatic discharge protection structure 400A.

In other embodiments, the electrostatic discharge protection structure 400A further includes interconnect structures 330-350. The interconnect structure 330 electrically connects the power pad PD_1, doping regions N1, P5 and P2. The interconnect structure 340 electrically connects the power pad PD_2, doping regions P1, P3 and P4. The interconnect structure 350 electrically connects the power pad PD_3 and the doping region P6. In this example, the power pad PD_1 receives the operating voltage VH, the power pad PD_2 receives the operating voltage VL, and the power pad PD_3 receives the operating voltage VSUB.

Please refer to FIG. 3A, which shows the layout of doping regions P1~P6 and N1 of the ESD protection structure 400A. To simplify the diagram, other components of FIG. 4A are omitted and not shown in FIG. 3A. In FIG. 3A, doping regions P6 and N1 are ring structures. Doping region N1 surrounds doping regions P1~P5. Doping region P6 surrounds doping region N1. The resistive protection oxide 320 overlaps part of the doping regions P1, P3 and P4.

FIG. 3B is another top view of the structure of the electrostatic discharge protection circuit 110 of the present invention. FIG. 4B is a cross-sectional view of the electrostatic discharge protection structure of FIG. 3B along the dotted lines AA' and BB'. FIG. 4B is similar to FIG. 4A, but the difference is that the electrostatic discharge protection structure 400B of FIG. 4B has an additional insulating structure S_8. For the convenience of explanation, FIG. 4B omits the symbols that have appeared in FIG. 4A.

The insulating structure S_8 separates the doped region P4 of FIG. 4A. The separated doped regions are called P4_1 and P4_2. In this example, the interconnect structure 340 electrically connects the power pad PD_2, the doped regions P1, P3, P4_1, and P4_2. In some embodiments, the width DS2 of the insulating structure S_8 is related to the performance of the ESD protection structure 400B. For example, when the width DS2 of the insulating structure S_8 is larger, the ESD protection structure 400B has better HBM performance and MM performance, and has a lower on-resistance, which is conducive to the ESD current entering the ESD protection structure 400B.

Please refer to FIG. 3B, which shows the layout of doping regions P1~P3, P4_1, P4_2, P5, P6, and N1 of the ESD protection structure 400B. FIG. 3B is similar to FIG. 3A, except that FIG. 3B has additional doping regions P4_1 and P4_2. To simplify the diagram, other components of FIG. 4B are omitted and not shown in FIG. 3B. In FIG. 3B, doping region P4_2 is located between doping regions P5 and P4_1. The resistive protection oxide 320 overlaps part of the doping regions P1, P3, and P4_1.

FIG. 5A is a top view of the ESD protection structure of the ESD protection circuit 210 of the present invention. FIG. 6A is a cross-sectional view of the ESD protection structure of FIG. 5A along the dotted lines CC' and DD'. FIG. 6A shows that the ESD protection structure 600A includes a P-type substrate 300, a deep N-type well region 310, well regions W1~W12, doping regions P1~P3, P6, P7, N2 and N3. Since the P-type substrate 300, the deep N-type well region 310, the well region W1~W12, the doping regions P1~P3 and P6 have been described above, they will not be repeated. For the convenience of explanation, FIG. 6A omits the symbols that appear in FIG. 4A.

In FIG. 6A, doping regions P7 and N2 are disposed in well region W10. The conductivity type of doping region P7 is P type. The conductivity type of doping region N2 is N type. In addition, doping region N3 is disposed in well region W11. The conductivity type of doping region N3 is N type. In this embodiment, the impurity concentrations of doping regions N2 and N3 are similar and higher than those of well regions W5 and W11.

The insulating structure S_9 separates the doped region P7 and N2 and is located in the well region W10. In this embodiment, by adjusting the width DS3 of the insulating structure S_9, the performance of the electrostatic discharge protection structure 600A can be improved, such as increasing the HBM performance and the MM performance, and having a lower on-resistance.

In some embodiments, the insulating structure S_10 separates the doped regions N2 and N3. In some embodiments, the insulating structure S_10 further separates the well regions W10 and W11. The insulating structure S_11 separates the doped regions N3 and P6. In some embodiments, the insulating structure S_11 further separates the well regions W11 and W12.

In this embodiment, the doped region P1, the well region W7 and W1 constitute the emitter of the PNP bipolar junction transistor PNP_2. The deep N-type well region 310, the well regions W5, W11 and the doped region N3 constitute the base of the PNP bipolar junction transistor PNP_2. The P-type substrate 300, the well regions W6, W12 and the doped region P6 constitute the collector of the PNP bipolar junction transistor PNP_2. In addition, the deep N-type well region 310, the well regions W5, W11 and the doped region N3 constitute the cathode of the diode DD. The P-type substrate 300, the well regions W6, W12 and the doped region P6 constitute the anode of the diode DD.

The doped region P1, the well region W7 and W1 constitute the collector of the PNP bipolar junction transistor PNP_1. The doped region P2 serves as the emitter of the PNP bipolar junction transistor PNP_1. The deep N-type well region 310, the well region W2 and W8 constitute the base of the PNP bipolar junction transistor PNP_1. The equivalent resistance of the deep N-type well region 310 serves as the resistor R_1.

The doped region P2 serves as the emitter of the parasitic PNP bipolar junction transistor PNP_5. The well regions W8, W2 and the deep N-type well region 310 constitute the base of the parasitic PNP bipolar junction transistor PNP_5. The well regions W3, W9 and the doped region P3 constitute the collector of the parasitic PNP bipolar junction transistor PNP_5.

The doped region N2 serves as the emitter of the parasitic NPN bipolar junction transistor NPN_2. The well regions W10 and W4 constitute the base of the parasitic NPN bipolar junction transistor NPN_2. The deep N-type well region 310, the well regions W5 and W11, and the doped region N3 constitute the collector of the parasitic NPN bipolar junction transistor NPN_2.

The doped region N2 serves as the emitter of the NPN bipolar junction transistor NPN_1. The well regions W10 and W4 constitute the base of the NPN bipolar junction transistor NPN_1. The deep N-type well region 310, the well regions W5, W11 and the doped region N3 constitute the collector of the NPN bipolar junction transistor NPN_1. The equivalent resistance of the well region W10 serves as the resistors R_2 and R_3.

In this embodiment, the interconnect structure 610 electrically connects the power pad PD_1, doping regions N3 and P2, the interconnect structure 620 electrically connects the power pad PD_2, doping regions P1, P3, P7 and N2, and the interconnect structure 630 electrically connects the power pad PD_3 and doping region P6. In this example, the power pad PD_1 receives the operating voltage VH, the power pad PD_2 receives the operating voltage VL, and the power pad PD_3 receives the operating voltage VSUB.

Please refer to FIG. 5A, which shows the layout of doping regions P1~P3, P6, P7, N2 and N3 of the ESD protection structure 600A. To simplify the diagram, other components of FIG. 6A are omitted and not shown in FIG. 5A. In FIG. 5A, doping regions P6 and N3 are ring structures. Doping region N3 surrounds doping regions P1~P3, P6, P7. Doping region P6 surrounds doping region N3. The resistive protection oxide 320 overlaps part of the doping regions P1, P3 and P7.

In some embodiments, the distance DS3 between the doped regions N2 and P7 (i.e., the width of the insulating structure S_9 in FIG. 6A ) is related to the performance of the ESD protection structure 600A. For example, when the distance DS3 is larger, the ESD protection structure 600A has better HBM performance and MM performance, and has lower on-resistance.

FIG. 5B is another top view of the structure of the electrostatic discharge protection circuit 210 of the present invention. FIG. 6B is a cross-sectional view of the electrostatic discharge protection structure 600B of FIG. 5B along the dotted lines CC' and DD'. FIG. 6B is similar to FIG. 6A, but the difference is that the electrostatic discharge protection structure 600B of FIG. 6B has an additional insulating structure S_13. For the convenience of explanation, FIG. 6B omits the symbols that appear in FIG. 6A.

The insulating structure S_13 separates the doped region N3 of FIG. 6A to form doped regions N3_1 and N3_2. As shown in FIG. 6B, the doped regions N3_1 and N3_2 are located in the well region W11 and have N-type conductivity. The impurity concentration of the doped regions N3_1 and N3_2 is greater than the impurity concentration of the well region W11. The impurity concentration of the well region W11 is greater than the impurity concentration of the well region W5. The doped region N3_1 is located between the insulating structures S_11 and S_13, and the doped region N3_2 is located between the insulating structures S_10 and S_13. In this embodiment, the interconnect structure 610 electrically connects the power pad PD_1, the doped regions N3_1, N3_2, and P2.

Please refer to FIG. 5B, which shows the layout of doping regions P1~P3, P6, P7, N2, N3_1, and N3_2 of the ESD protection structure 600B. FIG. 5B is similar to FIG. 5A, except that FIG. 5B has additional doping regions N3_1 and N3_2. To simplify the diagram, other components of FIG. 6B are omitted and not shown in FIG. 5B. In FIG. 5B, doping region N3_2 is located between doping regions N3_1 and N2. Doping region N3_1 is located between doping region N3_2 and P6.

In some embodiments, the distance DS3 between the doped regions N2 and P7 (i.e., the width of the insulating structure S_9 in FIG. 6B ) and the distance DS4 between the doped regions N3_1 and N3_2 (i.e., the width of the insulating structure S_13 in FIG. 6B ) are related to the performance of the ESD protection structure 600B. For example, when at least one of the distances DS3 and DS4 is larger, the ESD protection structure 600B has better HBM performance and MM performance, and has lower on-resistance.

FIG. 7A is a top view of the ESD protection structure of the ESD protection circuit 210 of the present invention. FIG. 8A is a cross-sectional view of the ESD protection structure of FIG. 7A along the dotted lines EE' and FF'. The ESD protection structure 800A of FIG. 8A is similar to the ESD protection structure 600A of FIG. 6A, except that the positions of the doping regions P7 and N2 of FIG. 8A are different from the positions of the doping regions P7 and N2 of FIG. 6A. For the convenience of explanation, the symbols of the omitted parts of FIG. 8A already appear in FIG. 6A.

In FIG. 6A, the doping region N2 is located between the insulating structures S_9 and S_10. Therefore, in FIG. 6A, the distance between the doping regions N2 and N3 is smaller than the distance between the doping regions P7 and N3. In FIG. 8A, the doping region P7 is located between the insulating structures S_9 and S_10. Therefore, the distance between the doping regions P7 and N3 is smaller than the distance between the doping regions N2 and N3. In this embodiment, the equivalent resistance of the doping region P3 and the well region W9 serves as the resistors R_2 and R_3 in FIG. 2.

Please refer to FIG. 7A, which shows the layout of the doping regions P1~P3, P6, P7, N2 and N3 of the ESD protection structure 800A. To simplify the diagram, other components of FIG. 8A are omitted and not shown in FIG. 7A. In FIG. 7A, the doping region P7 is located between the doping regions N2 and N3.

In some embodiments, the distance DS3 between the doped regions N2 and P7 (i.e., the width of the insulating structure S_9 in FIG. 8A ) is related to the performance of the ESD protection structure 800A. For example, when the distance DS3 is larger, the ESD protection structure 800A has better HBM performance and MM performance, and has lower on-resistance.

FIG. 7B is another top view of the structure of the electrostatic discharge protection circuit 210 of the present invention. FIG. 8B is a cross-sectional view of the electrostatic discharge protection structure 800B of FIG. 7B along the dotted lines EE' and FF'. FIG. 8B is similar to FIG. 6B, except that the positions of the doping regions P7 and N2 of FIG. 8B are different from the positions of the doping regions P7 and N2 of FIG. 6B. For the convenience of explanation, FIG. 8B omits the symbols that have appeared in FIGS. 6B and 8A.

In FIG. 6B, the doping region N2 is located between the insulating structures S_9 and S_10. Therefore, in FIG. 6B, the distance between the doping region N2 and N3_2 is smaller than the distance between the doping region P7 and N3_2. In FIG. 8B, the doping region P7 is located between the insulating structures S_9 and S_10. Therefore, the distance between the doping region P7 and N3_2 is smaller than the distance between the doping region N2 and N3_2.

Please refer to FIG. 7B, which shows the layout of doping regions P1~P3, P6, P7, N2, N3_1, and N3_2 of the ESD protection structure 800B. FIG. 7B is similar to FIG. 7A, except that FIG. 7B has additional doping regions N3_1 and N3_2. To simplify the diagram, other components of FIG. 8B are omitted and not shown in FIG. 7B. In FIG. 7B, doping region P7 is located between doping regions N3_2 and N2. Doping region N3_1 is a ring structure that surrounds doping regions P1~P3, P7, N2, and N3_2.

In some embodiments, the distance DS3 between the doped regions N2 and P7 (i.e., the width of the insulating structure S_9 in FIG. 8B ) and the distance DS4 between the doped regions N3_1 and N3_2 (i.e., the width of the insulating structure S_13 in FIG. 8B ) are related to the performance of the ESD protection structure 800B. For example, when at least one of the distances DS3 and DS4 is larger, the ESD protection structure 800B has better HBM performance and MM performance, and has lower on-resistance.

It must be understood that when an element or layer is referred to as being "coupled" to another element or layer, it can be directly coupled or connected to the other element or layer, or have other elements or layers interposed therebetween. Conversely, if an element or layer is "connected" to another element or layer, there will be no other elements or layers interposed therebetween.

Unless otherwise defined, all terms (including technical and scientific terms) herein are generally understood by those with ordinary knowledge in the technical field to which the present invention belongs. In addition, unless expressly stated, the definitions of terms in general dictionaries should be interpreted as consistent with the meanings in articles in the relevant technical field, and should not be interpreted as ideal or overly formal. Although terms such as "first" and "second" can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. In the scope of the patent application, terms such as "first" and "second" are used as markers and are not intended to impose numerical requirements on their objects.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field may make some changes and modifications without departing from the spirit and scope of the present invention. For example, the system, device or method described in the embodiments of the present invention can be implemented in a physical embodiment of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: Operating system

110: Electrostatic discharge protection circuit

120: Core circuit

121~123: Circuit

PD_1~PD_3: Power pad

VH, VL, VSUB: operating voltage

PNP_1~PNP_4: PNP type bipolar junction transistor

R_1, R_2: resistance

DD: diode

111:Specific bipolar junction transistor

Claims (20)

An electrostatic discharge protection circuit is used to protect a core circuit, and includes: A first PNP type bipolar junction transistor, having a first base, a first emitter and a first collector, the first emitter is coupled to a first power pad, and the first collector is coupled to a second power pad; A first resistor is coupled between the first power pad and the first base; A second PNP type bipolar junction transistor, having a second base, a second emitter and a second collector, the second emitter is coupled to the second power pad, and the second collector is coupled to a third power pad; A diode having a cathode and an anode, the cathode coupled to the first power pad and the second base, the anode coupled to the third power pad; A specific bipolar junction transistor coupled between the first power pad and the second power pad; and A second resistor coupled between an emitter and a base of the specific bipolar junction transistor, wherein when an electrostatic discharge event occurs, the first PNP bipolar junction transistor and the specific bipolar junction transistor are turned on, so that an electrostatic discharge current flows through the first PNP bipolar junction transistor and the specific bipolar junction transistor. The electrostatic discharge protection circuit as described in claim 1, wherein: The specific bipolar junction transistor is a third PNP bipolar junction transistor, the emitter of the third PNP bipolar junction transistor is coupled to the first power pad, the collector of the third PNP bipolar junction transistor is coupled to the second power pad, and the base of the third PNP bipolar junction transistor is coupled to the second resistor. The electrostatic discharge protection circuit as described in claim 2 further includes: A parasitic PNP bipolar junction transistor, whose base is coupled to the first base, whose emitter is coupled to the first power pad, and whose collector is coupled to the second power pad. An electrostatic discharge protection circuit as described in claim 3, wherein the first PNP bipolar junction transistor, the specific bipolar junction transistor and the parasitic PNP bipolar junction transistor share the same substrate. An electrostatic discharge protection circuit as described in claim 3, wherein when the electrostatic discharge event occurs, the parasitic PNP bipolar junction transistor is turned on. The electrostatic discharge protection circuit as described in claim 1, wherein: The specific bipolar junction transistor is a first NPN bipolar junction transistor, the base of the first NPN bipolar junction transistor is coupled to the second resistor, the emitter of the first NPN bipolar junction transistor is coupled to the second power pad, and the collector of the first NPN bipolar junction transistor is coupled to the first power pad. The electrostatic discharge protection circuit as described in claim 6 further includes: a parasitic PNP bipolar junction transistor, whose base is coupled to the first base, whose emitter is coupled to the first power pad, and whose collector is coupled to the base of the first NPN bipolar junction transistor; a third resistor, coupled between the collector of the parasitic PNP bipolar junction transistor and the second power pad; a second NPN bipolar junction transistor, whose base is coupled to the base of the first NPN bipolar junction transistor, whose emitter is coupled to the second power pad, and whose collector is coupled to the first base. An electrostatic discharge protection circuit as described in claim 7, wherein the first PNP bipolar junction transistor, the specific bipolar junction transistor, the parasitic PNP bipolar junction transistor and the second NPN bipolar junction transistor share the same substrate. An electrostatic discharge protection circuit as described in claim 1, wherein when the electrostatic discharge event does not occur, the first power pad receives a first operating voltage, the second power pad receives a second operating voltage, and the third power pad receives a third operating voltage, the first operating voltage is greater than the second operating voltage, and the second operating voltage is greater than the third operating voltage. An electrostatic discharge protection circuit as described in claim 9, wherein when the electrostatic discharge event does not occur, the first PNP type bipolar junction transistor and the specific bipolar junction transistor are not conductive, and the first to third power pads provide the first to third operating voltages to the core circuit. An electrostatic discharge protection structure includes: a P-type substrate; a deep N-type well region, disposed in the P-type substrate; a first well region, disposed on the deep N-type well region; a first P-type doped region, disposed in the first well region; a second well region, disposed on the deep N-type well region; a second P-type doped region, disposed in the second well region; a third well region, disposed on the deep N-type well region; a third P-type doped region, disposed in the third well region; a fourth well region, disposed on the deep N-type well region; a fourth P-type doped region, disposed in the fourth well region; a fifth well region, disposed on the deep N-type well region; A specific doped region is disposed in the fourth well region or the fifth well region; A first N-type doped region is disposed in the fifth well region; Wherein, the conductivity type of the first, third and fourth well regions is P-type, and the conductivity type of the second and fifth well regions is N-type. An electrostatic discharge protection structure as described in claim 11, wherein the conductivity type of the specific doped region is P type and is located in the fifth well region. The electrostatic discharge protection structure as described in claim 12 further includes: A first insulating structure disposed between the fifth well regions and separating the specific doping region and the first N-type doping region. The electrostatic discharge protection structure as described in claim 12 further includes: a fifth P-type doped region disposed in the fourth well region; and a second insulating structure disposed between the fourth well regions and separating the fourth and fifth P-type doped regions. The electrostatic discharge protection structure as described in claim 11, wherein the conductivity type of the specific doping region is N-type and is located in the fourth well region. The electrostatic discharge protection structure as described in claim 15 further includes: A third insulating structure disposed between the fourth well regions and separating the specific doping region and the fourth P-type doping region. The electrostatic discharge protection structure as described in claim 15 further includes: a second N-type doped region disposed in the fifth well region; and a second insulating structure disposed between the fifth well regions and separating the first N-type doped region and the second N-type doped region. An electrostatic discharge protection structure as described in claim 17, wherein the specific doped region is located between the second N-type doped region and the fourth P-type doped region. An electrostatic discharge protection structure as described in claim 17, wherein the fourth P-type doped region is located between the specific doped region and the first N-type doped region. The electrostatic discharge protection structure as described in claim 11 further includes: a first internal connection structure electrically connecting the first N-type doped region, the specific doped region, and the second P-type doped region; a second internal connection structure electrically connecting the first, third, and fourth P-type doped regions.

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