TWI882215B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a silicon carbide circuit board, a gallium nitride device and a silicon integrated circuit device. The silicon carbide circuit board includes a silicon carbide substrate and a circuit structure located above the silicon carbide substrate. The gallium nitride device includes a sapphire substrate, a gallium nitride component on the sapphire substrate, and a first redistribution structure on the gallium nitride component. The silicon integrated circuit device includes a silicon substrate, a field-effect transistor on the silicon substrate, and a second redistribution structure on the field-effect transistor.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a method for manufacturing the same.

In the field of integrated circuits, III-V compound semiconductors are often used to form a variety of semiconductor devices, such as high power field-effect transistors, high frequency transistors, or high electron mobility transistors (HEMT). A high electron mobility transistor is a field effect transistor that can use a junction between two materials with different energy gaps as a channel, so that the channel has a two-dimensional electron gas (2DEG) with high electron mobility. In recent years, high electron mobility transistors have gradually attracted attention due to their high power performance.

Generally speaking, when manufacturing semiconductor devices, the performance of semiconductor devices will be affected by the material of the semiconductor substrate. For example, silicon semiconductor materials have the advantage of mature process, but when III-V compound semiconductor devices (such as gallium nitride semiconductor devices) are formed on a silicon substrate, parasitic channels may be formed in the silicon substrate, thereby reducing the performance of III-V compound semiconductor devices. In addition, gallium nitride semiconductor devices formed on sapphire substrates can have better performance, but if gallium nitride semiconductor devices are formed on sapphire substrates, gallium nitride semiconductor devices may have characteristics shift after long-term use due to the poor heat dissipation capacity of the sapphire substrate.

The present invention provides a semiconductor device that can improve the problem of parasitic resistance in the circuit of the semiconductor device, and the semiconductor device has the advantage of good heat dissipation effect.

The present invention provides a method for manufacturing a semiconductor device, which can improve the problem of parasitic resistance in the circuit of the semiconductor device, and the semiconductor device has the advantage of good heat dissipation effect.

At least one embodiment of the present invention provides a semiconductor device, including a silicon carbide circuit board, a gallium nitride device, and a silicon integrated circuit device. The silicon carbide circuit board includes a silicon carbide substrate and a circuit structure located above the silicon carbide substrate. The circuit structure includes a plurality of first internal connection terminals, a plurality of second internal connection terminals, and a plurality of external connection terminals. The external connection terminals are configured to connect external signals. The gallium nitride device includes a sapphire substrate, a gallium nitride element located on the sapphire substrate, and a first redistribution structure located on the gallium nitride element. The first redistribution structure is electrically connected to the first internal connection terminal. The silicon integrated circuit device includes a silicon substrate, a field effect transistor element located on the silicon substrate, and a second redistribution structure located on the field effect transistor element. The second redistribution structure is electrically connected to the second internal connection terminal.

At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a circuit structure on a silicon carbide substrate, wherein the circuit structure includes a plurality of first internal connection terminals, a plurality of second internal connection terminals, and a plurality of external connection terminals, wherein the external connection terminals are configured to connect to external signals; forming a gallium nitride component layer on a sapphire wafer; forming a first redistribution layer on the gallium nitride component layer; cutting the sapphire wafer to form a plurality of gallium nitride devices, each of which has a plurality of first internal connection terminals, and forming a plurality of second internal connection terminals; forming a plurality of second internal connection terminals, and forming a plurality of external connection terminals; forming a plurality of first internal connection terminals, and forming a plurality of external ... second internal connection terminals, and forming a plurality of external connection terminals; forming a plurality of second internal connection terminals, and forming a plurality of external connection terminals; forming a plurality of second internal connection terminals, and forming a plurality of external connection terminals; forming a plurality of second internal connection terminals, and forming a plurality of external connection terminals; forming a plurality of second internal connection terminals, and forming a plurality of external connection terminals; forming a plurality of second internal connection terminals, and forming a plurality of external connection terminals; forming a plurality of second internal connection terminals, and forming a plurality of external connection terminals. The device includes a sapphire substrate, a first redistribution structure and a gallium nitride device; electrically connecting at least one gallium nitride device to a first internal connection terminal; forming a field effect transistor device layer on a silicon wafer; forming a second redistribution layer on the field effect transistor device layer; cutting the silicon wafer to form a plurality of silicon integrated circuit devices, each silicon integrated circuit device including a silicon substrate, a second redistribution structure and a field effect transistor device; and electrically connecting at least one silicon integrated circuit device to a second internal connection terminal.

10: Silicon carbide circuit board

20: Gallium nitride device

30: Silicon integrated circuit device

100,100a: Silicon carbide substrate

111,112: First internal connection terminal

113,114: Second internal connection terminal

115,116: External connection terminals

117: Routing

120: Protective layer

200: Sapphire wafer

2001: Sapphire base

2001t,3001t: Top surface

210: Gallium nitride component layer

2101: Gallium nitride components

211,2111: Channel layer

212,2121: First semiconductor layer

213,2131: Passivation layer

214: Gate

215: Source/Drain

220: First redistribution layer

2201: The first redistribution structure

221:Line structure

222: Dielectric structure

230:Connection terminal

300: Silicon wafer

3001:Silicon substrate

310: Field effect transistor device layer

3101: Cutting field effect transistor device layer

311: Field effect transistor device

320: Second redistribution layer

3201: Second redistribution structure

321: Line structure

322: Dielectric structure

330:Connection terminal

400: Packaging materials

CS: Circuit structure

Figures 1A to 2A are top-view schematic diagrams of a method for manufacturing a silicon carbide circuit board according to an embodiment of the present invention.

Figures 1B to 2B are schematic cross-sectional views along lines a-a’ of Figures 1A to 2A, respectively.

Figures 3A to 3C are cross-sectional schematic diagrams of a method for manufacturing a gallium nitride device according to an embodiment of the present invention.

Figures 4A to 4C are cross-sectional schematic diagrams of a method for manufacturing a silicon integrated circuit device according to an embodiment of the present invention.

Figures 5A to 7A are top-view schematic diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Figures 5B to 7B are schematic cross-sectional views along lines a-a’ of Figures 7A to 7A, respectively.

Figures 8A to 9A are top-view schematic diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Figures 8B to 9B are schematic cross-sectional views along lines a-a' of Figures 8A to 9A, respectively.

Figures 10 and 11 are top-view schematic diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG12 is a circuit diagram of a semiconductor device according to an embodiment of the present invention.

Figures 1A to 2A are top-view schematic diagrams of a method for manufacturing a silicon carbide circuit board according to an embodiment of the present invention. Figures 1B to 2B are cross-sectional schematic diagrams along lines a-a' of Figures 1A to 2A, respectively.

Referring to FIG. 1A and FIG. 1B , a silicon carbide substrate 100 is provided. In the present embodiment, the silicon carbide substrate 100 is a cut substrate. For example, a circular silicon carbide wafer is cut into a rectangular silicon carbide substrate 100, but the present invention is not limited thereto. In other embodiments, the silicon carbide substrate 100 includes other shapes, such as a triangle, a pentagon, a circle, an ellipse or other shapes. In addition, in other embodiments, the silicon carbide substrate 100 may also be an uncut silicon carbide wafer. In some embodiments, the thickness 100t of the silicon carbide substrate 100 is 200 microns to 700 microns.

Compared to the polymer substrate materials used in general printed circuit boards, the silicon carbide substrate 100 has the advantage of a high heat dissipation coefficient. Specifically, in some embodiments, the heat dissipation coefficient of the silicon carbide substrate 100 is between 3.3W/cmK and 4.9W/cmK at room temperature (25 degrees Celsius). In this embodiment, since the silicon carbide substrate 100 is not used for the epitaxial process, the quality of the silicon carbide substrate 100 can be lower than the quality of the silicon carbide wafer generally used for the epitaxial process. In other words, the production cost of the silicon carbide substrate 100 can be lower than the production cost of the silicon carbide wafer generally used for the epitaxial process. For example, the defect density in the silicon carbide substrate 100 is greater than 9000 cm ^-2 , the bow is less than ±800 μm (preferably less than ±350 μm, and most preferably less than ±100 μm), and the warp is less than ±900 μm (preferably less than ±450 μm, and most preferably less than ±100 μm), but the present invention is not limited thereto.

Next, please refer to FIG. 2A and FIG. 2B to form a circuit structure CS on the silicon carbide substrate 100 to form a silicon carbide circuit board 10.

The circuit structure CS includes a plurality of first internal connection terminals (111, 112), a plurality of second internal connection terminals (113, 114) and a plurality of external connection terminals (115, 116). The plurality of first internal connection terminals (111, 112) and the plurality of second internal connection terminals (113, 114) are configured to be used for connecting internal components in a chip, a passive component or other semiconductor device, while the external connection terminals (115, 116) are configured to be used for connecting external signals. In other words, the external connection terminals (115, 116) are the input/output terminals of the silicon carbide circuit board 10. In some embodiments, the size of the external connection terminals (115, 116) is larger than the size of the first internal connection terminals (111, 112) and the size of the second internal connection terminals (113, 114).

In the present embodiment, the first internal connection terminals (111, 112), the plurality of second internal connection terminals (113, 114), and the plurality of external connection terminals (115, 116) are electrically connected to each other via corresponding traces 117. For example, the first internal connection terminal 111 is electrically connected to the external connection terminal 115, the first internal connection terminal 112 is electrically connected to the second internal connection terminal 113, and the second internal connection terminal 114 is electrically connected to the external connection terminal 116. In the present embodiment, the first internal connection terminals (111, 112), the second internal connection terminals (113, 114), the external connection terminals (115, 116), and the traces 117 belong to the same layer. Specifically, the method for forming the first internal connection terminal (111, 112), the second internal connection terminal (113, 114), the external connection terminal (115, 116) and the wiring 117 includes depositing a first metal layer on the silicon carbide circuit board 10, and then patterning the first metal layer to form a first metal wiring layer, wherein the first metal wiring layer includes the first internal connection terminal (111, 112), the second internal connection terminal (113, 114), the external connection terminal (115, 116) and the wiring 117. However, in other embodiments, the circuit structure CS may include more than one metal wiring layer, and different metal wiring layers are separated from each other by an insulating layer.

In this embodiment, the circuit structure CS further includes a protective layer 120 (omitted in FIG. 2A ). The protective layer 120 is used to protect the trace 117 in the circuit structure CS. The protective layer 120 exposes the first internal connection terminal (111, 112), the second internal connection terminal (113, 114) and the external connection terminal (115, 116).

It should be noted that in FIG. 2A and FIG. 2B , the circuit layout in the circuit structure CS is only for illustration, and the circuit layout in the circuit structure CS can be adjusted according to actual needs. In other words, the number and position of the first internal connection terminals (111, 112), the second internal connection terminals (113, 114), the external connection terminals (115, 116) and the trace 117 can be adjusted according to actual needs.

Figures 3A to 3C are cross-sectional schematic diagrams of a method for manufacturing a gallium nitride device according to an embodiment of the present invention.

Please refer to FIG. 3A , a sapphire wafer 200 is provided.

Referring to FIG. 3B , a gallium nitride device layer 210 is formed on a sapphire wafer 200. For example, the gallium nitride device layer 210 includes a channel layer 211, a first semiconductor layer 212, a passivation layer 213, a plurality of gates 214, and a plurality of source/drain electrodes 215.

In this embodiment, the channel layer 211 directly contacts the sapphire wafer 200, but the present invention is not limited thereto. In other embodiments, other intermediate layers are sandwiched between the channel layer 211 and the sapphire wafer 200. In one embodiment, the material of the channel layer 211 includes a III-V semiconductor material, which may be, for example, doped or non-doped GaN.

The first semiconductor layer 212 is located on the channel layer 211. The material of the first semiconductor layer 212 may be, for example, doped or non-doped AlGaN. For example, the material of the first semiconductor layer 212 includes n-AlGaN. A heterojunction may be formed between the channel layer 211 and the first semiconductor layer 212, so that a two-dimensional electron gas (2DEG) with high electron mobility is formed in the region where the channel layer 211 is close to the first semiconductor layer 212.

A plurality of gates 214 are located above the first semiconductor layer 212. In this embodiment, the gate 214 directly contacts the first semiconductor layer 212, but the present invention is not limited thereto. In other embodiments, p-GaN (not shown) is sandwiched between the gate 214 and the first semiconductor layer 212.

The passivation layer 213 is located above the gate 214 and the first semiconductor layer 212. A plurality of source/drain electrodes 215 penetrate the passivation layer 213 and contact the first semiconductor layer 212. The source/drain electrodes 215 selectively penetrate the first semiconductor layer 212 and contact the two-dimensional electron gas in the channel layer 211.

In this embodiment, the gallium nitride component layer 210 has a plurality of gallium nitride components 2101, and each gallium nitride component 2101 includes a corresponding channel layer 2111, a corresponding first semiconductor layer 2121, a corresponding passivation layer 2131, a corresponding gate 214, and a corresponding source/drain 215.

A first redistribution wiring layer 220 is formed on the gallium nitride component layer 210. The first redistribution wiring layer 220 includes a dielectric structure 222 and a circuit structure 221 embedded in the dielectric structure 222. In this embodiment, the circuit structure 221 and the dielectric structure 222 may each include a single-layer or multi-layer structure. When the circuit structure 221 includes a multi-layer structure, the circuit structures 221 between different layers are electrically connected through conductive holes.

Please continue to refer to FIG. 3B , a plurality of connection terminals 230 are selectively formed on the first redistribution wiring layer 220. The connection terminals 230 are electrically connected to the gate 214 and the source/drain 215 in the gallium nitride device layer 210 through the first redistribution wiring layer 220. The connection terminals 230 include, for example, tin, conductive glue or other similar structures.

Referring to FIG. 3C , the sapphire wafer 200 is cut to form a plurality of gallium nitride devices 20. Each gallium nitride device 20 includes a sapphire substrate 2001, a first redistribution structure 2201, and a gallium nitride element 2101. In some embodiments, each gallium nitride device 20 selectively further includes a connection terminal 230 on the first redistribution structure 2201.

In this embodiment, the lattice matching between gallium nitride and the sapphire substrate 2001 is good, and the sapphire substrate 2001 is not easy to generate parasitic channels during the manufacturing process, so a gallium nitride device 20 with better performance can be obtained.

Figures 4A to 4C are cross-sectional schematic diagrams of a method for manufacturing a silicon integrated circuit device according to an embodiment of the present invention.

Referring to FIG. 4A , a silicon wafer 300 is provided. The silicon wafer 300 includes, for example, doped or undoped bulk silicon or a semiconductor on an insulating layer (SOI), wherein the semiconductor on an insulating layer includes an insulating layer and a silicon layer formed on the aforementioned insulating layer.

Referring to FIG. 4B , a field effect transistor layer 310 is formed on a silicon wafer 300. In FIG. 4B , a field effect transistor element 311 in the field effect transistor layer 310 is indicated by a dotted box, and the specific structure of the field effect transistor element 311 is omitted. The field effect transistor layer 310 may include multiple layers of semiconductor elements and multiple layers of interconnect layers. For example, the field effect transistor layer 310 may include semiconductor elements manufactured in the front-end-of-line (FEOL) process and semiconductor elements manufactured in the back-end process (bank-end-of-line, BEOL). The semiconductor elements may be electrically connected to each other through the interconnect layer.

A second redistribution wiring layer 320 is formed on the field effect transistor element layer 310. The second redistribution wiring layer 320 includes a dielectric structure 322 and a circuit structure 321 embedded in the dielectric structure 322. In this embodiment, the circuit structure 321 and the dielectric structure 322 may each include a single layer or a multi-layer structure. When the circuit structure 321 includes a multi-layer structure, the circuit structures 321 between different layers are electrically connected through conductive holes.

Please continue to refer to FIG. 4B , selectively form a plurality of connection terminals 330 on the second redistribution layer 320. The connection terminals 330 are electrically connected to the field effect transistor element 311 in the field effect transistor element layer 310 through the second redistribution layer 320. The connection terminals 330 include, for example, tin, conductive glue or other similar structures.

Referring to FIG. 4C , the silicon wafer 300 is cut to form a plurality of silicon integrated circuit devices 30. Each silicon integrated circuit device 30 includes a silicon substrate 3001, a second redistribution structure 3201, and a field effect transistor element 311. In this embodiment, the cut field effect transistor element layer 3101 includes a plurality of field effect transistor elements 311, and each silicon integrated circuit device 30 includes a plurality of field effect transistor elements 311. In some embodiments, each silicon integrated circuit device 30 selectively further includes a connection terminal 330 on the second redistribution structure 3201.

In this embodiment, field effect transistor components are manufactured using silicon wafers, which has the advantages of mature photoprocessing technology, high production yield and low cost.

Figures 5A to 7A are top-view schematic diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 5B to 7B are cross-sectional schematic diagrams along lines a-a' of Figures 7A to 7A, respectively.

Please refer to FIG. 5A and FIG. 5B , at least one gallium nitride device 20 is electrically connected to the first internal connection terminal (111, 112) of the silicon carbide circuit board 10. Specifically, the gallium nitride device 20 is connected to the first internal connection terminal (111, 112) of the silicon carbide circuit board 10 through the connection terminal 230. In this embodiment, the manufacturing method of the gallium nitride device 20 is as described in FIG. 3A to FIG. 3C, but the present invention is not limited thereto. In other embodiments, other methods can also be used to manufacture the gallium nitride device 20.

At least one silicon integrated circuit device 30 is electrically connected to the second internal connection terminal (113, 114) of the silicon carbide circuit board 10. Specifically, the silicon integrated circuit device 30 is connected to the second internal connection terminal (113, 114) of the silicon carbide circuit board 10 through the connection terminal 330. In this embodiment, the manufacturing method of the silicon integrated circuit device 30 is as described in Figures 4A to 4C, but the present invention is not limited thereto. In other embodiments, other methods can also be used to manufacture the silicon integrated circuit device 30.

In this embodiment, the gallium nitride device 20 and the silicon integrated circuit device 30 are bonded in an inverted manner (e.g., welding or eutectic bonding) to the silicon carbide circuit board 10. The gallium nitride element 2101 is located between the sapphire substrate 2001 and the silicon carbide substrate 100, and the field effect transistor element 311 is located between the silicon substrate 3001 and the silicon carbide substrate 100. The gallium nitride device 20 and the silicon integrated circuit device 30 can be electrically connected to each other through the circuit structure CS on the silicon carbide circuit board 10. In this embodiment, the gallium nitride element 2101 in the gallium nitride device 20 includes a high electron mobility crystal transistor, and the high electron mobility crystal transistor is electrically connected to the field effect transistor element 311 of the silicon integrated circuit device 30 through the first redistribution structure 2201, the circuit structure CS and the second redistribution structure 3201. In some embodiments, the silicon integrated circuit device 30 is a driving element, such as a power chip.

In this embodiment, since the circuit structure CS electrically connecting the gallium nitride device 20 and the silicon integrated circuit device 30 is directly formed on the silicon carbide substrate 100 with a relatively high resistance value (for example, greater than 5000 ohm-cm), compared with connecting the gallium nitride device 20 and the silicon integrated circuit device 30 by means of jumpers, this embodiment can improve the problem of metal wiring disconnection between the gallium nitride device 20 and the silicon integrated circuit device 30 and the generation of parasitic resistance and parasitic inductance.

Please refer to FIG. 6A and FIG. 6B , a packaging material 400 is formed on the silicon carbide substrate 100 to cover the sapphire substrate 2001 and the silicon substrate 3001. In this embodiment, the packaging material 400 covers the gallium nitride device 20 and the silicon integrated circuit device 30 laterally. In this embodiment, the packaging material 400 covers the top surface of the sapphire substrate 2001 and the top surface of the silicon substrate 3001.

In this embodiment, the packaging material 400 is filled between the gallium nitride device 20 and the silicon carbide circuit board 10 and between the silicon integrated circuit device 30 and the silicon carbide circuit board 10, and laterally covers the connection terminals 230 and the connection terminals 330, but the present invention is not limited thereto. In other embodiments, after forming other bottom filling materials (Underfill) to cover the connection terminals 230 and the connection terminals 330, the packaging material 400 is formed on the silicon carbide circuit board 10.

Please refer to FIG. 7A and FIG. 7B , the packaging material 400, the sapphire substrate 2001 of the gallium nitride device 20, and the silicon substrate 3001 of the silicon integrated circuit device 30 are polished simultaneously to reduce the thickness of the gallium nitride device 20 and the thickness of the silicon integrated circuit device 30, and improve the heat dissipation problem of the gallium nitride device 20 and the silicon integrated circuit device 30. In this embodiment, the top surface 2001t of the sapphire substrate 2001 is coplanar with the top surface 3001t of the silicon substrate 3001.

Figures 8A to 9A are schematic top views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 8B to 9B are schematic cross-sectional views along lines a-a' of Figures 8A to 9A, respectively. It must be noted that the embodiments of Figures 8A to 9A use the component numbers and partial contents of the embodiments of Figures 5A to 7A, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

Please refer to FIG. 8A and FIG. 8B. In this embodiment, before the gallium nitride device 20 is electrically connected to the first internal connection terminal (111, 112) of the silicon carbide circuit board 10, the sapphire substrate 2001 of the gallium nitride device 20 or the sapphire wafer used to prepare the gallium nitride device 20 is ground. In other words, the gallium nitride device 20 that has been ground and thinned is directly connected to the first internal connection terminal (111, 112) of the silicon carbide circuit board 10 through the connection terminal 230.

In this embodiment, before the silicon integrated circuit device 30 is electrically connected to the second internal connection terminal (113, 114) of the silicon carbide circuit board 10, the silicon substrate 3001 of the silicon integrated circuit device 30 or the silicon wafer used to prepare the silicon integrated circuit device 30 is ground. In other words, the ground and thinned silicon integrated circuit device 30 is directly connected to the second internal connection terminal (113, 114) of the silicon carbide circuit board 10 through the connection terminal 330.

In this embodiment, the gallium nitride device 20 and the silicon integrated circuit device 30 are electrically connected to the silicon carbide circuit board 10 after the grinding process is performed first. Therefore, the negative effect of the stress generated by the grinding process on the contact between the gallium nitride device 20 and the silicon carbide circuit board 10 or the contact between the silicon integrated circuit device 30 and the silicon carbide circuit board 10 can be improved. In this embodiment, the top surface 2001t of the sapphire substrate 2001 and the top surface 3001t of the silicon substrate 3001 can be coplanar or non-coplanar.

Referring to FIG. 9A and FIG. 9B , a packaging material 400 is formed on the silicon carbide substrate 100 to cover the sapphire substrate 2001 and the silicon substrate 3001. In this embodiment, the packaging material 400 covers the gallium nitride device 20 and the silicon integrated circuit device 30 laterally. In this embodiment, the packaging material 400 covers the top surface 2001t of the sapphire substrate 2001 and the top surface 3001t of the silicon substrate 3001.

In this embodiment, the packaging material 400 is filled between the gallium nitride device 20 and the silicon carbide circuit board 10 and between the silicon integrated circuit device 30 and the silicon carbide circuit board 10, and laterally covers the connection terminals 230 and the connection terminals 330, but the present invention is not limited thereto. In other embodiments, other bottom filling materials are first formed to cover the connection terminals 230 and the connection terminals 330, and then the packaging material 400 is formed on the silicon carbide circuit board 10.

Figures 10 and 11 are top-view schematic diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Please refer to FIG. 10 . In this embodiment, a plurality of circuit structures are formed on a silicon carbide substrate 100a, wherein the silicon carbide substrate 100a is a silicon carbide wafer. In this embodiment, the specific structure and description of each circuit structure can refer to the embodiments of FIG. 1A to FIG. 2A , and will not be described in detail here.

Then, multiple gallium nitride devices 20 are electrically connected to the first internal connection terminal of the circuit structure, and multiple silicon integrated circuit devices 30 are electrically connected to the second internal connection terminal of the circuit structure. In this embodiment, for example, the gallium nitride devices 20 and the silicon integrated circuit devices 30 are transferred to the silicon carbide substrate 100a by mass transfer technology.

Next, please refer to FIG. 11 , and perform a cutting process on the silicon carbide substrate 100a to form a plurality of silicon carbide circuit boards 10. Each silicon carbide circuit board 10 is provided with a corresponding gallium nitride device 20 and a corresponding silicon integrated circuit device 30.

In some embodiments, before the cutting process is performed, the gallium nitride device 20 and the silicon integrated circuit device 30 are packaged on the silicon carbide substrate 100a using a packaging material (omitted in FIG. 10 and FIG. 11 ) to prevent the cutting process from causing damage to the gallium nitride device 20 and the silicon integrated circuit device 30. In addition, in some embodiments, before the cutting process is performed, the gallium nitride device 20 and the silicon integrated circuit device 30 are polished to reduce the thickness of the gallium nitride device 20 and the thickness of the silicon integrated circuit device 30.

FIG12 is a circuit diagram of a semiconductor device according to an embodiment of the present invention. FIG12 is, for example, a circuit diagram of a semiconductor device of any of the aforementioned embodiments.

Referring to FIG. 12 , the semiconductor device includes a silicon integrated circuit device 30 and a gallium nitride device 20. The external connection terminals (115a, 115b) of the semiconductor device are input terminals and are connected to the silicon integrated circuit device 30. The external connection terminals (116a, 116b) of the semiconductor device are output terminals and are connected to the gallium nitride device 20. The gallium nitride device 20 is a high electron mobility transistor, and the silicon integrated circuit device 30 can be used as a driving device to control the potential of the gate of the gallium nitride device 20.

If the silicon integrated circuit device 30 and the gallium nitride device 20 are manufactured on the same wafer, the production process will be complicated, resulting in high production costs and poor production yield. The silicon integrated circuit device 30 and the gallium nitride device 20 of this embodiment are manufactured separately on different wafers, and then electrically connected to each other through the silicon carbide circuit board and the circuit above it, thereby reducing production costs and improving production yield.

10: Silicon carbide circuit board

20: Gallium nitride device

30: Silicon integrated circuit device

100: Silicon carbide substrate

2001: Sapphire base

2001t,3001t: Top surface

2101: Gallium nitride components

2201: The first redistribution structure

230:Connection terminal

3001:Silicon substrate

3101: Cutting field effect transistor device layer

311: Field effect transistor device

3201: Second redistribution structure

330:Connection terminal

400: Packaging materials

Claims (9)

A semiconductor device, comprising: a silicon carbide circuit board, comprising: a silicon carbide substrate, wherein the defect density of the silicon carbide substrate is greater than 9000 cm ^-2 ; and a circuit structure, located above the silicon carbide substrate, and comprising: a plurality of first internal connection terminals, a plurality of second internal connection terminals, and a plurality of external connection terminals, wherein the external connection terminals are configured to connect external signals; and a protective layer, located above the first internal connection terminals, the second internal connection terminals, and the external connection terminals, wherein the protective layer has a plurality of first openings, a plurality of second openings, and a plurality of third openings, wherein the first internal connection terminals are respectively located at the bottom of the first openings, the second internal connection terminals are respectively located at the bottom of the second openings, and the external connection terminals are respectively located at the bottom of the third openings; a plurality of first solders, respectively filled into the first openings; A plurality of second solders are respectively filled into the second openings; a gallium nitride device, comprising: a sapphire substrate; a gallium nitride component, located on the sapphire substrate; and a first redistribution structure, located on the gallium nitride component and soldered to the first internal connection terminal through the first solder; a silicon integrated circuit device, comprising: a silicon substrate; A field effect transistor element is located on the silicon substrate; and a second redistribution structure is located on the field effect transistor element and is soldered to the second internal connection terminal through the second solder; and a packaging material is located above the silicon carbide substrate, covers the sapphire substrate and the silicon substrate, and continuously extends from the gap between the gallium nitride device and the silicon integrated circuit device to the gap between the gallium nitride device and the circuit structure and the gap between the silicon integrated circuit device and the circuit structure, and the third opening is laterally located between the edge of the packaging material and the edge of the silicon carbide circuit board, wherein the protective layer contacts the bottom surface of the packaging material and extends from below the packaging material to the edge of the silicon carbide circuit board. A semiconductor device as described in claim 1, wherein the gallium nitride element includes a high electron mobility crystal transistor, and the high electron mobility crystal transistor is electrically connected to the field effect transistor element through the first redistribution structure, the circuit structure and the second redistribution structure. A semiconductor device as described in claim 1, wherein the gallium nitride element is located between the sapphire substrate and the silicon carbide substrate, and the field effect transistor element is located between the silicon substrate and the silicon carbide substrate, wherein the top surface of the sapphire substrate is coplanar with the top surface of the silicon substrate. A semiconductor device as described in claim 1, wherein the thickness of the silicon carbide substrate is 200 microns to 700 microns. A semiconductor device as described in claim 1, wherein the size of the external connection terminal is larger than the size of the first internal connection terminal and the size of the second internal connection terminal. A method for manufacturing a semiconductor device, comprising: forming a circuit structure on a silicon carbide substrate, wherein the defect density of the silicon carbide substrate is greater than 9000 cm ^-2 , wherein the circuit structure comprises: a plurality of first internal connection terminals, a plurality of second internal connection terminals, and a plurality of external connection terminals, wherein the external connection terminals are configured to connect external signals; and a protective layer, located on the first internal connection terminals, the second internal connection terminals, and the external connection terminals, wherein the protective layer has a plurality of first openings, a plurality of second openings, and a plurality of third openings, wherein the first internal connection terminals are respectively located at the bottom of the first openings, the second internal connection terminals are respectively located at the bottom of the second openings, and the external connection terminals are respectively located at the bottom of the third openings; forming a gallium nitride component layer on a sapphire wafer; Forming a first redistribution layer on the gallium nitride component layer; Cutting the sapphire wafer to form a plurality of gallium nitride devices, each of which includes a sapphire substrate, a first redistribution structure, and a gallium nitride component; Soldering at least one of the gallium nitride devices to the first internal connection terminal by a plurality of first solders, wherein the first solders are respectively filled into the first openings; Forming a field effect transistor component layer on the silicon wafer; Forming a second redistribution layer on the field effect transistor component layer; Cutting the silicon wafer to form a plurality of silicon integrated circuit devices, each of which includes a silicon substrate, a second redistribution structure, and a field effect transistor component; soldering at least one of the silicon integrated circuit devices to the second internal connection terminal by a plurality of second solders, wherein the second solders are respectively filled into the second openings; forming a packaging material on the silicon carbide substrate to cover the sapphire substrate of the at least one of the gallium nitride devices and the silicon substrate of the at least one of the silicon integrated circuit devices, and the packaging material continuously extends from the gap between the at least one of the gallium nitride devices and the at least one of the silicon integrated circuit devices to the gap between the at least one of the gallium nitride devices and the circuit structure and the gap between the at least one of the silicon integrated circuit devices and the circuit structure; and performing a cutting process on the silicon carbide substrate, To form a plurality of silicon carbide circuit boards, wherein at least one of the gallium nitride devices and at least one of the silicon integrated circuit devices are located on one of the silicon carbide circuit boards, and the third opening of one of the silicon carbide circuit boards is laterally located between an edge of the packaging material on one of the silicon carbide circuit boards and an edge of one of the silicon carbide circuit boards, wherein the protective layer contacts the bottom surface of the packaging material and extends from below the packaging material to the edge of one of the silicon carbide circuit boards. The method for manufacturing a semiconductor device as described in claim 6 further comprises: After soldering at least one of the gallium nitride devices to the first internal connection terminal and after soldering at least one of the silicon integrated circuit devices to the second internal connection terminal, simultaneously grinding the sapphire substrate of at least one of the gallium nitride devices and the silicon substrate of at least one of the silicon integrated circuit devices. The method for manufacturing a semiconductor device as described in claim 6 further comprises: Before soldering at least one of the gallium nitride devices to the first internal connection terminal, grinding the sapphire substrate or the sapphire wafer; and Before soldering at least one of the silicon integrated circuit devices to the second internal connection terminal, grinding the silicon substrate or the silicon wafer. The method for manufacturing a semiconductor device as described in claim 6 further comprises: After welding at least one of the gallium nitride devices to the first internal connection terminal and after welding at least one of the silicon integrated circuit devices to the second internal connection terminal, performing the cutting process on the silicon carbide substrate, wherein the silicon carbide substrate is a silicon carbide wafer.

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