200411902 A7 B7 五、發明説明（1 ) 【技術領域】 本發明是關於’應用在半導體裝置，特別是應用在， 下面有外部電極端子的半導體晶片上，經由中介配線基板 搭載複數個電子零件之架構的半導體模組很有效的技術。 【背景技術】 分別將裝配電晶體等的主動元件的半導體晶片、及裝 配電阻或電谷器等的被動兀件的晶片零件，搭載在配線基 板的半導體裝置的一個例子，有習知的倂合模組（hybrid module ) 〇 倂合模組有一習知的例子，亦即是，在下面有當作外 部電極端子的焊接區電極的電路基板的下面，搭載半導體 元件等的電路零件，且在上面搭載複數個分散的晶片狀電 子零件，且在上面安裝用以被覆上述晶片狀電子零件的金 屬外殼的構造。上述電路零件安裝在設於電路基板下面的 凹部，且在此電路零件的下面設散熱板，將電路零件產生 的熱量，以安裝狀態發散到母電路基板（例如，參照專利 文獻1 )。 〔專利文獻1〕 日本特開2000-58741號公報（第5-6頁，第1圖） 另一方面，行動通信的終端機器（攜帶式電話機）裝 配有很多電子零件。裝配在攜帶式電話機之發送系統的高 頻放大裝置（電力放大模組：PA )的小型•高功能化也 (請先閱讀背面之注意事項再填寫本頁) -裝·200411902 A7 B7 V. Description of the invention (1) [Technical Field] The present invention relates to a structure of 'applied to a semiconductor device, in particular, to a semiconductor wafer having external electrode terminals underneath, and a plurality of electronic components mounted via an interposer wiring substrate. The semiconductor module is a very effective technology. [Background Art] A conventional example of a semiconductor device mounted on a wiring board is a semiconductor device on which an active element such as a transistor is mounted, and a wafer component on which a passive element such as a resistor or a valley device is mounted. Hybrid module: There is a conventional example of hybrid modules. That is, a circuit component such as a semiconductor element is mounted on a lower surface of a circuit board having a pad electrode serving as an external electrode terminal below, and on the upper side. A structure in which a plurality of discrete wafer-shaped electronic parts are mounted and a metal case for covering the wafer-shaped electronic parts is mounted thereon. The above-mentioned circuit components are mounted in a recessed portion provided under the circuit substrate, and a heat sink is provided under the circuit component to dissipate heat generated by the circuit components to the mother circuit substrate in a mounted state (for example, refer to Patent Document 1). [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-58741 (page 5-6, Fig. 1) On the other hand, a terminal device (portable telephone) for mobile communication is equipped with many electronic parts. Compact and high-functional high-frequency amplifier (power amplifier module: PA) installed in the transmission system of a portable telephone (Please read the precautions on the back before filling this page) -Installation ·
J 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -5- 200411902 A7 ___ B7 五、發明説明（2 ) (請先閲讀背面之注意事項再填寫本頁) 正在快速進展。習知的通信方式之一有GSM ( Global System for Mobile Communication)方式，此 GSM 方式用 的電力放大模組之外形尺寸在目前是，縱10 mm、橫8 mm，但是下一世代的模組則可能是縱6 mm、橫5 mm的 產品會成爲主流。 而在 CDMA (code division multiple access)領域亦被 預測，目前的縱6 mm、橫6 mm的尺寸會依次被要求縮小 成縱5mm、橫5mm甚至於縱4mm、橫4mm的大小。 在如此超小型的電力放大模組，只是在配線基板架構 的模組基板表面，以二度空間方式安裝零件，將無法搭載 ，裝配有電晶體等主動元件的半導體晶片，或由電阻（晶 片電阻）、電容器（晶片電容器）等被動元件構成的晶片 零件，需要有立體方式的安裝。 將電路基板當作中介配線基板（interposer-插入件） 使用的如專利文獻1的半導體裝置，由於是在中介配線基 板搭載各種電子零件的構造，因此無法使半導體裝置的外 形較中介配線基板的外形小，這種構造的小型化很困難。 經濟部智慧財產局員工消費合作社印製 本發明的目的在，藉由提高搭載零件的安裝密度，達 成半導體裝置的小型化。 本發明的另一目的在提供，能夠提高發熱量大的半導 體晶片之散熱性的半導體裝置。 本發明的上述及其他目的以及新穎的特徵，可以從本 說明書的記述及附圖獲得進一步的瞭解。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） __ -6- 200411902 A7 五、發明説明（3 【發明揭示】 兹簡單說明本案所揭示的發明中具代表性者的槪要如 下。 一種半導體模組，包含： 以單片方式裝配1至複數個主動元件（電晶體），上 面有連接用電極，下面有外部電極端子的半導體晶片； 重疊配置在上述半導體晶片的上面，電氣方式連接在 上述半導體晶片的上述連接用電極的中介配線基板；以及 搭載於上述中介配線基板上，電氣方式連接在上述中 介配線基板的配線的電子零件（被動零件或被動零件及主 動零件），其特徵爲， 上述中介配線基板較上述半導體晶片小，上述中介配 線基板的邊緣不突出於上述半導體晶片邊緣的外側， 較之上述元件形成領域的半導體晶片的上面，離開上 述元件形成領域的領域之上面較低，連接離開上述元件形 成領域的半導體晶片領域與上述中介配線基板的配線之連 接用電極（第2連接電極）的高度，較連接上述半導體晶 片的元件形成領域內的電極與上述中介配線基板的配線之 連接用電極（第1連接電極）的高度爲高， 在上述元件形成領域外側的領域形成有從其上面貫穿 至下面的導體，此導體是電氣方式連接在設於半導體晶片 下面的外部電極端子， 一部分的上述導體成電氣方式連接在上述中介配線基 板的配線， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閏讀背面之注意事項再填寫本頁) -裝· 經濟部智慈財產局員工消費合作社印製 200411902 經濟部智慈財產局員工消費合作社印製 A7 B7 五、發明説明（4 ) 一部分的上述導體接觸於上述密封部。 【實施發明的最佳形態】 茲參照附圖詳細說明本發明的實施形態如下。再者， 在說明發明的實施形態用的所有圖面，具有同一功能者標 示相同記號，省略重覆的說明。 (實施形態1 ) 第1圖至第13圖是有關本發明一實施形態（實施形 態1 )的半導體模組（電力放大模組）之圖，第1圖至第 6圖是有關半導體模組的形狀及構造之圖，第7圖及第8 圖是有關半導體模組之安裝圖，第9圖至第13圖是有關 半導體模組的製造方法之圖。 本實施形態1的半導體模組（半導體裝置）1的架構 是如第2圖的截面圖所示，具有：半導體晶片2;重疊在 此半導體晶片2上面相連接的中介配線基板（interposer )3 ;搭載於上述中介配線基板3的複數個離散的電子零 件4 ;被覆設在半導體晶片2上面的上述中介配線基板3 及電子零件4之具有一定高度，.由絕緣性樹脂構成的密 封部5;設在上述半導體晶片2下面的散熱墊6及複數個 外部電極端子7。半導體晶片2的下面設有絕緣體8。散 熱墊6是形成在絕緣體8的表面。同時，外部電極端子7 是形成在部分去除絕緣膜8的領域，而電氣方式連接在導 體32。散熱墊6由導體層構成，廣大分布在半導體晶片2 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -8- ---Γ----I I n ΙΊ n —ί ^ ~r-ϋ I_線 (請先閲讀背面之注意事項再填寫本頁) 200411902 經濟部智慧財產局Μ工消費合作社印製 A7 _B7五、發明説明（5 ) 的下面中央，具有可以有效從半導體晶片2的下面向外部 發散形成在半導體晶片2的電晶體所產生之熱量的功能。 在本實施形態1，散熱墊6是在第1基準電位，亦即在接 地電位。 外部電極端子7由突起電極（突塊電極）構成，如第 3圖的底面圖所示，沿著四角形狀的半導體晶片2的各邊 配置。外部電極端子7重疊在從半導體晶片2的上面貫穿 至下面配設的導體3 2，成爲電氣方式連接的狀態。本實 施形態1的外部電極端子7及散熱墊6是由不含Pb的焊 錫（以下稱爲無Pb焊錫）所形成。無Pb焊錫使用，例如 在Sn、Ag、Cu內含有Zn或Bi的焊錫。 半導體晶片2與中介配線基板3是以突起電極構成的 連接用電極10連接在一起。連接用電極10是由：配置在 設有被覆半導體晶片2的元件形成領域上的絕緣膜9領域 的第1連接用電極1 0a ;與設在離開元件形成領域的第2 連接用電極10b所構成。 在元件形成領域上，於規定處所，在絕緣膜9形成有 接觸孔，此孔的孔底露出有連接至電晶體的各電極等的配 線。第1連接用電極1 0a是電氣方式連接在此露出的配線 。因此，第1連接用電極1 0a是用以連接形成在半導體晶 片2的電晶體等的各電極與中介配線基板3的配線。 離開元件形成領域的領域較元件形成領域的表面低， 在此領域設有上下貫穿的上述導體3 2。而在一部分的導 體32上配置有上述的第2連接用電極10b (第2圖右端 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事 0— 項再填. 裝— 寫本頁) .!訂 200411902 Α7 Β7 五、發明説明（6 ) 的第2連接用電極1 Ob)。此第2連接用電極1 Ob是經由 導體32電氣方式連接在外部電極端子7。因此，可以藉 由第2連接用電極1 Ob連接中介配線基板3的配線與外部 電極端子7。 同時，第2圖右端的上面未配置有第2連接用電極 10b的導體32，因其上面重疊有密封部5，因此，此導體 32有將密封部5的熱量傳遞到外部電極端子7的作用。 其結果，當將半導體模組1安裝於安裝基板時，可經由導 體32及外部電極端子7迅速將密封部5的熱量發散到安 裝基板。由於在各處配置這種散熱用的外部電極端子7， 密封部5可以有效的散熱。 半導體晶片2的上面與中介配線基板3的下面之間隔 是，離開元件形成領域的領域較之元件形成領域寬，因此 ，較之第1連接用電極10a的連接高度，第2連接用電極 10b的連接高度較高。因此，第2連接用電極l〇b較第1 連接用電極10a大。 半導體模組1是依縱橫排列配置製品形成部的半導體 母基板（晶圓）製成。在晶圓的各製品形成部上重疊搭載 ，搭載有電子零件4的中介配線基板3，然後在晶圓的上 面形成一定高度的絕緣性樹脂層，接著將晶圓縱橫切斷， 製造複數個半導體模組1，因此，半導體模組1是如第1 圖的平面圖所示，成爲扁平的立方體，高度（厚度）也是 如第2圖所示，成爲一定値。 本實施形態1是如第4圖所示，搭載於中介配線基板 本紙張尺度適用中國國家標準（CNS ) A4規格（210Χ 297公釐） (請先閲讀背面之注意事項再填寫本頁) -裝- 經濟部智慧財產局g(工消費合作社印製 200411902 經濟部智慈財產局員工消費合作社印製 A7 __B7五、發明説明（7 ) 3上面的離政的電子零件，是複數個晶片狀的電子零件4 。晶片狀電子零件4是，例如’晶片電阻、晶片電容器、 晶片電感器等的晶片零件。再者，若改變中介配線基板3 上面的電極圖案（配線圖案），也可以搭載裝配有主動元 件的電子零件’亦即，也可以搭載半導體晶片或用樹脂密 封的小型的電晶體等。 密封部5是，以例如轉移塑模法形成，例如，以熱膨 脹率 α爲 180 〜200Μ0·6/α(：、揚氏（Young)率 E 爲 1〜200 MPa的矽樹脂形成。藉此，可以在進行依顧客需求安裝的 回流過程時’獲得防止封裝體內的焊錫膨脹造成的焊錫溢 出的效果。 半導體晶片2是依例如砂單結晶基板形成，藉由常用 的外延成長、成爲施體或受體之雜質的選擇擴散等，在規 定處所形成1個至複數個電晶體等的主動元件等的電子元 件。此等各電子元件的電極可視需要以配線連接，同時， 規定的電極是當作電極端子拉到半導體晶片2的上面。此 電極端子上設有連接用電極10 (第1連接用電極l〇a )( 參照第2圖）。第1連接用電極1 〇a是連接在中介配線基 板3下面的電極。 形成在半導體晶片2的電晶體的構造是例如第6圖所 示。P型高電阻的Si基板構成的半導體基板11的主面（ 上面）形成有由P型高電阻S i構成的外延層12，在此外 延層1 2的表面重疊且選擇性形成有閘極氧化膜1 3及層間 絕緣膜1 4。 (請先閱讀背面之注意事項再填寫本頁) -裝· J*11ί. 線 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -11 - 200411902 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 外延層12的表層部分成環狀形成有p型的井領域15 及N型的源極領域16。源極領域16的內周緣位於離開井 領域1 5的內周緣規定距離的內側，源極領域1 6的外周緣 則形成在離開井領域1 5的外周緣規定距離的內側。同時 ，源極領域1 6的底部較井領域1 5的底部淺，兩者間分開 有規定的間隔。 在環狀的井領域1 5之中心的外延層1 2的表層部分設 有N型的汲極領域1 7。此汲極領域1 7不接觸於井領域1 5 。在汲極領域17的外周之從汲極領域17至進入井領域 1 5內周緣少許的領域，設有N型的汲極偏移領域19。汲 極領域17上的閘極氧化膜13及層間絕緣膜14被選擇性 去除，而包含此去除的接觸孔，在層間絕緣膜14上延設 有汲電極20。同時，源極領域16上的閘極氧化膜13及 層間絕緣膜14也被選擇性去除，而包含此去除的接觸孔 ，在層間絕緣膜14上延設有源電極21。 從汲極偏移領域1 9至源極領域1 6的閘極氧化膜1 3 上設有閘電極22。此閘電極22被層間絕緣膜14覆蓋， 但其一部分藉由閘極配線拉出到層間絕緣膜14上，成爲 閘極配線。在此閘極配線、汲電極20及源電極2 1上設有 最終鈍化（f i n a 1 p a s s i v a t i ο η )膜的絕緣膜9。閘極配線、 汲電極20及源電極21是成爲配線，在層間絕緣膜14與 絕緣膜9之間延伸，而裝配在規定的電路。而延設在層間 絕緣膜1 4與絕緣膜9間的配線上之一部分的絕緣膜9被 去除，此被去除部分（孔）的底部分別露出配線，而成爲 (請先閱讀背面之注意事項再填寫本頁) •裝. 訂 線 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） -12 - 200411902 A7 B7 五、發明説明（9 ) 連接端子。此連接端子上設有上述第1連接用電極1 〇a。 連接用電極10也是使用無pb焊錫。 (請先閱讀背面之注意事項再填寫本頁) 在井領域1 5的外周緣部分的外延層1 2設有可以到達 半導體基板Π的表層部分的P型領域25，同時’在P型 領域25的表層部分形成有雜質濃度很高的P型的接點領 域26。P型領域25及接點領域26是沿著環狀的井領域 1 5的外周配設成環狀。連接在源極領域1 6的上述源電極 2 1貫穿層間絕緣膜1 4與閘極氧化膜1 3，電氣方式連接在 接點領域26。而半導體基板1 1是與源電極2 1同電位。 本實施形態1的源電極21是在第1基準電位，亦即在接 地電位。 又如第2圖所示，在離開半導體晶片2的元件形成領 域的領域（沿四方形狀晶片的各邊的領域），從上面至下 面設有導體32。亦即，如第8圖所示，在離開元件形成 領域的半導體晶片2部分設有貫穿孔30，同時，此貫穿 孔30的內周面是覆蓋絕緣膜3 1，其內側塡充有導體32。 此導體32的上面連接在上述第2連接用電極10b，或接 觸於密封部5。 經濟部智慧財產局員工消費合作社印製 第5圖是表示搭載於半導體晶片2的中介配線基板3 的連接狀態，及搭載於中介配線基板3的電子零件4的連 接狀態的模式圖。半導體晶片2之半導體基板1 1的表層 部分被層間絕緣膜1 4覆蓋，同時在此層間絕緣膜1 4上以 規定的圖案形成有配線42。例如，配線42是由下層的第 1層42a與形成在此第1層42a上的第2層42b所構成’ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 200411902 A7 B7 — 五、發明説明（） (請先閱讀背面之注意事項再填寫本頁) 第1層42a是由Ti (下層）/TiN構成，而第2層42b是 由Ti (下層）/ A1 -Cu-Si構成。而，此等配線42是由被 覆半導體基板11表面的絕緣膜9所覆蓋，但配置第1連 接用電極1 0a處的絕緣膜9被去除。此露出之配線42的 表面設有電鍍膜44。電鍍膜44是由下層44a與上層44b 構成的雙層構造。例如，下層44a是Ti層，上層44b是 Ni層。而在其上安裝由無Pb焊錫構成的第1連接用電極 1 Oa 〇 中介配線基板3是由印刷電路基板（PCB ) 45構成， 在上下面及內部有規定圖案的配線層46，同時，此等配 線層46是經由塡充在通孔47的導體49電氣方式連接在 一起。通孔47的內周面形成有導電性的電鍍膜48。內部 的配線層46呈複數層。印刷電路基板45的上下面的配線 層46，連接電極的部分設有電鍍膜50。此電鍍膜50是由 下電鍍膜50a，及形成在此下電鍍膜50a上的上電鍍膜 50b構成。例如，下電鍍膜50a是由Ni電鍍膜構成，上 電鍍膜50b是由Au電鍍膜構成。 經濟部智慧財產局員工消費合作社印製 中介配線基板3的下面經由第1連接用電極1 0a連接 在半導體晶片2的上面。亦即，由第1連接用電極1 〇a將 設在半導體晶片2的配線42之連接部分的電鍍膜44，與 設在中介配線基板3下面的配線層46之連接部分的電鍍 膜50，電氣方式連接在一起。同時，中介配線基板3的 上面搭載有晶片狀的電子零件4。晶片狀電子零件4呈在 兩端分別有電極4a的構造，各電極4a以無Pb焊錫55電 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 200411902 A7 B7 五、發明説明（11 ) 氣方式連接在設於中介配線基板3上面的配線層46之連 接部分的電鍍膜50上。 (請先閱讀背面之注意事項再填寫本頁) 中介配線基板3較半導體晶片2小，且，中介配線基 板3的端部不會從半導體晶片2的端部突出外部。因此， 半導體晶片2的外形直接成爲半導體模組1的外形。 同時，中介配線基板3的配線與半導體晶片2下面的 外部電極端子7，因爲是藉由貫穿狀態配設在半導體晶片 2的短形導體32電氣方式連接在一起（參照第2圖）， 因此配線可以低阻抗化。 由於半導體模組1是，例如，半導體晶片2的厚度是 0.0 5 mm ;中介配線基板3的厚度是0.4 mm ;晶片狀電子 零件4的厚度是0.6 mm ;連接半導體晶片2與中介配線 基板3的連接用電極10的厚度是0.02 mm前後；密封部 5的高度（厚度）是1.0 mm前後，因此，從外部電極端 子7的下面至密封部5的上面的高度成爲1.1 mm前後， 相當薄。 經濟部智慧財產局員工消費合作社印製 如此的半導體模組1是如第7圖所示，安裝在由PCB 基板構成的安裝基板60使用。安裝基板60在上下面及內 部有規定圖案的配線層61，同時，此等配線層61是經由 塡充在通孔的導體64成電氣方式相連接。內部的配線層 61有複數層。在安裝基板60的上下面的配線層46 ’爲了 提高連接性能，在連接電極的部分設有電鍍膜。亦即，第 8圖是表示連接在安裝基板60的半導體晶片部分的模式 圖。塡充在上下貫穿半導體晶片2的貫穿孔30的導體32 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 200411902 A7 B7 ίο - —---— 五、發明説明（） (請先閱讀背面之注意事項再填寫本頁) 是，經由外部電極端子7電氣方式連接在安裝基板60上 面的配線層61。配線層61的表面設有電鍍膜65。電鍍膜 65是由下層65a及上層65b構成的雙層構造。例如，下 層65a是Ni層，上層65b是Au層。而在此上面安裝由無 Pb焊錫構成的外部電極端子7。 其次，再參照第9圖至第14圖，說明本實施形態1 的半導體模組1的製造方法。半導體模組1是如第9圖所 示，對經過在晶圓上形成元件（S 101 )、形成深孔（S 102)、深孔絕緣處理（S 103)、在深孔塡充導體（S 104 )、背面硏磨（S 105 )、背面絕緣處理（S 106 )、晶圓 檢查（S 107)、形成連接用電極（S 108)之各製程的晶 圓，經由搭載中介配線基板（S 109 )、回流（S 1 10 )的 製程，在晶圓上分別搭載，經過不同製程之在配線母基板 形成突起電極（S 201 )、在配線母基板搭載零件（S 202 )、回流（S 203 )、切斷配線母基板（S 204 )的各製程 製成的中介配線基板，接著，再經過，在晶圓上面形成絕 緣樹脂層（S 1 1 1 )、在晶圓下面形成電極（S 1 1 2 )、測 試（S 113)，分割晶圓（S 114)的各製程而製成。 經濟部智慧財4局員工消費合作社印製 其次再參照第1 0圖至第1 3圖說明半導體模組1的製 造方法。本實施形態1的半導體模組1在製造時，是使用 半導體母基板（晶圓）及配線母基板。半導體母基板（晶 圓）是在步驟S 101至步驟S 1 14的過程使用，配線母基 板則在不同製程的步驟S 201至步驟S 204的過程使用。 配線母基板在最終製程，沿製品形成部的邊緣縱橫切斷， -16· 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 200411902 A7 B7 — — 五、發明説明（） 形成複數個中介配線基板3。此中介配線基板3是在S 1 09的製程分別搭載於晶圓的上面。晶圓則在最終製程的 S 114，沿製品形成部的邊緣縱橫切斷，製成複數個半導 體模組1。 在晶圓及配線母基板，縱橫排列配置由四方形領域形 成的製品形成部。晶圓的單一製品形成部是第1圖及第2 圖所示的四方形狀的半導體晶片2，配線母基板的製品形 成部是第1圖及第2圖所示的四方形狀的中介配線基板3 。配線母基板的製品形成部是較晶圓的製品形成部爲小的 四方形狀。 在說明S 101至S 114的製程之前，先參照第1 1圖 (a)〜（c)說明S 201至S 204的製程。 配線母基板70是如第1 1圖（a )所示，由平坦的印 刷電路基板構成，使可以排列配置η行m列製品形成部f 的大小。第1 1圖是爲了說明上的方便，以4列狀態表示 配線母基板70。製品形成部f的印刷電路基板的構造是 上述的中介配線基板3的構造。 對這種配線母基板70，如第11圖（a)所示，在配 線母基板70的上面供應形成搭載電子零件4用的突起電 極71。例如，藉由印刷與加熱，形成突起電極71 ( S 201 )。突起電極71是例如無Pb焊錫的球電極。突起電極 7 1是分別形成在第5圖所示之配線層46的電鍍膜50上 。也可以安裝球電極取代印刷。 接著，如第11圖（b )所示，在配線母基板70上面 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝. 訂 經濟部智慧財產局員工消費合作社印製 -17- 200411902 Α7 Β7 五、發明説明（） (請先閱讀背面之注意事項再填寫本頁) 搭載電子零件4，且藉由回流加以固定（S 202、S 203 ) 。亦即，如第1 1圖（b )所示，以電極4a重疊在各製品 形成部f之突起電極71上狀供給將電子零件4後，藉由 一定溫度的加熱，使上述突起電極71暫時溶融（回流） ，藉此將電子零件4用無Pb焊錫55搭載於配線母基板 70 (參照第5圖）。被搭載的電子零件4是，例如，晶片 形電阻器、晶片形電容器、晶片形電感器等的被動零件。 接著，如第11圖（c )所示，縱橫切斷配線母基板 70。切斷動作是沿相臨接的製品形成部f的境界線切斷。 藉此製成複數個中介配線基板3。 經濟部智慈財產局8工消費合作社印製 另一方面，製造半導體模組1時是如第10圖（a)所 示，先準備半導體母基板（晶圓）75。第10圖（a)所示 的晶圓75也是縱橫排列配置有製品形成部e，有L行Μ 列。在第10圖（a )是爲說明的方便上形成爲8列。而在 各製品形成部e已經形成有連接電晶體等的主動元件或各 電子元件的配線，甚至是最終鈍化膜等的絕緣膜4 3 ( S 101)。元件形成部分是方便上形成在以絕緣膜9代表的 部分下。製品形成部e是成爲半導體晶片2的部分。實際 上，晶圓是使用，例如直徑6吋、厚度750 μιη的矽單晶 基板。 接著，如第10圖（b )所示，藉由蝕刻在製品形成部 e的規定處所形成深孔76 ( S 102)。深孔76是對應，例 如第3圖所示的外部電極端子7形成。深孔76是直徑 10〜20 μιη左右的圓形孔，其深度是較1〇〇 μιη爲深。這是 -18- 本紙張尺度適用中國國家標準（CMS ) Α4規格（210Χ 297公釐） 200411902 A7 — B7 15 ·~-~- ' 五、發明説明（） 因爲，晶圓是在最後階段藉由硏磨去除背面使其厚度爲 100 μιη，而在這個時候要使上述深孔成爲貫穿孔30的緣 故。 接著，如第1 1圖（c )所示，在深孔76的內周面形 成絕緣膜31 ( S 103 )。絕緣膜31是由，例如Si〇2膜構 成，可以藉由，例如以抗蝕膜覆蓋深孔76以外的晶圓75 的表面，加以熱處理而形成。爲了達成電氣絕緣分離’絕 緣膜3 1的厚度是例如1 μιη左右的厚度。在第1 〇圖（c ) 〜（f)是表示製品形成部e的一部分。 接著，如第10圖（d)所示，在深孔76內塡充導體 32塡埋深孔76 ( S 104)。導體32是由例如Cu構成。 接著，如第10圖（e)所示，將晶圓75的背面硏磨 去除規定厚度（S 105 )。藉此背面硏磨，晶圓75的厚度 成爲100 μιη左右，深孔76成爲貫穿孔30。同時，導體 3 2便貫穿存在於晶圓7 5的上面至下面。背面硏磨是要使 導體32露出在晶圓75的下面。 接著，如第10圖（f)所示，進行背面絕緣處理（S 1 06 )，在晶圓75的背面選擇性形成絕緣膜8。絕緣體8 是由Si〇2膜構成，可以在不形成絕緣膜的部分形成抗蝕 膜，進行熱處理而形成。爲了達成電氣絕緣分離，絕緣膜 8厚度是例如2 μιη前後。絕緣膜8也可以使用，在晶圓 7 5的下面全區域藉氧化處理形成後，以蝕刻去除規定處 所的方法。 接著，以晶圓的狀態進行各製品形成部e的電氣特性 本紙張尺度適用中國國家標準（CNs ) A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝· 訂 經濟部智慧財產局員工消費合作社印製 •19- 200411902 A7 B7 五、發明説明（16 ) ^ 檢查（晶圓檢查）（S 107 )。 (請先閱讀背面之注意事項再填寫本頁) 接著，如第12圖（a )所示，在晶圓75上面的規定 處所，亦即在與中介配線基板3的電氣連接處所形成連接 用電極10 ( S 108 )。此連接用電極10是無Pb焊錫，成 爲球狀電極。連接用電極10是，例如藉由印刷與加熱形 成爲半球狀或球狀。也可以安裝球電極。 形成此連接用電極1 0時，在元件形成領域上形成第 1連接用電極l〇a，在離開元件形成領域的規定的導體32 上形成第2連接用電極1013。此等連接用電極10，亦即第 1連接用電極10a與第2連接用電極l〇b，是用以電氣方 式連接半導體晶片2與中介配線基板3者。同時，在元件 形成領域部分與離開元件形成領域部分間有台階差。因此 ，第2連接用電極l〇b較第1連接用電極10a大（高度高 )° 經濟部智慧財產局員工消費合作社印製 接著，如第12圖（b )所示，將藉由上述製程S 201〜S 204製造的搭載第11圖（c)所示電子零件4的中 介配線基板3，如第12圖（a )所示，定位配置在晶圓7 5 上面的各製品形成部e ( S 109 )後，將上述連接用電極 10回流（S 11 〇 )，而如第12圖（b )所示，藉由連接用 電極10將中介配線基板3分別固定（搭載）在晶圓75上 〇J Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) -5- 200411902 A7 ___ B7 V. Description of the invention (2) (Please read the note on the back first (Fill in this page again) This is progressing fast. One of the known communication methods is the GSM (Global System for Mobile Communication) method. The external dimensions of the power amplification module used in this GSM method are currently 10 mm vertical and 8 mm horizontal, but the next generation of modules is It may be that products with a length of 6 mm and a width of 5 mm will become the mainstream. In the field of CDMA (code division multiple access), it is predicted that the current size of 6 mm in length and 6 mm in length will be required to be reduced to 5 mm in length, 5 mm in width, and even 4 mm in length and 4 mm in length. In such an ultra-small power amplifier module, only a two-dimensional space is used to mount components on the surface of the module substrate of the wiring substrate structure. It will not be able to be mounted. Semiconductor chips equipped with active components such as transistors or resistors (chip resistors) ), Capacitors (chip capacitors) and other passive components, chip components need to be installed in a three-dimensional manner. A semiconductor device such as Patent Document 1 in which a circuit board is used as an interposer-interposer has a structure in which various electronic components are mounted on the interposer. Therefore, the shape of the semiconductor device cannot be made smaller than that of the interposer. Small, it is difficult to miniaturize this structure. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economics The present invention aims to reduce the size of semiconductor devices by increasing the mounting density of mounted components. Another object of the present invention is to provide a semiconductor device capable of improving the heat radiation property of a semiconductor wafer having a large amount of heat. The above and other objects and novel features of the present invention can be further understood from the description of the specification and the accompanying drawings. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) __ -6- 200411902 A7 V. Description of the invention (3 [Disclosure of the invention] Here is a brief description of the representative of the inventions disclosed in this case: A semiconductor module comprising: a semiconductor wafer in which one to a plurality of active elements (transistors) are assembled in a single piece, with a connection electrode on the top and an external electrode terminal on the bottom; the semiconductor wafer is superimposed and arranged on the semiconductor wafer, electrically An interposer wiring substrate connected to the connection electrode of the semiconductor wafer; and an electronic component (passive component or passive component and active component) mounted on the interposer wiring substrate and electrically connected to the wiring of the interposer wiring substrate. The intermediate wiring substrate is smaller than the semiconductor wafer, and the edge of the intermediate wiring substrate does not protrude from the outside of the edge of the semiconductor wafer. Low, connection leaves shape above The height of the connection electrode (second connection electrode) of the semiconductor wafer field and the above-mentioned interposer wiring substrate is higher than that of the connection electrode (the second connection electrode) of the electrode in the element formation field of the semiconductor wafer and the interposer wiring substrate. 1 connecting electrode) is high, and a conductor extending from the upper part to the lower part is formed in an area outside the above-mentioned element formation area. This conductor is electrically connected to an external electrode terminal provided below a semiconductor wafer, and a part of the conductor is formed. Electrically connected to the wiring of the above-mentioned intermediary wiring board, this paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of the Property Bureau 200411902 Printed by the Consumer Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (4) Part of the above-mentioned conductor is in contact with the above-mentioned sealed portion. [Best Form for Implementing the Invention] Please refer to the attached drawings The embodiments of the present invention will be described in detail as follows. In all the drawings used in the embodiment, those having the same function are marked with the same symbols, and repeated descriptions are omitted. (Embodiment 1) Figures 1 to 13 show a semiconductor module according to an embodiment (Embodiment 1) of the present invention. (Electric Power Amplifier Module), Figures 1 to 6 are diagrams related to the shape and structure of the semiconductor module, and Figures 7 and 8 are mounting diagrams related to the semiconductor module, Figures 9 to 13 The figure shows a method for manufacturing a semiconductor module. The structure of a semiconductor module (semiconductor device) 1 according to the first embodiment is as shown in the cross-sectional view of FIG. 2 and includes: a semiconductor wafer 2; The interposer 3 connected to the above; the discrete electronic parts 4 mounted on the interposer 3; the interposer 3 and the electronic part 4 covered on the semiconductor wafer 2 have a certain height, A sealing portion 5 made of an insulating resin; a heat radiation pad 6 and a plurality of external electrode terminals 7 provided below the semiconductor wafer 2; An insulator 8 is provided on the lower surface of the semiconductor wafer 2. The heat radiation pad 6 is formed on the surface of the insulator 8. Meanwhile, the external electrode terminal 7 is formed in a region where the insulating film 8 is partially removed, and is electrically connected to the conductor 32. The heat sink 6 is composed of a conductor layer, and is widely distributed on the semiconductor wafer. 2 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -8- --- Γ ---- II n ΙΊ n —ί ^ ~ r-ϋ I_ line (please read the notes on the back before filling this page) 200411902 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, M Industrial Consumer Cooperative A7 _B7 V. The lower center of the description of the invention (5), which can effectively The lower surface of 2 functions to dissipate the heat generated by the transistor formed on the semiconductor wafer 2 to the outside. In the first embodiment, the heat radiation pad 6 is at the first reference potential, that is, at the ground potential. The external electrode terminal 7 is composed of a protruding electrode (bump electrode), and is arranged along each side of the quadrangular semiconductor wafer 2 as shown in the bottom view of FIG. 3. The external electrode terminal 7 is superposed on the conductor 32 arranged from the upper surface to the lower surface of the semiconductor wafer 2 to be electrically connected. The external electrode terminal 7 and the heat radiation pad 6 of the first embodiment are formed of Pb-free solder (hereinafter referred to as Pb-free solder). Pb-free solder is used, for example, solder containing Zn or Bi in Sn, Ag, Cu. The semiconductor wafer 2 and the interposer wiring substrate 3 are connected together by a connection electrode 10 composed of a bump electrode. The connection electrode 10 is composed of a first connection electrode 10a provided in the field of the insulating film 9 provided in the element formation area where the covered semiconductor wafer 2 is provided, and a second connection electrode 10b provided in the element formation area provided away from the element. . In the field of element formation, contact holes are formed in the insulating film 9 at predetermined locations, and the bottoms of the holes expose wirings such as electrodes connected to transistors. The first connection electrode 10a is an electrically connected wiring exposed here. Therefore, the first connection electrode 10a is a wiring for connecting each electrode such as a transistor formed on the semiconductor wafer 2 and the intermediate wiring substrate 3. The area leaving the element formation area is lower than the surface of the element formation area, and the above-mentioned conductors 32 are provided in this area. The above-mentioned second connection electrode 10b is arranged on a part of the conductor 32 (the right end of the second figure in this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm)) (please read the note on the back 0-item first) (Fill it again (install — write this page).! Order 200411902 Α7 Β7 V. The second connection electrode 1 Ob of the invention description (6). The second connection electrode 1 Ob is electrically connected to the external electrode terminal 7 via a conductor 32. Therefore, the wiring of the interposer wiring board 3 and the external electrode terminal 7 can be connected by the second connection electrode 1 Ob. At the same time, the conductor 32 of the second connection electrode 10b is not disposed on the upper surface of the right end of FIG. 2, and the sealing portion 5 is superposed thereon. Therefore, the conductor 32 has the function of transmitting the heat of the sealing portion 5 to the external electrode terminal 7. . As a result, when the semiconductor module 1 is mounted on the mounting substrate, the heat of the sealing portion 5 can be quickly dissipated to the mounting substrate via the conductor 32 and the external electrode terminal 7. Since such external electrode terminals 7 for heat radiation are arranged in various places, the sealing portion 5 can efficiently dissipate heat. The distance between the upper surface of the semiconductor wafer 2 and the lower surface of the interposer wiring substrate 3 is that the area away from the element formation area is wider than the element formation area. Therefore, the distance between the first connection electrode 10a and the second connection electrode 10b is larger than the connection height of the first connection electrode 10a. The connection height is high. Therefore, the second connection electrode 10b is larger than the first connection electrode 10a. The semiconductor module 1 is made of a semiconductor mother substrate (wafer) in which product forming portions are arranged in a vertical and horizontal arrangement. The intermediate product wiring board 3 on which the electronic components 4 are mounted is superimposed on each product forming portion of the wafer, and then an insulating resin layer of a certain height is formed on the wafer, and then the wafer is cut vertically and horizontally to manufacture a plurality of semiconductors. Module 1, therefore, the semiconductor module 1 is a flat cube as shown in the plan view of FIG. 1, and the height (thickness) is also constant as shown in FIG. This embodiment 1 is shown in FIG. 4 and is mounted on an interposer wiring substrate. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) (please read the precautions on the back before filling this page). -Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs (printed by the Industrial and Consumer Cooperatives 200411902 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed A7 __B7 V. Invention Description (7) 3 The departed electronic parts above are multiple wafer-shaped electronics Component 4. The wafer-shaped electronic component 4 is, for example, a chip component such as a chip resistor, a chip capacitor, a chip inductor, etc. Furthermore, if the electrode pattern (wiring pattern) on the interposer wiring substrate 3 is changed, it can also be mounted with an active component. The electronic component of the element, that is, a semiconductor wafer, a small transistor sealed with a resin, or the like can also be mounted. The sealing portion 5 is formed by, for example, a transfer molding method, for example, with a thermal expansion coefficient α of 180 to 200 M0 · 6 / α (:, Young's ratio E is 1 ~ 200 MPa, silicone resin is formed. Thereby, it is possible to 'prevent packaging prevention' during the reflow process of mounting according to customer requirements The effect of solder overflow caused by the expansion of the internal solder. The semiconductor wafer 2 is formed by, for example, a single-crystal sand substrate, and is commonly formed by epitaxial growth, selective diffusion of impurities that become donors or acceptors, and the like. A plurality of electronic components such as transistors and other active components. The electrodes of each of these electronic components can be connected by wiring as required. At the same time, a predetermined electrode is drawn as an electrode terminal on the semiconductor wafer 2. This electrode terminal is provided with Connection electrode 10 (first connection electrode 10a) (see FIG. 2). The first connection electrode 10a is an electrode connected below the interposer wiring substrate 3. The structure of the transistor formed on the semiconductor wafer 2 For example, as shown in Fig. 6. An epitaxial layer 12 composed of a P-type high resistance Si is formed on the main surface (upper surface) of a semiconductor substrate 11 composed of a P-type high-resistance Si substrate, and the surface of the epitaxial layer 12 is overlapped. A gate oxide film 13 and an interlayer insulating film 1 4 are selectively formed. (Please read the precautions on the back before filling this page) -Packing · J * 11ί. The size of the paper is applicable to the Chinese National Standard (CNS) Α4 Specifications (210 × 297 mm) -11-200411902 Α7 Β7 Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () The surface layer of the epitaxial layer 12 forms a ring with a p-type well field 15 and an N-type source The polar region 16. The inner periphery of the source region 16 is located inside a predetermined distance from the inner periphery of the well region 15 and the outer periphery of the source region 16 is formed inside a predetermined distance from the outer periphery of the well region 15. At the same time The bottom of the source region 16 is shallower than the bottom of the well region 15 and the two are separated by a predetermined interval. The surface layer of the epitaxial layer 12 in the center of the annular well region 15 is provided with an N-type drain. Polar field 1 7. This drain region 17 does not touch the well region 15. An N-type drain offset region 19 is provided on the outer periphery of the drain region 17 from the drain region 17 to the entry well region 15. The gate oxide film 13 and the interlayer insulating film 14 on the drain region 17 are selectively removed, and a drain electrode 20 is provided on the interlayer insulating film 14 including the removed contact hole. At the same time, the gate oxide film 13 and the interlayer insulating film 14 on the source region 16 are also selectively removed, and the source electrode 21 is extended on the interlayer insulating film 14 including the removed contact hole. A gate electrode 22 is provided on the gate oxide film 1 3 from the drain offset region 19 to the source region 16. The gate electrode 22 is covered with the interlayer insulating film 14, but a part of the gate electrode 22 is pulled out onto the interlayer insulating film 14 through the gate wiring, and becomes a gate wiring. An insulating film 9 of a final passivation (f i n a 1 p a s s i v a t i ο η) film is provided on the gate wiring, the drain electrode 20 and the source electrode 21. The gate wiring, the drain electrode 20, and the source electrode 21 are wirings, extend between the interlayer insulating film 14 and the insulating film 9, and are assembled in a predetermined circuit. One part of the insulating film 9 extending on the wiring between the interlayer insulating film 14 and the insulating film 9 is removed, and the bottom of the removed part (hole) respectively exposes the wiring, and becomes (please read the precautions on the back first) (Fill in this page) • Binding. The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -12-200411902 A7 B7 V. Description of the invention (9) Connection terminal. The connection terminal is provided with the first connection electrode 10a. The connection electrode 10 is also made of pb-free solder. (Please read the precautions on the back before filling this page.) The epitaxial layer 12 on the outer peripheral part of the well area 15 is provided with a P-type area 25 that can reach the surface layer portion of the semiconductor substrate Π, and 'in the P-type area 25 A P-type contact region 26 having a high impurity concentration is formed on the surface layer portion. The P-type area 25 and the contact area 26 are arranged in a ring shape along the outer periphery of the ring-shaped well area 15. The source electrode 21 connected to the source region 16 penetrates the interlayer insulating film 14 and the gate oxide film 13 and is electrically connected to the contact region 26. The semiconductor substrate 11 is at the same potential as the source electrode 21. The source electrode 21 of the first embodiment is at the first reference potential, that is, at the ground potential. As shown in FIG. 2, conductors 32 are provided from the top to the bottom of the area (area along each side of the tetragonal wafer) of the semiconductor wafer 2. That is, as shown in FIG. 8, a through-hole 30 is provided in a portion of the semiconductor wafer 2 away from the element formation area. At the same time, the inner peripheral surface of the through-hole 30 is covered with the insulating film 31 and the inner side thereof is filled with the conductor 32. . The upper surface of this conductor 32 is connected to the second connection electrode 10b, or is in contact with the sealing portion 5. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs FIG. 5 is a schematic diagram showing the connection state of the interposer wiring board 3 mounted on the semiconductor wafer 2 and the connection state of the electronic parts 4 mounted on the interposer wiring board 3. The surface layer portion of the semiconductor substrate 1 1 of the semiconductor wafer 2 is covered with an interlayer insulating film 14, and wirings 42 are formed on the interlayer insulating film 14 in a predetermined pattern. For example, the wiring 42 is composed of the first layer 42a of the lower layer and the second layer 42b formed on the first layer 42a. 'This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 200411902 A7 B7 — 5. Description of the invention () (Please read the notes on the back before filling out this page) The first layer 42a is composed of Ti (lower layer) / TiN, and the second layer 42b is composed of Ti (lower layer) / A1 -Cu-Si Make up. These wirings 42 are covered with the insulating film 9 covering the surface of the semiconductor substrate 11, but the insulating film 9 at the position where the first connection electrode 10a is disposed is removed. A plating film 44 is provided on the surface of this exposed wiring 42. The plated film 44 has a double-layered structure including a lower layer 44a and an upper layer 44b. For example, the lower layer 44a is a Ti layer, and the upper layer 44b is a Ni layer. The first connection electrode 10a made of Pb-free solder is mounted on the interposer wiring substrate 3, which is composed of a printed circuit board (PCB) 45. The wiring layer 46 has a predetermined pattern on the top, bottom, and inside. The iso-wiring layers 46 are electrically connected together via a conductor 49 filled in the through hole 47. A conductive plating film 48 is formed on the inner peripheral surface of the through hole 47. The internal wiring layer 46 has a plurality of layers. The upper and lower wiring layers 46 of the printed circuit board 45 are provided with a plating film 50 at a portion where the electrodes are connected. This plated film 50 is composed of a lower plated film 50a and an upper plated film 50b formed on the lower plated film 50a. For example, the lower plating film 50a is composed of a Ni plating film, and the upper plating film 50b is composed of an Au plating film. The lower surface of the intermediary wiring board 3 printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is connected to the upper surface of the semiconductor wafer 2 via the first connection electrode 10a. That is, the first connection electrode 10a electrically connects the plated film 44 provided at the connection portion of the wiring 42 of the semiconductor wafer 2 and the plated film 50 provided at the connection portion of the wiring layer 46 provided below the interposer wiring substrate 3, electrically. Way together. At the same time, a wafer-shaped electronic component 4 is mounted on the intermediate wiring board 3. The wafer-shaped electronic component 4 has a structure having electrodes 4a at both ends, and each electrode 4a is Pb-free solder 55. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 200411902 A7 B7 V. Description of the invention ( 11) It is gas-connected to the plating film 50 on the connection portion of the wiring layer 46 provided on the intermediate wiring substrate 3. (Please read the precautions on the back before filling in this page.) The interposer wiring board 3 is smaller than the semiconductor wafer 2 and the end of the interposer wiring board 3 does not protrude from the end of the semiconductor wafer 2 to the outside. Therefore, the outer shape of the semiconductor wafer 2 directly becomes the outer shape of the semiconductor module 1. At the same time, the wiring of the interposer wiring substrate 3 and the external electrode terminals 7 below the semiconductor wafer 2 are electrically connected together by a short conductor 32 arranged on the semiconductor wafer 2 in a penetrating state (see FIG. 2), so the wiring Can be reduced in impedance. Since the semiconductor module 1 is, for example, the thickness of the semiconductor wafer 2 is 0.0 5 mm; the thickness of the interposer wiring substrate 3 is 0.4 mm; the thickness of the wafer-shaped electronic component 4 is 0.6 mm; The thickness of the connection electrode 10 is about 0.02 mm, and the height (thickness) of the sealing portion 5 is about 1.0 mm. Therefore, the height from the lower surface of the external electrode terminal 7 to the upper surface of the sealing portion 5 is about 1.1 mm, which is relatively thin. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Such a semiconductor module 1 is mounted on a mounting substrate 60 composed of a PCB substrate as shown in FIG. 7. The mounting substrate 60 has wiring layers 61 of a predetermined pattern on the top, bottom, and inside. At the same time, these wiring layers 61 are electrically connected via a conductor 64 filled in a through hole. The internal wiring layer 61 has a plurality of layers. The wiring layers 46 'on the upper and lower surfaces of the mounting substrate 60 are provided with a plated film at a portion where the electrodes are connected in order to improve the connection performance. That is, FIG. 8 is a schematic view showing a semiconductor wafer portion connected to the mounting substrate 60. As shown in FIG.塡 Fill the conductor 32 penetrating the through hole 30 of the semiconductor wafer 2 above and below. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 200411902 A7 B7. V. Description of the invention () (please Read the precautions on the back before filling in this page) Yes, the wiring layer 61 is electrically connected to the mounting substrate 60 via the external electrode terminal 7. A plating film 65 is provided on the surface of the wiring layer 61. The plated film 65 has a double-layered structure including a lower layer 65a and an upper layer 65b. For example, the lower layer 65a is a Ni layer, and the upper layer 65b is an Au layer. An external electrode terminal 7 made of Pb-free solder is mounted thereon. Next, a method of manufacturing the semiconductor module 1 according to the first embodiment will be described with reference to FIGS. 9 to 14 again. As shown in FIG. 9, the semiconductor module 1 is formed by forming elements on a wafer (S 101), forming deep holes (S 102), deep hole insulation treatment (S 103), and filling conductors in the deep holes (S 104), back honing (S 105), back insulation processing (S 106), wafer inspection (S 107), wafers for each process of forming the connection electrode (S 108), via an interposer wiring board (S 109) ), The process of reflow (S 1 10), is mounted on the wafer separately, after different processes, protruding electrodes (S 201) are formed on the wiring mother substrate, parts (S 202) are mounted on the wiring mother substrate, and reflow (S 203) Intermediate wiring substrate made by each process of cutting the wiring mother substrate (S204), and then passed through to form an insulating resin layer (S1 1 1) on the wafer and an electrode (S1 1) under the wafer 2). The test (S 113) is performed by dividing each process of the wafer (S 114). Printed by the Consumer Cooperatives of the 4th Bureau of the Ministry of Economic Affairs and Consumer Cooperatives Next, the manufacturing method of the semiconductor module 1 will be described with reference to FIGS. 10 to 13. When manufacturing the semiconductor module 1 of the first embodiment, a semiconductor mother substrate (wafer) and a wiring mother substrate are used. The semiconductor mother substrate (crystal wafer) is used in steps S101 to S114, and the wiring mother substrate is used in steps S201 to S204 in different processes. In the final process, the wiring mother substrate is cut vertically and horizontally along the edge of the product forming part. -16 · This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 200411902 A7 B7 — — V. Description of the invention () Formation A plurality of interposer wiring boards 3. This interposer wiring board 3 is mounted on the top surface of the wafer in the process of S109. At S 114 in the final process, the wafer is cut vertically and horizontally along the edge of the product forming part to form a plurality of semiconductor modules 1. On the wafer and the wiring mother substrate, a product forming portion formed of a rectangular area is arranged in a vertical and horizontal manner. The single product forming portion of the wafer is a square-shaped semiconductor wafer 2 shown in FIGS. 1 and 2, and the product forming portion of the wiring mother substrate is a square-shaped interposer wiring substrate 3 shown in FIGS. 1 and 2. . The product forming portion of the wiring mother substrate has a smaller square shape than the product forming portion of the wafer. Before explaining the processes of S 101 to S 114, the processes of S 201 to S 204 will be described with reference to Figs. 11 (a) to (c). The wiring mother substrate 70 is composed of a flat printed circuit board as shown in FIG. 11 (a) so that the product formation portions f of n rows and m columns can be arranged in an array. FIG. 11 shows the wiring mother board 70 in a four-row state for convenience of explanation. The structure of the printed circuit board of the product formation portion f is the structure of the interposer wiring board 3 described above. As shown in FIG. 11 (a), such a wiring mother substrate 70 is provided with a protruding electrode 71 for forming electronic components 4 on the wiring mother substrate 70. For example, the bump electrode 71 is formed by printing and heating (S 201). The protruding electrode 71 is, for example, a ball electrode without Pb solder. The protruding electrodes 71 are formed on the plating films 50 of the wiring layer 46 shown in FIG. 5, respectively. Ball electrodes can also be installed instead of printing. Next, as shown in Figure 11 (b), the paper size on the wiring mother substrate 70 applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page). Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-17- 200411902 Α7 Β7 V. Description of the invention () (Please read the precautions on the back before filling this page) Equipped with electronic parts 4 and fixed by reflow (S 202 , S 203). That is, as shown in FIG. 11 (b), the electrode 4a is superposed on the protruding electrode 71 of each product forming portion f, and the electronic component 4 is supplied, and then the protruding electrode 71 is temporarily heated by a certain temperature. The Pb-free solder 55 for the electronic component 4 is mounted on the wiring mother substrate 70 by melting (reflowing) (see FIG. 5). The mounted electronic component 4 is, for example, a passive component such as a chip resistor, a chip capacitor, or a chip inductor. Next, as shown in FIG. 11 (c), the wiring mother substrate 70 is cut vertically and horizontally. The cutting operation is to cut along the boundary line of the adjacent product forming portion f. Thereby, a plurality of interposer wiring substrates 3 are produced. Printed by the 8th Consumer Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs On the other hand, when manufacturing the semiconductor module 1, as shown in Fig. 10 (a), a semiconductor mother substrate (wafer) 75 is first prepared. The wafer 75 shown in FIG. 10 (a) is also provided with the product formation portions e arranged in a vertical and horizontal direction, and has L rows and M columns. FIG. 10 (a) is formed in eight rows for convenience of explanation. On the other hand, in each product forming portion e, an active element such as a transistor or a wiring for each electronic element, or even an insulating film 4 3 such as a final passivation film has been formed (S 101). The element forming portion is conveniently formed under the portion represented by the insulating film 9. The product formation portion e is a portion that becomes the semiconductor wafer 2. In fact, the wafer is a silicon single crystal substrate with a diameter of 6 inches and a thickness of 750 μm, for example. Next, as shown in FIG. 10 (b), a deep hole 76 is formed in a predetermined place in the product forming portion e by etching (S 102). The deep hole 76 corresponds to the external electrode terminal 7 shown in Fig. 3, for example. The deep hole 76 is a circular hole having a diameter of about 10 to 20 μm, and its depth is deeper than 100 μm. This is -18- This paper size applies the Chinese National Standard (CMS) A4 specification (210 × 297 mm) 200411902 A7 — B7 15 · ~-~-'V. Because the wafer is in the final stage by Honing removes the back surface so that it has a thickness of 100 μm, and at this time, it is necessary to make the above-mentioned deep hole into the through hole 30. Next, as shown in FIG. 11 (c), an insulating film 31 is formed on the inner peripheral surface of the deep hole 76 (S103). The insulating film 31 is made of, for example, a SiO2 film, and can be formed by, for example, covering the surface of the wafer 75 other than the deep hole 76 with a resist film and applying heat treatment. In order to achieve electrical insulation separation, the thickness of the insulating film 31 is, for example, about 1 μm. Figures 10 (c) to (f) show a part of the product forming portion e. Next, as shown in FIG. 10 (d), the filling conductor 32 is buried in the deep hole 76 (S 104). The conductor 32 is made of, for example, Cu. Next, as shown in FIG. 10 (e), the back surface of the wafer 75 is honed to remove a predetermined thickness (S 105). By this back-side honing, the thickness of the wafer 75 becomes about 100 μm, and the deep hole 76 becomes the through-hole 30. At the same time, the conductors 3 2 exist from the top to the bottom of the wafer 75. The back honing is to expose the conductor 32 under the wafer 75. Next, as shown in FIG. 10 (f), a back surface insulation process is performed (S 1 06), and an insulating film 8 is selectively formed on the back surface of the wafer 75. The insulator 8 is made of a SiO 2 film, and can be formed by forming a resist film on a portion where the insulating film is not formed, and performing heat treatment. In order to achieve electrical insulation separation, the thickness of the insulating film 8 is, for example, about 2 μm. The insulating film 8 can also be used. After the entire area under the wafer 75 is formed by an oxidation process, a predetermined place is removed by etching. Next, the electrical characteristics of each product forming section e are performed in the state of a wafer. The paper size is in accordance with Chinese National Standards (CNs) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page). · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs • 19- 200411902 A7 B7 V. Description of Invention (16) ^ Inspection (wafer inspection) (S 107). (Please read the precautions on the back before filling in this page.) Next, as shown in Figure 12 (a), the electrodes for connection are formed in the prescribed space above the wafer 75, that is, in the electrical connection with the interposer wiring board 3. 10 (S 108). This connection electrode 10 is a Pb-free solder and is a spherical electrode. The connection electrode 10 is formed into a hemispherical shape or a spherical shape by, for example, printing and heating. Ball electrodes can also be installed. When this connection electrode 10 is formed, a first connection electrode 10a is formed in the element formation region, and a second connection electrode 1013 is formed on a predetermined conductor 32 which is separated from the element formation region. These connection electrodes 10, that is, the first connection electrode 10a and the second connection electrode 10b, are used to electrically connect the semiconductor wafer 2 and the interposer wiring substrate 3. At the same time, there is a step difference between the part forming the area and the part leaving the part forming area. Therefore, the second connection electrode 10b is larger (higher) than the first connection electrode 10a. It is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. As shown in FIG. 12 (b), the above process will be used. As shown in FIG. 12 (a), the interposer wiring substrate 3 on which the electronic component 4 shown in FIG. 11 (c) is mounted, which is manufactured in S 201 to S 204, is positioned on each of the product formation portions e on the wafer 7 5 ( S 109), the connection electrode 10 is reflowed (S 11 〇), and as shown in FIG. 12 (b), the intermediate wiring substrate 3 is fixed (mounted) on the wafer 75 by the connection electrode 10, respectively. 〇
接著，如第13圖（a )所示，藉由例如轉移塑模方法 ，在晶圓7 5上面形成規定高度的絕緣樹脂層80，以覆蓋 搭載於晶圓75上面的中介配線基板3及電子零件4 ( S -20- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 200411902 A7 B7 經濟部智惡財產局員工消費合作社印奴 17五、發明説明（） 111)。 接著，如第13圖（b )所示，藉由例如印刷及加熱， 在晶圓75下面形成散熱墊6及外部電極端子7 ( S 112) 〇 接著，如第13圖（c)所示，縱橫切斷晶圓75。切 斷動作是在相鄰接的製品形成部e的境界爲之。藉此，製 成複數個半導體模組1。藉由此項切斷’晶圓75便變成 半導體晶片2。 第14圖是表示本實施形態1的變形例子。如果可靠 性沒有問題，則如第14圖所示，可以不在半導體晶片2 上面用密封部來加以覆蓋。此半導體模組1除了起因於密 封部的效果以外，具有與實施形態1的半導體模組1同樣 的效果。 第1 5圖是可以應用在本實施形態1的半導體模組的 高頻電力放大裝置的例子。此高頻電力放大裝置的電路架 構如第15圖所示。此高頻電力放大裝置是可以放大兩種 通信系統，放大各Μ信系統的放大系統是縱列連接3級電 晶體的3級架構。 亦即，一方的通信系統是，在輸入端子Pinl與輸出 端子Pout 1之間，順序連接初級電晶體Q 1、次級電晶體 Q2、並聯的最末級（輸出級）電晶體Q3、Q4的架構，各 電晶體的汲電極施加有電源電壓Vddl，各電晶體的閘電 極施加有從控制端子Vapc輸入的控制電壓的偏壓。 同時，另一方的通信系統是，在輸入端子Pin2與輸 (請先閱讀背面之注意事項再填寫本頁) 裝. 、\=口 線 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） -21 - 200411902 A7 B7 經濟部智慈財產局員工消費合作社印製 五、發明説明（18 ) 出端子Pout2之間，順序連接初級電晶體Q5、次級電晶 體Q6、並聯的最末級（輸出級）電晶體Q7、Q8的架構 ，各電晶體的汲電極施加有電源電壓I Vdd2，各電晶體的 閘電極施加有從控制端子Vapc輸入的控制電壓的偏壓。 控制端子Vapc連接在開關SW1，此開關SW1因切 換端子Vctl的切換信號而切換，控制端子Vapc的控制電 壓是用以放大由此開關SW1特定的通信系統。 電晶體Ql ' Q2、Q5、Q6是以單片方式形成在單一的 半導體晶片（晶片1 )，一方的通信系統的輸出級電晶體 的Q3、Q4是以單片方式形成在單一的半導體晶片（晶片 2 )，另一方的通信系統的輸出級電晶體的Q7、Q8是以 單片方式形成在單一的半導體晶片（晶片3)。 在兩通信系統，裝配有複數組以C表示的電容元件 (CP、CG、CB ):以R表示的電阻元件（RP、RG );以 L表示的電感器，構成匹配電路或偏壓電路。 本實施形態1是，例如，一方的通信系統是1710 〜1785 MHz 頻帶的 DCS (Digital Cellular System 1800)方 式，另一方的通信系統是880〜915 MHz頻帶的GSM ( Global System for Mobile Communication)方式。 裝配有發熱量大的輸出級電晶體的晶片丨是形成爲半 導體晶片2，而經由散熱墊6直接接觸於安裝基板，裝配 有發熱量較輸出級小很多的初級、次級電晶體的晶片2、 晶片3則搭載於中介配線基板3的上面。 本實施形態1的半導體模組1具有下述的效果。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -22- (請先閱讀背面之注意事項再填寫本頁) •裝· 訂 線 200411902 經濟部智慈財產局員工消費合作社印製 A7 B7 —~ — ' —五、發明説明（） (1 )因爲在下面有外部電極端子7的半導體晶片2 上面搭載中介配線基板3，在此中介配線基板3的上面搭 載晶片狀電子零件4，構成規定電路架構的的半導體模組 1，因此可以提高安裝密度，同時可以達成小型化。 (2 )同時，中介配線基板3是較半導體晶片2小， 並將中介配線基板3配置成中介配線基板3的端部不會從 半導體晶片2的端部突出，因此可以達成半導體模組1的 小型化。 (3 )半導體晶片2的下面設有散熱墊6，因此可以 將形成在半導體晶片2的電晶體等的主動元件所產生的熱 量迅速傳至安裝基板，散熱性提高，主動元件可以穩定動 作。例如，以本發明的半導體模組1形成高頻放大裝置時 ，在多級架構的放大級，將發熱量大的最後級（輸出級） 的電路形成在半導體晶片2，形成發熱量小的初級的電晶 體或控制用電晶體的半導體晶片搭載於中介配線基板3的 上面時，可以提供小型且散熱特性良好的高頻放大裝置。 (4 )因爲中介配線基板3的配線與半導體晶片2下 面的外部電極端子7，是以貫穿狀態配設在半導體晶片2 的短形導體32連接，因此，可以達成配線的低阻抗化， 可以提高半導體模組1的高頻特性。 (5 )因爲連接在外部電極端子7的導體32的一部分 ，其上面接觸在密封部5，因此，可以經由導體32及外 部電極端子7迅速將密封部5的熱量發散至半導體模組1 的外部，可使半導體模組1穩定動作。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -23- (請先閱讀背面之注意事項再填寫本頁) -裝· 、-** 線 200411902 A7 B7 經濟部智慧財產局員工消費合作社印製 20 -五、發明説明（） (實施形態2 ) 第1 6圖是表示本發明的其他實施形態（實施形態2 )的半導體模組的模式截面圖，第17圖是表示本實施形 態2的半導體模組的IPD的模式放大截面圖。 本實施形態2的半導體模組1是在實施形態1的半導 體模組1，於中介配線基板3的上面搭載IPD ( Integrated Passive Device :積體被動裝置）85者。IPD 85是如第17 圖所示，在由玻璃基板等構成的基板86的一主面，於規 定處所順序堆疊規定形狀的導體層87或介電體層88，在 同樣反覆堆疊的架構的絕緣層89內裝配電阻元件90、電 容元件91、電感元件92，使其成爲一個電路架構者，雖 在第1 7圖未圖示，但外部電極端子95是突出在上述絕緣 層89的表面。此IPD 85因爲能夠將多數被動元件裝配成 很小型，因此近年來被用得很多。如第16圖所示，IPD 85是經由外部電極端子95以電氣方式連接在中介配線基 板3的未圖示的電極。 習知的IPD的構造有：在配線基板上順序形成由導體 或介電體構成的薄膜，藉此形成各被動零件的構造；或在 半導體基板的主面形成規定圖案的擴散領域，同時，配設 絕緣層或配線等以形成各被動零件的構造。 本實施形態1的半導體模組1因爲是將裝配複數個被 動元件的小型的IPD 85搭載於中介配線基板3，因此可 以在中介配線基板3搭載更多的被動元件（被動零件）。 (請先閱讀背面之注意事項再填寫本頁) -裝- 、-卩 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） -24- 200411902 A7 B7 — —-- 五、發明説明（） 這在搭載的被動零件的數目有限時，半導體模組1的小型 化也是有可能。 (請先閱讀背面之注意事項再填寫本頁) (實施形態3) 第1 8圖是表示本發明的其他實施形態（實施形態3 )的半導體模組的模式截面圖，第19圖是表示本實施形 態3的半導體模組之設在零件搭載基板內的被動元件的模 式截面圖。 本實施形態3的半導體模組1具備，在實施形態1 的半導體模組1，於中介配線基板3的內部裝配有基板內 被動零件100的架構。本實施形態3的半導體模組1是如 第1 8圖所示，裝配有大小不相同的3個基板內被動零件 100 ° 經濟部智慧財產局B(工消費合作社印製 基板內被動零件100的架構如第19圖所示。基板內 被動零件100是在製造構成中介配線基板3的PCB基板 時，於規定處所順序堆疊規定形狀的導體層101或介電體 層102，裝配電阻元件103、電容元件104、電感元件105 ，而連接至PCB基板的配線者。因裝配的被動元件的數 目，基板內被動零件1 00的大小會不相同。本實施形態1 也同時裝配兩個薄形且小型的其他基板內被動零件1 00。 而，在本實施衫態3的半導體模組1，設在半導體晶 片2下面中央的散熱墊6是由複數個電極構成。此複數個 電極是在安裝半導體模組1時，在安裝基板上將其一體化 。藉此架構，可以緩和模組與安裝基板的應力。 -25- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 200411902 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（22 ) 本實施形態3的半導體模組1也是因在內部配設基板 內被動零件100，而得達成高積體度化、小型化。 (實施形態4) 第20圖是表示本發明的其他實施形態（實施形態4 )的半導體模組的模式截面圖。本實施形態4的半導體模 組1是不在實施形態3的半導體模組1配設成爲散熱墊6 的電極。此架構的半導體模組1在模組中央無電極，而由 於可以利用該部分，因而可收到增加模組安裝基板側的配 線自由度之效果。 以上，依據實施形態具體說明本發明人所完成的發明 ，但本發明並非限定如上述實施形態，當然可以在不脫離 其主旨的範圍內作各種變更。實施形態1的中介配線基板 3是PCB基板，但也可以用陶瓷基板等的配線基板形成。 而實施形態1的放大元件是使用MOSFET ( Metal Oxide Semiconductor Field Effect Transistor)，但也可以是包含 其他的矽或化合物半導體雙極系列電晶體。 茲簡單說明，可以由本案所揭示的發明中具代表性者 獲得的效果如下。 (1)可以藉由提高搭載零件之安裝密度，達成半導 體模組的小型化。 (2 )可以提供’能提高發熱量多的半導體晶片的散 熱性的半導體模組。 (請先閲讀背面之注意事項再填寫本頁) -裝·Next, as shown in FIG. 13 (a), an insulating resin layer 80 having a predetermined height is formed on the wafer 75 by a transfer molding method, for example, so as to cover the interposer wiring board 3 and the electronics mounted on the wafer 75. Part 4 (S -20- This paper size applies to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 200411902 A7 B7 Employees' Cooperatives of the Intellectual Property Office of the Ministry of Economic Affairs, Consumer Cooperatives, India, 17th, Invention Description (111)). Next, as shown in FIG. 13 (b), a heat dissipation pad 6 and an external electrode terminal 7 are formed under the wafer 75 by, for example, printing and heating (S 112). Then, as shown in FIG. 13 (c), The wafer 75 is cut vertically and horizontally. The cutting operation is performed in the realm of the adjacent product forming portion e. Thereby, a plurality of semiconductor modules 1 are manufactured. By this cutting, the wafer 75 becomes the semiconductor wafer 2. FIG. 14 shows a modified example of the first embodiment. If there is no problem in reliability, as shown in Fig. 14, the upper surface of the semiconductor wafer 2 may not be covered with a sealing portion. This semiconductor module 1 has the same effects as those of the semiconductor module 1 of the first embodiment except for the effects due to the sealing portion. Fig. 15 is an example of a high-frequency power amplifier device that can be applied to the semiconductor module of the first embodiment. The circuit structure of this high-frequency power amplifier is shown in FIG. This high-frequency power amplification device can amplify two communication systems, and the amplification system that amplifies each M signal system is a three-level structure in which three levels of transistors are connected in series. That is, in one communication system, a primary transistor Q1, a secondary transistor Q2, and a final-stage (output-stage) transistor Q3, Q4 connected in parallel are sequentially connected between the input terminal Pinl and the output terminal Pout 1. In the structure, a drain electrode of each transistor is applied with a power supply voltage Vddl, and a gate electrode of each transistor is applied with a bias voltage of a control voltage input from a control terminal Vapc. At the same time, the other party ’s communication system is to install the input terminal Pin2 and input (please read the precautions on the back before filling this page). 、 \ = 口 线 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -21-200411902 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Office of the Ministry of Economic Affairs 5. Description of the invention (18) Between the terminals Pout2, the primary transistor Q5, the secondary transistor Q6, and the parallel most The structure of the final stage (output stage) transistors Q7 and Q8, the drain electrode of each transistor is applied with the power supply voltage I Vdd2, and the gate electrode of each transistor is applied with the bias voltage of the control voltage input from the control terminal Vapc. The control terminal Vapc is connected to the switch SW1. This switch SW1 is switched by switching the switching signal of the terminal Vctl. The control voltage of the control terminal Vapc is used to amplify the communication system specified by the switch SW1. The transistors Ql 'Q2, Q5, and Q6 are formed on a single semiconductor wafer (wafer 1) in a monolithic manner. The output transistors Q3 and Q4 of one communication system are formed in a single wafer on a single semiconductor wafer ( Wafer 2), Q7 and Q8 of the output stage transistors of the other communication system are formed on a single semiconductor wafer (wafer 3) in a monolithic manner. In the two communication systems, a complex array of capacitive elements (CP, CG, CB) represented by C: a resistive element (RP, RG) represented by R; an inductor represented by L to form a matching circuit or a bias circuit . In the first embodiment, for example, one communication system is a DCS (Digital Cellular System 1800) system with a frequency band of 1710 to 1785 MHz, and the other communication system is a GSM (Global System for Mobile Communication) method with a frequency band of 880 to 915 MHz. A wafer equipped with an output-stage transistor with a large amount of heat is formed as a semiconductor wafer 2 and directly contacts the mounting substrate via a heat dissipation pad 6. The wafer 2 is equipped with a primary and secondary transistor that generates much less heat than the output stage The wafer 3 is mounted on the intermediate wiring substrate 3. The semiconductor module 1 of the first embodiment has the following effects. This paper size applies to China National Standard (CNS) A4 specification (210X 297 mm) -22- (Please read the precautions on the back before filling out this page) • Binding line 200411902 Printed by the Employee Consumer Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs Production A7 B7 — ~ — '— V. Description of the invention () (1) Because the semiconductor wafer 2 with external electrode terminals 7 is provided with an interposer wiring board 3 on top, and wafer-shaped electronic parts 4 are mounted on the interposer wiring board 3 The semiconductor module 1 constituting a predetermined circuit architecture can increase the mounting density and achieve miniaturization. (2) At the same time, the interposer wiring substrate 3 is smaller than the semiconductor wafer 2 and the interposer wiring substrate 3 is configured so that the end portion of the interposer wiring substrate 3 does not protrude from the end of the semiconductor wafer 2, so that the semiconductor module 1 can be achieved. miniaturization. (3) The heat sink pad 6 is provided on the lower surface of the semiconductor wafer 2, so that heat generated by an active element such as a transistor formed on the semiconductor wafer 2 can be quickly transferred to the mounting substrate, heat dissipation is improved, and the active element can operate stably. For example, when a high-frequency amplification device is formed by using the semiconductor module 1 of the present invention, a circuit with a final stage (output stage) having a large amount of heat generation is formed on the semiconductor wafer 2 in an amplification stage of a multi-stage structure to form a primary stage having a small amount of heat generation. When a semiconductor wafer of a transistor or a control transistor is mounted on the upper surface of the interposer wiring board 3, a high-frequency amplifier device having a small size and excellent heat dissipation characteristics can be provided. (4) Since the wiring of the interposer wiring substrate 3 is connected to the external electrode terminals 7 below the semiconductor wafer 2 in a short state, the short conductors 32 arranged on the semiconductor wafer 2 are connected, so that the impedance of the wiring can be reduced and the impedance can be improved. High-frequency characteristics of the semiconductor module 1. (5) Since a part of the conductor 32 connected to the external electrode terminal 7 is in contact with the sealing portion 5, the heat of the sealing portion 5 can be quickly dissipated to the outside of the semiconductor module 1 through the conductor 32 and the external electrode terminal 7. , Can make the semiconductor module 1 operate stably. This paper size applies to China National Standard (CNS) A4 specification (210X 297 mm) -23- (Please read the precautions on the back before filling this page) -Installation ·,-** Line 200411902 A7 B7 Intellectual Property Bureau, Ministry of Economic Affairs Printed by employee consumer cooperatives 20-5. Description of the invention () (Embodiment 2) FIG. 16 is a schematic cross-sectional view showing a semiconductor module according to another embodiment (Embodiment 2) of the present invention, and FIG. 17 is a diagram showing the present invention. A schematic enlarged cross-sectional view of the IPD of the semiconductor module according to the second embodiment. The semiconductor module 1 according to the second embodiment is a semiconductor module 1 according to the first embodiment, and an IPD (Integrated Passive Device) 85 is mounted on the intermediate wiring board 3. As shown in FIG. 17, the IPD 85 is a conductive layer 87 or a dielectric layer 88 having a predetermined shape sequentially stacked on a main surface of a substrate 86 made of a glass substrate or the like in a predetermined place, and an insulating layer of a similarly stacked structure. The resistive element 90, the capacitive element 91, and the inductive element 92 are assembled in 89 to make it a circuit architect. Although not shown in FIG. 17, the external electrode terminal 95 protrudes from the surface of the insulating layer 89. This IPD 85 has been used a lot in recent years because it can assemble most passive components into a small size. As shown in Fig. 16, the IPD 85 is an electrode (not shown) which is electrically connected to the interposer wiring board 3 via an external electrode terminal 95. The structure of a conventional IPD includes: sequentially forming a thin film made of a conductor or a dielectric on a wiring substrate, thereby forming a structure of each passive part; or forming a diffusion pattern in a predetermined pattern on a main surface of a semiconductor substrate, and simultaneously An insulating layer or wiring is provided to form the structure of each passive component. Since the semiconductor module 1 according to the first embodiment is a small-sized IPD 85 equipped with a plurality of passive elements mounted on the interposer wiring substrate 3, more passive components (passive components) can be mounted on the interposer wiring substrate 3. (Please read the precautions on the back before filling out this page) -Installation-, -The size of this paper is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) -24- 200411902 A7 B7 — —-V. Invention Explanation () This also makes it possible to reduce the size of the semiconductor module 1 when the number of passive components mounted is limited. (Please read the precautions on the back before filling in this page) (Embodiment 3) Figure 18 is a schematic cross-sectional view showing a semiconductor module according to another embodiment (Embodiment 3) of the present invention, and Figure 19 is a diagram showing this A schematic cross-sectional view of a passive element of a semiconductor module according to a third embodiment provided in a component mounting substrate. The semiconductor module 1 according to the third embodiment includes a structure in which the passive component 100 in the substrate is mounted inside the interposer wiring substrate 3 in the semiconductor module 1 according to the first embodiment. As shown in FIG. 18, the semiconductor module 1 of the third embodiment is equipped with passive components in three substrates of different sizes 100 °. The Intellectual Property Bureau B of the Ministry of Economic Affairs (industrial and consumer cooperatives printed passive components in substrate 100) The structure is shown in Fig. 19. When manufacturing a PCB substrate constituting the interposer wiring substrate 3, the passive component 100 in the substrate is sequentially stacked in a predetermined place with a conductive layer 101 or a dielectric layer 102 having a predetermined shape, and a resistance element 103 and a capacitor element are assembled. 104, the inductance element 105, and the wiring connected to the PCB substrate. Due to the number of assembled passive components, the size of the passive component 100 in the substrate will be different. This embodiment 1 also assembles two thin and small other Passive part 100 in the substrate. In the semiconductor module 1 of the third embodiment, the heat sink 6 provided at the center of the lower surface of the semiconductor wafer 2 is composed of a plurality of electrodes. The plurality of electrodes are mounted on the semiconductor module 1 It is integrated on the mounting substrate. With this structure, the stress of the module and the mounting substrate can be relaxed. -25- This paper size applies to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 200411902 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (22) The semiconductor module 1 of the third embodiment is also equipped with passive components 100 in the substrate, which has achieved a high accumulation. (Fourth Embodiment) FIG. 20 is a schematic cross-sectional view showing a semiconductor module according to another embodiment (Embodiment 4) of the present invention. The semiconductor module 1 according to the fourth embodiment is not an embodiment The semiconductor module 1 of 3 is provided as an electrode of the heat dissipation pad 6. The semiconductor module 1 of this structure has no electrode in the center of the module, and since this part can be used, it can receive increased wiring freedom on the module mounting substrate side. In the foregoing, the invention made by the present inventors has been specifically described based on the embodiment, but the invention is not limited to the embodiment described above, and of course, various changes can be made without departing from the gist thereof. The interposer wiring board 3 of the first embodiment It is a PCB substrate, but it may be formed using a wiring substrate such as a ceramic substrate. The amplifying element of the first embodiment uses a MOSFET (Metal Oxide Semiconductor Fi). eld Effect Transistor), but may also include other silicon or compound semiconductor bipolar series transistors. I will briefly explain that the effects that can be obtained by the representative of the inventions disclosed in this case are as follows. (1) It can be improved by The mounting density of the mounted components achieves miniaturization of semiconductor modules. (2) We can provide semiconductor modules that can improve the heat dissipation of semiconductor wafers with high heat generation. (Please read the precautions on the back before filling out this page)- Loading ·
、1T 線 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） -26- 200411902 A7 B7 23 -—- 五、發明説明（） 【產業上的可利用性】 (請先閱讀背面之注意事項再填寫本頁) 如以上所述’本發明的半導體模組的構造是，在裝配 發熱量大的主動元件的半導體晶片的上面，重疊連接中介 配線基板，且在中介配線基板上搭載由被動零件等構成的 電子零件。同時，在半導體晶片產生的熱量是經由設在半 導體晶片下面的散熱墊傳至安裝基板，因此，可以有效散 熱’使半導體模組的動作穩定。特別是，考慮散熱性，可 以採，複數個半導體晶片搭載於半導體晶片內或中介配線 基板上面的架構，作爲攜帶式電話機等的無線電裝置用的 局頻電力放大裝置最適合。 【圖式的簡單說明】 第1圖是本發明一實施形態（實施形態1 )的半導體 模組的平面圖。 第2圖是表示上述半導體模組的內部架構的模式截面 圖。 第3圖是上述半導體模組的底面圖。 第4圖是去除密封部的半導體模組的平面圖。 經濟部智慧財產局員工消費合作社印製 第5圖是表示上述半導體模組的中介配線基板與半導 體晶片的連接狀態，及中介配線基板上的晶片狀電子零件 之搭載狀態的模式截面圖。 第6圖是表示形成在上述半導體模組的半導體晶片之 電晶體部分模式截面圖。 第7圖是表示將上述半導體模組安裝在安裝基板之狀 -27- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 200411902 A7 B7 24 -- 五、發明説明（） 態的一部分模式截面圖。 第8圖是表示上述半導體模組的安裝部分之一部分的 模式截面圖。 第9圖是表示本實施形態1的半導體模組之製造方法 的流程圖。 第10圖是對應流程圖的S 101〜S 106的晶圓的模式 截面圖。 第11圖是表示對應流程圖的S 201〜S 204，搭載零件 的中介配線基板之製造方法的模式截面圖。 第1 2圖是表示對應流程圖的s 1 0 8〜S 11 0，將搭載零 件的中介配線基板搭載於半導體晶片上之狀態的模式截面 圖。 第13圖是表示對應流程圖的S 111〜S 114，製造由密 封部被覆的半導體模組之狀態的模式截面圖。 第14圖是表示本實施形態1的變形例子之半導體模 組的模式截面圖。 第1 5圖是可以應用在本實施形態1的半導體模組之 (請先閱讀背面之注意事項再填寫本頁) -裝· I訂 線 經濟部智慧財產局員工消費合作社印製 態 形 施 實 他 其 c 的圖 明面 發截 。本式 圖示模 路表的 電是組 的圖模 器 6 體 大1導 放第半 頻的 2 態 形 施 的 D P 1 之 組 模 導 半 的 2 態 形 施 實 本 示 表 是 圖。 圖 面 第截 式 模 3 態 形 施 實 /^- 態 形 施 實 他 其 c 的圖 明面 發截 本式 示模 表的 是組 圖模 8 體 1導 第半 的 -28 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公缝） 200411902 A7 B7 - oc 一 --—-—— 五、發明説明（） 第1 9圖是表示本實施形態3的半導體模組之設在零 件搭載基板內的被動元件的模式截面圖。 ο 2 他 其 。 的圖 明面 發截 本式 示模 表的 是組 圖模 澧 導 第半 的 4 態 形 施 實 /ίν 態 形 施 明 說 號 圖 板 組片基 模晶線件 體體配零 導導介子 半半中電 極 子 端 極 部墊電 封熱部 密散外 · ♦ _·· 5 6 7 (請先閱讀背面之注意事項再填寫本頁) -裝· 、11 經濟部智慧財產局®χ消費合作社印製 2 6 7 9 域 極板 膜 領 膜電基 緣 域域移 緣用體層膜絕域領領偏 絕接導延化間領極極極 : 連半外氧層井源汲汲 線 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 200411902 A7 B7 五、發明説明（26 ) 20 :汲電極 21 :源電極 22 :閘電極 25 : P型領域 26 :接點領域 30 :貫穿孔 31 :絕緣膜 32 :導體 42 :配線 44 :電鍍膜 46 :配線層 47 :通孔 4 8 :電鍍膜 49 :導體 5 0 :電鍍膜 55 :無Pb焊錫 60 :安裝基板 61 :配線層 64 :導體 70 :配線母基板 7 1 :突起電極 75 :晶圓 76 :深孔 80 :絕緣樹脂層 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -30 - (請先閱讀背面之注意事項再填寫本頁)1. The paper size of the 1T line is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) -26- 200411902 A7 B7 23 ------ 5. Description of the invention () [Industrial availability] (Please read the back first Please note this page and fill in this page again.) As mentioned above, the structure of the semiconductor module of the present invention is such that an interposer wiring substrate is superimposed on the semiconductor wafer on which an active element with a large heat generation is mounted, and is mounted on the interposer wiring substrate. Electronic parts composed of passive parts, etc. At the same time, the heat generated in the semiconductor wafer is transferred to the mounting substrate via a heat sink provided under the semiconductor wafer, so that the heat can be efficiently dissipated to stabilize the operation of the semiconductor module. In particular, a structure in which a plurality of semiconductor wafers are mounted in a semiconductor wafer or on an interposer substrate can be adopted in consideration of heat dissipation properties, and is most suitable as a local-frequency power amplifier device for a radio device such as a portable telephone. [Brief description of the drawings] Fig. 1 is a plan view of a semiconductor module according to an embodiment (Embodiment 1) of the present invention. Fig. 2 is a schematic cross-sectional view showing the internal structure of the semiconductor module. FIG. 3 is a bottom view of the semiconductor module. FIG. 4 is a plan view of the semiconductor module with the sealing portion removed. Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 5 is a schematic cross-sectional view showing the connection state between the interposer wiring substrate of the semiconductor module and the semiconductor wafer, and the mounting state of wafer-shaped electronic components on the interposer wiring substrate. Fig. 6 is a schematic cross-sectional view showing a transistor portion of a semiconductor wafer formed on the semiconductor module. Figure 7 shows the state where the above-mentioned semiconductor module is mounted on a mounting substrate. -27- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 200411902 A7 B7 24-V. Description of the invention Partial pattern cross-sectional view. Fig. 8 is a schematic sectional view showing a part of a mounting portion of the semiconductor module. Fig. 9 is a flowchart showing a method for manufacturing a semiconductor module according to the first embodiment. FIG. 10 is a schematic cross-sectional view of a wafer corresponding to S 101 to S 106 of the flowchart. Fig. 11 is a schematic cross-sectional view showing a manufacturing method of an interposer wiring board in which components are mounted in accordance with S201 to S204 of the flowchart. Fig. 12 is a schematic cross-sectional view showing a state in which a component-equipped interposer wiring board is mounted on a semiconductor wafer corresponding to s 108 to S 110 in the flowchart. Fig. 13 is a schematic cross-sectional view showing a state in which a semiconductor module covered with a sealing portion is manufactured in accordance with S111 to S114 of the flowchart. Fig. 14 is a schematic cross-sectional view showing a semiconductor module according to a modification example of the first embodiment. Figure 15 shows the semiconductor module that can be applied to the first embodiment (please read the precautions on the back before filling out this page). The figure of his c is cut out. This formula shows the electrical model of the model table. The 6-body large 1-conductor has a half-frequency 2-state configuration of the D P 1 group. The 2-mode implementation of the group-mode semi-conductor is shown. The first section of the drawing mode 3 state implementation / ^-The state of the state implementation of the other c's diagram This side mode is shown in the group diagram mode 8 body 1 guide half -28 This paper size applies China National Standard (CNS) A4 specification (210X 297 cm) 200411902 A7 B7-oc One ----------- 5. Description of the invention () Figure 19 shows the components of the semiconductor module in this third embodiment. A schematic cross-sectional view of a passive element in a mounting substrate. ο 2 others. The cut-out model shown in the figure shows the 4th form of the first half of the group diagram mode / ίν state of the state Mingming diagram board assembly base crystal wire body body with zero guide meson half Middle electrode pads, pads, electrical seals, and heat seals are scattered outside. ♦ _ ·· 5 6 7 (Please read the precautions on the back before filling out this page) -Installed · 11 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs® χ Consumer Cooperative System 2 6 7 9 Domain plate membrane collar film Electric base edge Domain membrane transfer domain body membrane domain collar partial insulation extended extension poles Polar pole: even semi-outer oxygen layer well source drain line This paper is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 200411902 A7 B7 V. Description of the invention (26) 20: Drain electrode 21: Source electrode 22: Gate electrode 25: P type Field 26: Contact field 30: Through hole 31: Insulation film 32: Conductor 42: Wiring 44: Plating film 46: Wiring layer 47: Through hole 4 8: Plating film 49: Conductor 50 0: Plating film 55: Pb-free solder 60: mounting substrate 61: wiring layer 64: conductor 70: wiring mother substrate 7 1: protruding electrode 75: crystal Circle 76: Deep hole 80: Insulating resin layer The paper size is applicable to Chinese National Standard (CNS) A4 (210X 297 mm) -30-(Please read the precautions on the back before filling this page)
200411902 A7 B7200411902 A7 B7
五、發明説明（ 85 ·· IPD 27 6 7 8 9 0 1 8 8 8 8 9 9 2 9 層 件件件 層體層元元元 板體電緣阻容感 基導介絕電電電 ο ο 件 零 被 層 內層體 板體電 基導介 (請先閱讀背面之注意事項再填寫本頁) -裝· 4 ο 件件件 元元元 阻容感 電電電 I訂 經濟部智慧財產局員工消费合作社印製 本紙張尺度適用中國國家標隼（CNS ) A4規格（210 X 297公釐） -31 -V. Description of the invention (85 ·· IPD 27 6 7 8 9 0 1 8 8 8 9 9 2 9 The inner layer of the inner layer of the electric body of the body (please read the precautions on the back before filling in this page)-4 · ο Pieces of Yuan Yuan Yuan Capacitive Electricity Electricity I Order Printed by the Ministry of Economic Affairs Intellectual Property Bureau Employee Consumption Cooperative The paper size of the paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) -31-