TW201604965A - Semiconductor component and high frequency amplifier module - Google Patents

Abstract

According to the present invention, the thermal resistance can be reduced. The semiconductor device includes a substrate having a first surface and a second surface facing the first surface, a compound semiconductor transistor formed on the first surface of the substrate, and a ground portion laminated on the compound semiconductor transistor. The electrode layer is electrically connected to the emitter layer of the compound semiconductor transistor; and the insulating film is provided between the first surface of the substrate and the ground portion.

Description

Semiconductor component and high frequency amplifier module

The present invention relates to a semiconductor component and a high frequency amplifier module.

Patent Document 1 discloses a semiconductor element in which a bump is formed directly above the emitter of a compound semiconductor transistor, and by connecting the bump to a circuit board, the thermal resistance of the compound semiconductor transistor is lowered.

Patent Document 1: Japanese Laid-Open Patent Publication No. 2004-95714

However, in the configuration described in Patent Document 1, since the bump is not easily thinned, the distance between the transistor as the heat generating portion and the circuit substrate serving as the heat dissipation path becomes long, and the thermal resistance is less likely to be sufficiently lowered.

One of the objects of the present invention is to reduce the thermal resistance.

A semiconductor device according to one aspect of the present invention includes: a substrate having a first surface and a second surface facing the first surface; a compound semiconductor transistor formed on the first surface of the substrate; and a ground portion laminated on the compound semiconductor The upper side of the transistor is electrically connected to the emitter layer of the compound semiconductor transistor; and the insulating film is provided between the first surface of the substrate and the ground portion.

According to the present invention, the thermal resistance can be lowered.

10,60,70‧‧‧High frequency amplifier module

12‧‧‧Module substrate

14‧‧‧Semiconductor components

18A, 18B, 18C, 18D, 18E‧‧‧ wire bond pads (electrodes)

21‧‧‧ Conductive adhesive (connection)

22‧‧‧Compound semiconductor substrate (substrate)

22A‧‧‧The main face of one party (one side)

22B‧‧‧The other side of the other side (the other side)

24‧‧‧through hole electrode

26,80‧‧‧Compound semiconductor transistor

28‧‧‧ Collector layer (collective)

29‧‧‧base layer (base)

30‧‧ ‧ emitter layer (emitter)

31,90‧‧‧ Collector electrode

44‧‧‧Layer 3 wiring (grounding)

50‧‧‧Inductors

54‧‧‧Insulation film

Fig. 1A is a plan view showing a high frequency amplifier module according to a first embodiment of the present invention.

Figure 1B is a cross-sectional view taken along line A-A of Figure 1A.

Figure 1C is a cross-sectional view taken along line B-B of Figure 1B.

Fig. 2 is a cross-sectional view showing a high frequency amplifier module according to a second embodiment of the present invention.

Fig. 3 is a plan view showing a high frequency amplifier module according to a third embodiment of the present invention.

Fig. 4 is a cross-sectional view showing the HBT assembled to the high frequency amplifier module shown in Fig. 1 in place of the HBT of the first embodiment.

Fig. 5 is a view showing an example of the relationship between the thermal resistance and the parasitic capacitance with respect to the thickness of the insulating film in the first embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the embodiments described below are merely illustrative, and are not intended to exclude various modifications or technical applications that are not explicitly described below. That is, the present invention can be implemented in various modifications (combination of the respective embodiments, etc.) without departing from the spirit and scope of the invention. In the following description, the same or similar components are denoted by the same or similar reference numerals. The drawings are shown in schematic form and are not necessarily consistent with actual dimensions or ratios. There will also be situations in which the drawings contain parts that differ in size or ratio from each other.

(First embodiment)

Fig. 1A is a plan view of a high frequency amplifier module 10 according to a first embodiment of the present invention. Figure 1B is a cross-sectional view taken along line A-A of Figure 1A. Figure 1C is a cross-sectional view taken along line B-B of Figure 1B.

As shown in FIG. 1A and FIG. 1B, the high frequency amplifier module 10 of the first embodiment includes a module substrate 12 and a semiconductor element 14.

As shown in FIG. 1B, the module substrate 12 is, for example, a substrate having a laminated structure. Module The shape of the substrate 12 is, for example, a rectangular flat plate shape. In the configuration shown in FIG. 1B, the main surface of one of the thickness directions of the module substrate 12 is the surface 12A, and the other main surface of the thickness direction is the back surface 12B.

A rear terminal (not shown) is provided on the back surface 12B of the module substrate 12. Further, one or a plurality of surface mount members 16 that are electrically connected to the rear terminals are provided on the surface 12A of the module substrate 12. The surface mount component 16 includes, for example, a high frequency amplification active portion. Further, a member that is electrically connected to the rear terminal may be provided inside the substrate.

As shown in FIG. 1A, wire bonding pads 18A, 18B, 18C, 18D, 18E and 18F electrically connected to the surface mount component 16 and the like are formed on the surface 12A of the module substrate 12.

The shape of the wire bonding pad 18A is, for example, a rectangle. The lead bonding pad 18A extends along the periphery of the semiconductor element 14 around the one side of the semiconductor element 14 to be described later. The shapes of the other wire bonding pads 18B, 18C, 18D, 18E, and 18F are, for example, shorter than the wire bonding pads 18A. These wire bonding pads 18B, 18C, 18D, 18E, and 18F are provided along the periphery of the semiconductor element 14 around the other side, for example, around the semiconductor element 14.

A die pad 20 as a ground plane is provided on the surface 12A of the module substrate 12. The die pad 20 is electrically connected to any of the back terminals through a through hole or a wiring (not shown) in the module substrate 12, and is grounded through the back terminal. The die pad 20 is disposed between the wire bond pads 18A and the wire bond pads 18B, 18C, 18D, 18E and 18F. The shape of the die pad 20 is, for example, a rectangular plate shape elongated from the wire bond pad 18A toward the other wire bond pads 18B, 18C, 18D, 18E and 18F.

A semiconductor element 14 is provided on a surface of the die pad 20 opposite to the module substrate 12.

As shown in FIG. 1B, the semiconductor element 14 is die-bonded in a face-down manner. On the module substrate 12. Here, the face down means that the element forming surface of the semiconductor substrate is disposed opposite to the die pad of the module substrate. More specifically, the semiconductor element 14 is transmitted through the conductive adhesive 21 to the surface of the die pad 20. Thereby, the die pad 20 of the module substrate 12 is electrically connected to the third wiring layer 44 of the semiconductor element 14 to be described later.

The shape of the semiconductor element 14 is a rectangular flat plate shape in which the longitudinal direction L of the die pad 20 is long. This semiconductor element 14 has a substrate, for example, a compound semiconductor substrate 22.

The shape of the compound semiconductor substrate 22 is a rectangular flat plate shape in which the longitudinal direction L of the die pad 20 is long. The material of the compound semiconductor substrate 22 is not particularly limited, and examples thereof include materials having a crystal structure. Examples of the material having a crystal structure include GaAs, Si, InP, SiC, GaN, and the like. In addition, among these, it is preferable to contain GaAs or Si which is lower in price than InP and which is easy to have a large diameter as a main component. In addition, the "main component" means that the ratio of the material which is a main component of a certain substrate or a certain layer as a whole is 80% by mass or more.

The compound semiconductor substrate 22 has one main surface 22A (first surface) facing the die pad 20 and the other main surface 22B (second surface) facing the outer side. Further, the compound semiconductor substrate 22 is formed with a plurality of via electrodes 24 penetrating from one main surface 22A to the other main surface 22B.

As shown in FIG. 1B and FIG. 1C, a guard ring 25 is provided on the periphery of the principal surface 22A of one of the compound semiconductor substrates 22 in order to ensure moisture resistance reliability. The guard ring 25 is, for example, a semiconductor conductive layer.

Further, as shown in FIG. 1B, a compound semiconductor transistor 26 surrounded by a guard ring 25 is provided on one of the principal faces 22A. The compound semiconductor transistor 26 is, for example, a Heterojunction Bipolar Transistor (HBT) or a Field Effect Transistor (FET: Field). Effcet Transistor), a BiFET containing both of the same wafer. In the first embodiment, the compound semiconductor transistor 26 is an HBT.

Similarly to the compound semiconductor substrate 22, the HBT 26 has a subcollector layer 27, a collector layer 28, a base layer 29, and an emitter layer 30 each having a compound semiconductor as a constituent material.

A collector electrode 31 is provided on the sub-collector layer 27. Further, a wiring 32 is connected to the collector electrode 31. The wiring 32 is connected to, for example, one end of the via electrode 24. The other end of the via electrode 24 is connected to the collector terminal 34, whereby the collector layer 28 is electrically connected to the collector terminal 34. The set terminal 34 is disposed on the other main surface 22B so as to overlap the heat generating region, that is, the HBT 26, when partially viewed (in a plan view) from the other main surface 22B. That is, the collector terminal 34, which is formed directly above the HBT 26 in FIG. 1B. Further, the collector terminal 34 has, for example, a larger dimension in the longitudinal direction L than the HBT 26. Further, the collector terminal 34 is connected to the wire bonding pad 18A via the lead 36.

A base electrode 33 is provided on the base layer 29. The base electrode 33 is connected to a bias circuit or the like, for example, in the main surface 22A. Further, the base electrode 33 is led out to the other main surface 22B via the matching circuit or the like, and is connected to a signal input terminal (not shown).

The emitter layer 30 is connected to the emitter electrode 38 formed directly under the die pad 20 side. The emitter electrode 38 is connected to the first layer wiring 40 formed directly underneath (the die pad 20 side).

The first layer wiring 40 is connected to the second layer wiring 42 formed directly under the die pad 20 side. The second layer wiring 42 is connected to the third layer wiring 44 formed directly under the die pad 20 side. Thereby, the third layer wiring 44 is electrically connected to the emitter layer 30 through the second layer wiring 42 , the first layer wiring 40 , and the emitter electrode 38 .

As shown in FIG. 1C, the third layer wiring 44, when seen from the side of the die pad 20, A rectangular shape in which the longitudinal direction L of the die pad 20 is long is formed so as to completely cover the inner side of the guard ring 25.

Further, as shown in FIG. 1B, the third layer wiring 44 is connected to the surface of the die pad 20 through which the conductive adhesive 21 is grounded to be grounded. Therefore, the third layer wiring 44 has a function as a ground portion (ground).

In addition to the HBT 26, for example, a capacitor 46 is provided on one main surface 22A of the compound semiconductor substrate 22. A third layer wiring 44 is connected to one end of the capacitor 46. One end of the resistor 48 is connected to the other end of the capacitor 46.

This resistor 48 is provided on one of the main faces 22A. The other end of the resistor 48 is connected to one end of a via electrode 24. At one end of the one via electrode 24, one end of the inductor 50 is connected. The inductor 50 is formed on the other main surface 22B. Thereby, the capacitor 46 and the resistor 48 on the side of the element arrangement surface (one main surface 22A) and the inductor 50 on the side of the back surface (the other main surface 22B) are electrically connected through the via electrode 24. As shown in FIG. 1A, the other end of the inductor 50 is connected to the wire bond pad 18B via a lead 36.

Further, various elements (not shown) are provided on one main surface 22A of the compound semiconductor substrate 22, and are connected to, for example, various patterns 52 through the via electrodes 24. Various patterns 52 are formed on the other main surface 22B. As shown in FIG. 1A, various patterns 52 are connected via lead wires 36 to any of wire bond pads 18C, 18D, 18E and 18F.

Further, an insulating film 54 is provided in a space between the main surface 22A of the compound semiconductor substrate 22 and the third wiring layer 44.

The insulating film 54 is not particularly limited, but may be, for example, an epoxy film, a nitride film, or a polyimide film. The insulating film 54 may also have a laminated structure of an inorganic film and an organic film. For example, the first real In the embodiment, the insulating film 54 has a laminated structure of a nitride film and a polyimide film. The thickness of the insulating film 54 is not particularly limited, but generally it can be formed to be thinner than the bumps. The thickness of the insulating film 54 can be freely set to, for example, 1 μm to 50 μm by a general manufacturing method. Further, the thickness of the insulating film 54 is preferably less than 36 μm from the viewpoint of reliably lowering the thermal resistance in the case where the bump is used. Further, the thickness of the insulating film 54 is more preferably 1 μm or more and 10 μm or less. When the thickness of the insulating film 54 is 10 μm or less, the distance D between the second layer wiring 42 and the third layer wiring 44 can be shortened (see FIG. 1B), and the thermal resistance can be surely lowered, that is, the heat dissipation property can be surely improved. When the thickness of the insulating film 54 is 1 μm or more, for example, the parasitic capacitance of the third layer wiring 44 and the second layer wiring 42 can be reduced.

According to the semiconductor device 14 of the first embodiment of the present invention, the third layer wiring 44 which is laminated on the upper side of the HBT 26 and is electrically connected to the ground portion of the emitter of the HBT 26, and one of the compound semiconductor substrates 22 are provided. An insulating film 54 between the surface 22A and the third wiring layer 44.

According to this configuration, the insulating film 54 can be made thinner than the bump. When the insulating film 54 is thinned, the distance D between the second layer wiring 42 and the third layer wiring 44 can be shortened. Further, when the distance D is shortened, the HBT 26 as the heat generating portion approaches the module substrate 12 serving as the heat dissipation path, and the thermal resistance can be lowered.

Further, if a bump is formed directly above the emitter of the compound semiconductor transistor, the energization lifetime is shortened by the influence of the stress, and therefore it is considered that the bump must be shifted to the position directly above the non-emitter. When the bump is shifted to the position directly above the non-electrode, the distance between the transistor as the heat generating portion and the circuit substrate serving as the heat dissipation path is changed long, and it is considered that it is difficult to sufficiently reduce the thermal resistance. On the other hand, in the semiconductor device 14 of the first embodiment, since the third layer wiring 44 is formed by the emitter electrode 38 or the like directly under the emitter layer 30, the distance is shortened, and the thermal resistance can be further reduced.

Further, if the thermal resistance can be further lowered (if the heat dissipation property is improved), the resistance to thermal damage can be expected to be improved.

Further, the semiconductor element 14 according to the first embodiment can be connected to the ground portion (the third layer wiring 44) from any place by grounding the third layer wiring 44 without grounding the ground wiring. Further, in the bumps, it is not easy to shorten the interval between the bumps (120 μm to 150 μm), but it is not necessary to secure the above-described interval. Thereby, the wafer size can be reduced.

Further, in the related art, a connection of about 80 μm square or the like such as a via electrode or a bump is required for the connection to the ground. On the other hand, the semiconductor element 14 according to the first embodiment can be connected to the ground at a thickness of about 8 μm (that is, an area of about 1/100 as compared with a case of a member of about 80 μm square). Thereby, the wafer size can be reduced.

Further, by adjusting the size (heat dissipation area) of the emitter contact hole of the HBT 26, the temperature rise balance of each of the finger parts can be made uniform, and high performance can be expected.

Further, according to the semiconductor element 14 of the first embodiment, the collector terminal 34 is formed on the other principal surface 22B of the compound semiconductor substrate 22, and the through via electrode 24 is electrically connected to the collector layer 28 of the HBT 26. Therefore, it is not necessary to arrange a plurality of set terminals on the element arrangement surface (one main surface 22A), and the wafer size can be correspondingly reduced.

Further, the collector terminal 34 is formed on the other principal surface 22B of the compound semiconductor substrate 22 so as to overlap the HBT 26 in plan view. Therefore, the distance between the HBT 26 and the collector terminal 34 becomes close, and the heat of the HBT 26 is easily transmitted to the collector terminal 34 through the compound semiconductor substrate 22 and the via electrode 24. As a result, heat generated by the HBT 26 can be largely dissipated from the leads 36 electrically connected to the collector terminal 34 to the module substrate 12. Also, the wafer size can be reduced.

Further, in the semiconductor element 14 of the first embodiment, the inductor 50 is formed in another The main face of one party is 22B. Therefore, since the inductor 50 is separated from the third layer wiring 44 which is a ground portion formed on one main surface 22A side, the magnetic field can be suppressed from being interrupted by the third layer wiring 44, and the Q value can be improved. Further, in the element arrangement surface, the degree of freedom in the terminal pull-up position of the element placement surface, for example, the collector layer 28 can be increased in accordance with the amount of space in which the inductor 50 is not formed.

In addition, since the thickness of the insulating film 54 is 1 μm or more and 10 μm or less, for example, the third layer wiring 44 and the second layer wiring 42 can reduce, for example, the parasitic capacitance of the third layer wiring 44 and the second layer wiring 42 and can be surely Improve heat dissipation.

Further, the high-frequency amplifier module 10 of the first embodiment includes a module substrate 12, a die pad 20 which is a ground contact surface provided on the surface 12A of the module substrate 12, and a land portion and a third layer wiring 44. The semiconductor element 14 and the conductive adhesive 21 electrically connecting the die pad 20 and the third layer wiring 44 are provided.

According to this configuration, the heat of the HBT 26 can be transmitted to the module substrate 12 through the third layer wiring 44, the conductive adhesive 21, and the die pad 20, and the heat can be dissipated. Further, since the die pad 20 and the third layer wiring 44 are connected only by the conductive adhesive 21, the semiconductor element 14 and the module substrate 12 can be connected, and thus the two are connected to each other by bumps. The manufacturing steps of the high-frequency amplifier module 10 can be reduced, and the manufacturing becomes easy.

Further, since the collector terminal 34 is wire-bonded to the wire bonding pad 18A formed on the module substrate 12, heat generated by the HBT 26 can be dissipated from the lead 36 connected to the collector terminal 34 to the module substrate 12. Further, since the collector terminal 34 is formed on the other main surface 22B, the collector terminal 34 can be freely disposed on the one main surface 22A which is the element forming surface, and the lead wire 36 connected thereto can be drawn in any direction.

(Second embodiment)

Next, a high frequency amplifier module according to a second embodiment of the present invention will be described. In the first embodiment described above, the case where the module substrate 12 and the semiconductor element 14 are connected by the conductive adhesive 21 will be described. In the second embodiment, the point at which the module substrate 12 and the semiconductor element 14 are connected by solder is different from that of the first embodiment.

Fig. 2 is a cross-sectional view showing the high frequency amplifier module 60 of the second embodiment.

As shown in FIG. 2, in the high frequency amplifier module 60 of the second embodiment, the module substrate 12 and the semiconductor element 14 are connected by solder 62 instead of the conductive adhesive 21. Further, the high frequency amplifier module 60 does not include the guard ring 25 of the first embodiment. However, the high frequency amplifier module 60 may also be provided with a guard ring 25.

The configuration of the high frequency amplifier module 60 other than the above is the same as that of the first embodiment.

As described above, the high-frequency amplifier module 60 according to the second embodiment can achieve the same effects as those of the first embodiment, and the connection between the module substrate 12 and the semiconductor element 14 can be strengthened.

(Third embodiment)

Next, a high frequency amplifier module according to a third embodiment of the present invention will be described. In the first embodiment described above, the case where the semiconductor element 14 is provided with the inductor 50 will be described. In the third embodiment, the semiconductor element 14 is different from the first embodiment in that the inductor 50 is not provided.

Fig. 3 is a plan view showing the high frequency amplifier module 70 of the third embodiment.

As shown in FIG. 3, the high frequency amplifier module 70 of the third embodiment does not include the inductor 50 of the semiconductor element 14. Therefore, the high frequency amplifier module 70 does not have the wire bonding pad 18B electrically connected to the inductor 50 of the semiconductor element 14.

The configuration of the high-frequency amplifier module 70 other than the above is the same as that of the first embodiment.

As described above, the high-frequency amplifier module 70 according to the third embodiment can achieve the same effect as that of the first embodiment, and the wiring processing on the other main surface 22B becomes easier in accordance with the case where the inductor 50 is not provided. Can suppress manufacturing costs.

(Fourth embodiment)

Next, a high frequency amplifier module according to a fourth embodiment of the present invention will be described. In addition, the same components as those in the first embodiment are denoted by the same reference numerals, and their description is omitted.

4 is a cross-sectional view of the HBT 80 assembled to the high frequency amplifier module 10 shown in FIG. 1 in place of the HBT 26.

HBT80 is formed on the main surface 22A side of one of the compound semiconductor substrates 22. Similarly to the compound semiconductor substrate 22, the HBT 80 has a subcollector layer 27, a collector layer 28, a base layer 29, and an emitter layer 30 each having a compound semiconductor as a constituent material.

The surface of the sub-collector layer 27 on the side of the compound semiconductor substrate 22 is connected to the collector electrode 90. The collector layer 28 is electrically connected to the collector electrode 90 through the sub-collector layer 27. The collector electrode 90 is provided to penetrate the compound semiconductor substrate 22 in the thickness direction. The collector electrode 90 overlaps with the heat generating region, that is, the HBT 80 (particularly, the emitter layer 30) when partially seen (in a plan view) from the other main surface 22B. That is, the collector electrode 90 is formed on the collector layer 28 through the sub-collector layer 27. Further, the collector electrode 90 is electrically connected to a wire bonding pad (not shown) through a lead wire on the other main surface 22B side of the compound semiconductor substrate 22.

As described above, according to the high-frequency amplifier module of the fourth embodiment, the collector electrode 90 is formed on the other side of the compound semiconductor substrate 22 so as to overlap the HBT 80 in plan view. The main face of the party 22B. Therefore, in the same manner as in the first embodiment, heat generation of the HBT 80 can be largely radiated from the leads connected to the collector electrode 90 to the module substrate 12, and the wafer size can be reduced.

(Example)

Next, an embodiment of a high frequency amplifier module will be described.

In the embodiment, in the configuration of the high-frequency amplifier module 10 of the first embodiment, the relationship between the thickness (unit: μm) of the insulating film 54 and the thermal resistance θ jc (unit: ° C/W) is obtained by simulation. In addition, the simulation is implemented by the configuration of the high frequency amplifier module 10 of the first embodiment of the software of "ADS (Advanced Design System)" of Agilent Technology. Moreover, the relationship between the thickness (unit: μm) of the insulating film 54 and the parasitic capacitance (unit: pF/mm ² ) of the second layer wiring 42 and the third layer wiring 44 is calculated.

In addition, as a comparative example, as in the case of the configuration in which a bump is formed directly above the emitter of the compound semiconductor transistor and the bump is connected to the semiconductor element of the circuit board, the simulation is performed in the same manner as described above. Thermal resistance θ jc (unit: °C/W).

Fig. 5 is a view showing an example of the relationship between the thermal resistance and the parasitic capacitance with respect to the thickness of the insulating film in the first embodiment. Further, the four corners on the vertical axis (thermal resistance: θ jc) indicate a comparative example (thickness: 0 μm, thermal resistance: 48 ° C/W).

As shown in FIG. 5, in the comparative example, the thermal resistance was about 48 ° C / W. On the other hand, in the examples, it is understood that the thicker the insulating film 54 is, the thermal resistance increases in proportion. In order to lower the thermal resistance of the embodiment in comparison with the thermal resistance of the comparative example, it is understood that, for example, less than 36 μm is required in FIG. 5 . However, depending on the method of simulation, the value of 36 μm may vary. Therefore, the thickness of the insulating film 54 is not limited to less than 36 μm, and it is preferable that it is less than 36 μm.

Further, in the embodiment, if the thickness of the insulating film 54 is 10 μm or less, In the thermal resistance of the comparative example, the thermal resistance can be lowered by about 10 ° C / W or more, and the thickness of the insulating film 54 is preferably 10 μm or less.

Further, in the examples, it is understood that the thinner the thickness of the insulating film 54, the higher the parasitic capacitance. In particular, when the thickness of the insulating film 54 is less than 1 μm, the parasitic capacitance is rapidly increased as compared with 1 μm or more. On the other hand, when it is 1 μm or more, it is understood that the increase in the parasitic capacitance is slow. The thickness of the insulating film 54 is preferably 1 μm or more from the viewpoint of reducing the parasitic capacitance of the third layer wiring 44 and the second layer wiring 42.

(Modification)

The first to third embodiments are intended to facilitate the understanding of the present invention and are not intended to limit the present invention. Modifications/modifications may be made without departing from the spirit and scope of the invention, and the invention also includes equivalents thereof.

For example, a photoresist (not shown) may be provided around the die pad 20. Further, the guard ring 25 may be omitted.

10‧‧‧High frequency amplifier module

12‧‧‧Module substrate

12A‧‧‧ surface

12B‧‧‧Back

14‧‧‧Semiconductor components

16‧‧‧Surface construction parts

18A, 18E‧‧‧ wire bond pads (electrodes)

20‧‧‧ die pad

21‧‧‧ Conductive adhesive (connection)

22‧‧‧Compound semiconductor substrate (substrate)

22A‧‧‧The main face of one party (one side)

22B‧‧‧The other side of the other side (the other side)

24‧‧‧through hole electrode

25‧‧‧Protection ring

26‧‧‧Compound semiconductor transistor

27‧‧‧Subset

28‧‧‧ Collector layer (collective)

29‧‧‧base layer (base)

30‧‧ ‧ emitter layer (emitter)

31‧‧‧ Collector electrode

32‧‧‧Wiring

33‧‧‧ base electrode

34‧‧ ‧ extremes

36‧‧‧ lead

38‧‧ ‧ emitter electrode

40‧‧‧First layer wiring

42‧‧‧Second layer wiring

44‧‧‧Layer 3 wiring (grounding)

46‧‧‧ capacitor

48‧‧‧resistance

50‧‧‧Inductors

52‧‧‧ pattern

54‧‧‧Insulation film

Claims (9)

A semiconductor device comprising: a substrate having a first surface and a second surface facing the first surface; a compound semiconductor transistor formed on the first surface of the substrate; and a ground portion laminated on the compound semiconductor The upper side of the transistor is electrically connected to the emitter layer of the compound semiconductor transistor; and the insulating film is disposed between the first surface of the substrate and the ground portion. The semiconductor device according to claim 1, comprising: a via electrode interposed between the first surface penetrating the substrate and the second surface of the substrate; and a collector terminal formed on the second surface of the substrate The surface is electrically connected to the collector layer of the compound semiconductor transistor through the via electrode. The semiconductor device according to claim 2, wherein the collector terminal is formed on the second surface of the substrate so as to overlap the compound semiconductor transistor in a plan view. The semiconductor device according to any one of claims 1 to 3, further comprising an inductor formed on the second surface. The semiconductor element according to any one of claims 1 to 3, wherein the insulating film has a thickness of 36 μm or less. The semiconductor device according to any one of claims 1 to 3, wherein the insulating film has a thickness of 1 μm or more and 10 μm or less. The semiconductor device according to any one of claims 1 to 3, further comprising a guard ring provided on a periphery of the first surface of the substrate. A high frequency amplifier module having: The module substrate; the grounding surface is disposed on the surface of the module substrate; the semiconductor component according to any one of claims 1 to 7, wherein the grounding portion is disposed facing the ground; and the connecting portion is connected The ground and the grounding portion are electrically connected. The high frequency amplifier module of claim 8, wherein the collector terminal of the semiconductor component is bonded to an electrode lead formed on the module substrate.