TWI886795B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a first electrode, an isolation structure, a second electrode, an oxide semiconductor structure, a gate dielectric layer and a gate electrode. The isolation structure is located above the first electrode. The second electrode is located above the isolation structure. One of the first electrode and the second electrode includes an oxygen absorbing layer. The oxygen absorbing layer includes at least one of hafnium, titanium, beryllium, aluminum, manganese, chromium, vanadium, calcium, and silicon. The oxide semiconductor structure extends from the top surface of the second electrode to the top surface of the first electrode and contacts the side surface of the isolation structure. The oxide semiconductor structure includes a conductive region in contact with the oxygen absorbing layer and a channel region in contact with the isolation structure. The carrier concentration of the conductive region is greater than that of the channel region. The gate dielectric layer is located on the oxide semiconductor structure. The gate electrode is located on the gate dielectric layer.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a method for manufacturing the same.

With the rapid development of technology, the resolution of display devices has been increasing year by year. In order to manufacture higher resolution display devices, it is urgent to reduce the size of semiconductor components in the device, such as the size of thin film transistors. Generally, the structure of thin film transistors includes a gate, a semiconductor channel layer, a source, and a drain. Among them, the function of the gate is to control the carriers in the semiconductor channel layer, thereby determining whether the current can flow between the source and the drain.

In order to reduce the size of thin film transistors, the channel length and/or channel width of the semiconductor channel layer must be reduced. However, such size reduction also brings a series of challenges. Reducing the size of the semiconductor channel layer may lead to insufficient on current of the thin film transistor, or even fail to meet the external quantum efficiency (EQE) requirements of the light-emitting diode. Therefore, there is an urgent need for a method that can maintain or even increase the on current of semiconductor devices while reducing the size of semiconductor devices.

The present invention provides a semiconductor device and a manufacturing method thereof, which have the advantage of high driving current.

At least one embodiment of the present invention provides a semiconductor device, which includes a first electrode, an isolation structure, a second electrode, an oxide semiconductor structure, a gate dielectric layer and a gate. The isolation structure is located on the first electrode. The second electrode is located on the isolation structure. One of the first electrode and the second electrode includes an oxygen absorption layer. The oxygen absorption layer includes at least one of cobalt, titanium, curium, aluminum, manganese, chromium, vanadium, calcium and silicon. The oxide semiconductor structure extends from the top surface of the second electrode to the top surface of the first electrode and contacts the side surface of the isolation structure. The oxide semiconductor structure includes a conductive region contacting the oxygen absorption layer and a channel region contacting the isolation structure. The carrier concentration of the conductive region is greater than that of the channel region. The gate dielectric layer is located on the oxide semiconductor structure. The gate is located on the gate dielectric layer.

At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps. A stacked structure consisting of a first electrode, an isolation structure, and a second electrode is formed. One of the first electrode and the second electrode includes an oxygen absorption layer. The oxygen absorption layer includes at least one of cobalt, titanium, curium, aluminum, manganese, chromium, vanadium, calcium, and silicon. An oxide semiconductor structure is formed on the stacked structure. The oxide semiconductor structure includes a conductive region contacting the oxygen absorption layer and a channel region contacting the isolation structure. The oxygen element in the conductive region diffuses into the oxygen absorption layer, so that the carrier concentration of the conductive region is greater than the carrier concentration of the channel region. A gate dielectric layer is formed on the oxide semiconductor structure. A gate electrode is formed on the gate dielectric layer.

10A, 10B, 10C, 10D, 10E: Semiconductor devices

100:Substrate

102: Buffer layer

110: Isolation structure

110s: Side

120: Gate dielectric layer

210,210A,210B: first electrode

210t,220t: Top surface

220A, 220B, 220C, 220D, 220E: Second electrode

222: Oxygen absorption layer

224:Metal layer

230: Gate

300,300A,300B,300C,300D,300E: oxide semiconductor structure

302: Conductive area

304: Channel area

306: Contact area

310: Native metal oxides

E: Arrow

t1,t2,t3,t4: thickness

FIG1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Figures 2A to 2D are cross-sectional schematic diagrams of a method for manufacturing the semiconductor device of Figure 1.

FIG3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Figures 4A to 4D are cross-sectional schematic diagrams of a method for manufacturing the semiconductor device of Figure 3.

FIG5 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG7 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG8A is a schematic cross-sectional view of a simulation structure of a semiconductor device according to an embodiment of the present invention.

Figure 8B is a partial enlarged view of the virtual frame position in Figure 8A.

FIG. 9A is a data diagram of the electric field and Y-axis position of the semiconductor device of Examples 1 to 3.

FIG. 9B is a data diagram of gate voltage and current (Id) of semiconductor devices of Examples 1 to 3.

FIG. 10A is a data diagram of the electric field and Y-axis position of the semiconductor devices of Examples 4 to 6.

FIG. 10B is a data diagram of gate voltage and current (Id) of semiconductor devices of Examples 4 to 6.

FIG. 11A is a data diagram of the electric field and Y-axis position of the semiconductor devices of Examples 7 to 9.

Figures 11B and 11C are data graphs of gate voltage and current (Id) of semiconductor devices of Examples 7 to 9.

FIG1 is a cross-sectional schematic diagram of a semiconductor device 10A according to an embodiment of the present invention. Referring to FIG1 , the semiconductor device 10A includes a first electrode 210A, an isolation structure 110, a second electrode 220A, an oxide semiconductor structure 300A, a gate dielectric layer 120, and a gate 230.

In this embodiment, the first electrode 210A, the isolation structure 110, the second electrode 220A, the oxide semiconductor structure 300A, the gate dielectric layer 120 and the gate 230 are sequentially stacked on the substrate 100. By designing the stacked structure, the effective channel length of the oxide semiconductor structure 300A can be reduced, and the size of the semiconductor device 10A can be reduced.

The substrate 100 is, for example, a rigid substrate, and its material may be glass, quartz, organic polymer or opaque/reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable materials. However, the present invention is not limited thereto. In other embodiments, the substrate 100 may also be a flexible substrate or a stretchable substrate. For example, the materials of the flexible substrate and the stretchable substrate include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane PU or other suitable materials.

The buffer layer 102 is located on the substrate 100. The buffer layer 102 includes, for example, silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride or other suitable materials or a combination of the aforementioned materials or a stack of the aforementioned materials. In some embodiments, the buffer layer 102 is used as a hydrogen barrier layer and/or a metal ion barrier layer.

The first electrode 210A is located on the substrate 100. In this embodiment, a buffer layer 102 is included between the first electrode 210A and the substrate 100. In some embodiments, the thickness t1 of the first electrode 210A is 100 nm to 500 nm.

The isolation structure 110 is located on the first electrode 210A. The isolation structure 110 partially overlaps the first electrode 210A. Specifically, a portion of the top surface 210t of the first electrode 210A is covered by the isolation structure 110, while another portion of the top surface 210t is not covered by the isolation structure 110. In some embodiments, the thickness t2 of the isolation structure 110 is 30 nanometers to 600 nanometers.

In some embodiments, the material of the isolation structure 110 includes, for example, an organic insulating material, silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, einsteinium oxide, zirconium oxide or other suitable materials or a combination of the foregoing materials. In some embodiments, the material of the isolation structure 110 includes an oxide (e.g., silicon oxide) and can be used as an oxygen storage/oxygen replenishing layer, thereby adjusting the oxygen concentration in the oxide semiconductor structure 300A during the manufacturing process. In some embodiments, the isolation structure 110 may have a single-layer structure or a multi-layer structure. When the isolation structure 110 has a multi-layer structure, an oxide layer (e.g., a silicon oxide layer) and a nitride layer (e.g., a silicon nitride layer) can be used in combination to optimize the performance of the semiconductor device 10A. For example, an oxide layer can be used as an oxygen storage/replenishing layer, while a nitride layer can be used as a hydrogen barrier layer or a metal ion barrier layer.

The second electrode 220A is located on the isolation structure 110. The second electrode 220A covers the top surface of the isolation structure 110. In some embodiments, the side surface 110s of the isolation structure 110 is aligned with the side surface of the second electrode 220A. In some embodiments, the thickness t3 of the second electrode 220A is 100 nm to 500 nm.

The oxide semiconductor structure 300A extends from the top surface 220t of the second electrode 220A to the top surface 210t of the first electrode 210A and contacts the side surface 110s of the isolation structure 110. In some embodiments, the material of the oxide semiconductor structure 300A includes an oxide containing two or more of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W) (e.g., metal oxides such as indium gallium zinc tin oxide (IGZTO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO), indium gallium oxide (InGO), and indium tungsten oxide (InWO)) or a rare earth doped metal oxide (e.g., Ln-IZO) or other suitable metal oxides or a combination of the above materials. The oxide semiconductor structure 300A has a single-layer structure or a multi-layer structure. In some embodiments, the thickness t4 of the oxide semiconductor structure 300A on the side surface 110s is 10 nm to 100 nm.

The first electrode 210A and the second electrode 220A may each have a single-layer structure or a multi-layer structure. In the present embodiment, the first electrode 210A and the second electrode 220A each have a single-layer structure. One of the first electrode 210A and the second electrode 220A includes an oxygen absorbing layer, and the other includes an oxygen blocking layer. In the present embodiment, the first electrode 210A includes an oxygen blocking layer, and the second electrode 220A includes an oxygen absorbing layer. In some embodiments, the material of the oxygen blocking layer (i.e., the first electrode 210A) includes tin, copper, molybdenum, nickel, or other suitable conductive materials. In some embodiments, the material of the oxygen absorption layer (i.e., the second electrode 220A) includes at least one of cobalt, titanium, beryllium, aluminum, manganese, chromium, vanadium, calcium, and silicon.

In the present embodiment, the second electrode 220A is used as an oxygen absorption layer, and in the process of manufacturing the semiconductor device 10A, the oxygen element in the oxide semiconductor structure 300A diffuses into the second electrode 220A, and the second electrode 220A is oxidized to form a native metal oxide 310 located between the oxygen absorption layer (i.e., the second electrode 220A) and the oxide semiconductor structure 300A. The standard Gibbs free energy of formation of the native metal oxide 310 is lower than the standard Gibbs free energy of formation of the oxide semiconductor structure 300A, and therefore, it is beneficial for the oxygen element in the oxide semiconductor structure 300A to diffuse into the second electrode 220A. In some embodiments, the standard Gibbs free energy of formation of the material of the native metal oxide 310 is less than -1000 KJ mol ^-1 , such as -1000 KJ mol ^-1 to -2000 KJ mol ^-1 .

In this embodiment, the oxygen absorption layer (i.e., the second electrode 220A) can be used as a reducing agent to absorb part of the oxygen element in the oxide semiconductor structure 300A to form a conductive region 302 in the oxide semiconductor structure 300A that contacts the oxygen absorption layer (i.e., the second electrode 220A). The conductive region 302 has a lower oxygen concentration and a higher carrier concentration.

In the present embodiment, the first electrode 210A is used as an oxygen barrier layer, and during the process of manufacturing the semiconductor device 10A, the oxygen element in the oxide semiconductor structure 300A is not easily diffused into the oxygen barrier layer (i.e., the first electrode 210A). In some embodiments, a small amount of oxygen element still diffuses from the oxide semiconductor structure 300A into the oxygen barrier layer (i.e., the first electrode 210A), and forms a native metal oxide (not shown) between the oxide semiconductor structure 300A and the oxygen barrier layer. However, in the present embodiment, the native metal oxide between the oxide semiconductor structure 300A and the first electrode 210A is not easily formed (e.g., only a thinner or smaller native metal oxide is formed) compared to the native metal oxide 310 between the oxide semiconductor structure 300A and the second electrode 220A. In some embodiments, the standard Gibbs free energy of formation of the native metal oxide between the oxide semiconductor structure 300A and the first electrode 210A is higher than the standard Gibbs free energy of formation of the native metal oxide 310, or even higher than the standard Gibbs free energy of formation of the oxide semiconductor structure 300A. In some embodiments, the standard Gibbs free energy of formation of the native metal oxide between the oxide semiconductor structure 300A and the first electrode 210A is higher than -1000 KJ mol ^-1 , such as -300 KJ mol ^-1 to -1000 KJ mol ^-1 .

After forming the native metal oxide 310, the oxide semiconductor structure 300A includes a conductive region 302 (also referred to as an n+ doped region) contacting the oxygen absorption layer, a channel region 304 contacting the isolation structure 110, and a contact region 306 contacting the oxygen barrier layer. The channel region 304 is sandwiched between the conductive region 302 and the contact region 306. In some embodiments, the oxygen concentration of the conductive region 302 is lower than the oxygen concentration of the channel region 304, and the carrier concentration of the conductive region 302 (e.g., 5e18~1e22cm ^-3 ) is greater than the carrier concentration of the channel region 304 (e.g., 1e16~1e18cm ^-3 ). The resistivity of the conductive region 302 is lower than the resistivity of the channel region 304. In some embodiments, the oxygen concentration of the contact region 306 is lower than or equal to the oxygen concentration of the channel region 304, but the oxygen concentration of the contact region 306 is higher than the oxygen concentration of the conductive region 302. The carrier concentration of the contact region 306 (e.g., 1e16-1e19 cm ^-3 ) is greater than or equal to the carrier concentration of the channel region 304, but lower than the carrier concentration of the conductive region 302. In some embodiments, the carrier concentration of the contact region 306 is between the carrier concentration of the channel region 304 and the carrier concentration of the conductive region 302.

In this embodiment, the first electrode 210A is used as a drain, and the second electrode 220A is used as a source. By forming a conductive region 302 on the source, the carrier concentration of the oxide semiconductor structure 300A can be increased, thereby increasing the driving current of the semiconductor device 10A. In addition, by making the drain include an oxygen barrier layer, the conductive region 302 (also known as an n+ doped region) of the oxide semiconductor structure 300A at the position in contact with the drain can be avoided, thereby reducing the problem of hot carrier effect caused by the electric field.

The gate dielectric layer 120 is located on the oxide semiconductor structure 300A. In some embodiments, the material of the gate dielectric layer 120 includes silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, vanadium oxide, zirconium oxide or other suitable materials or a combination of the foregoing materials.

The gate 230 is located on the gate dielectric layer 120 and overlaps the oxide semiconductor structure 300A. In some embodiments, the material of the gate 230 includes metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, alloys of the above metals, oxides of the above metals, nitrides of the above metals, or combinations thereof or other conductive materials. The gate 230 may have a single-layer structure or a multi-layer structure.

2A to 2D are cross-sectional schematic diagrams of a method for manufacturing the semiconductor device 10A of FIG. 1. Referring to FIG. 2A, a buffer layer 102 is formed on a substrate 100. A stacked structure consisting of a first electrode 210A, an isolation structure 110, and a second electrode 220A is formed on the buffer layer 102. One of the first electrode 210A and the second electrode 220A includes an oxygen absorbing layer, and the other includes an oxygen blocking layer. In this embodiment, the second electrode 220A includes an oxygen absorbing layer, and the first electrode 210A includes an oxygen blocking layer.

Referring to FIG. 2B , an oxide semiconductor structure 300A is formed on the stacked structure. The oxide semiconductor structure 300A extends from the top surface 220t of the second electrode 220A to the top surface 210t of the first electrode 210A.

Referring to FIG. 2C , the oxygen element in the conductive region 302 of the oxide semiconductor structure 300A is diffused into the second electrode 220A to form a native metal oxide 310 on the second electrode 220A. The native metal oxide 310 is formed at the interface between the second electrode 220A and the oxide semiconductor structure 300A. While forming the native metal oxide 310, a conductive region 302 with a high oxygen vacancy concentration and a high carrier concentration is formed in the oxide semiconductor structure 300A. In some embodiments, the channel region 304 and the contact region 306 of the oxide semiconductor structure 300A contact the isolation structure 110 and the first electrode 210A, respectively, wherein the carrier concentration of the contact region 306 is greater than or equal to the carrier concentration of the channel region 304. The channel region 304 is located between the contact region 306 and the conductive region 302. In some embodiments, less native metal oxide is formed between the contact region 306 and the first electrode 210A or no native metal oxide is formed between the contact region 306 and the first electrode 210A.

In some embodiments, during the deposition of the oxide semiconductor structure 300A, the native metal oxide 310 and the conductive region 302 are spontaneously formed, but the present invention is not limited thereto. In other embodiments, additional heat treatment processes are performed to promote the diffusion of oxygen in the oxide semiconductor structure 300A into the second electrode 220A.

Referring to FIG. 2D , a gate dielectric layer 120 is formed on the oxide semiconductor structure 300A. In the present embodiment, before the gate dielectric layer 120 is formed, a native metal oxide 310 is formed between the oxide semiconductor structure 300A and the second electrode 220A, but the present invention is not limited thereto. In other embodiments, after the gate dielectric layer 120 is formed or during the process of forming the gate dielectric layer 120, oxygen in the oxide semiconductor structure 300A is diffused into the second electrode 220A to form the native metal oxide 310 and the conductive region 302.

In some embodiments, the material of the isolation structure 110 includes oxide (e.g., silicon oxide). In some embodiments, after forming the gate dielectric layer 120, an additional heat treatment process is performed to diffuse the oxygen element in the isolation structure 110 into the oxide semiconductor structure 300A (e.g., diffuse into the channel region 304), thereby reducing the oxygen vacancy concentration in the channel region 304, thereby increasing the resistivity of the channel region 304 and reducing the leakage problem between the first electrode 210A and the second electrode 220A.

Finally, please return to FIG. 1 to form a gate 230 on the gate dielectric layer 120. At this point, the semiconductor device 10A is substantially completed.

FIG3 is a schematic cross-sectional view of a semiconductor device 10B according to an embodiment of the present invention. It must be noted that the embodiment of FIG3 uses the component numbers and some contents of the embodiment of FIG1, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the semiconductor device 10B of FIG. 3 and the semiconductor device 10A of FIG. 1 is that in the semiconductor device 10B, the first electrode 210B includes an oxygen absorption layer, and the second electrode 220B includes an oxygen barrier layer. In some embodiments, the material of the first electrode 210B includes at least one of cobalt, titanium, curium, aluminum, manganese, chromium, vanadium, calcium, and silicon. In some embodiments, the material of the second electrode 220B includes tin, copper, molybdenum, nickel, or other suitable conductive materials.

In this embodiment, the first electrode 210B is used as a source, and the second electrode 220B is used as a drain. By forming a conductive region 302 on the source (i.e., the first electrode 210B), the resistivity of the oxide semiconductor structure 300B can be reduced, thereby increasing the driving current of the semiconductor device 10B. In addition, by making the drain (i.e., the second electrode 220B) include an oxygen barrier layer, the oxide semiconductor structure 300B can be prevented from generating a conductive region 302 (also known as an n+ doped region) at a position in contact with the drain, thereby reducing the generation of a hot carrier effect. In some embodiments, the conductive region 302 on the first electrode 210B contacts the isolation structure 110.

4A to 4D are cross-sectional schematic diagrams of a method for manufacturing the semiconductor device 10B of FIG. 3. Referring to FIG. 4A, a buffer layer 102 is formed on a substrate 100. A stacked structure consisting of a first electrode 210B, an isolation structure 110, and a second electrode 220B is formed on the buffer layer 102. One of the first electrode 210B and the second electrode 220B includes an oxygen absorbing layer, and the other includes an oxygen blocking layer. In this embodiment, the first electrode 210B includes an oxygen absorbing layer, and the second electrode 220B includes an oxygen blocking layer.

Referring to FIG. 4B , an oxide semiconductor structure 300B is formed on the stacked structure. The oxide semiconductor structure 300B extends from the top surface 220t of the second electrode 220B to the top surface 210t of the first electrode 210B.

Referring to FIG. 4C , the oxygen element in the conductive region 302 of the oxide semiconductor structure 300B is diffused into the first electrode 210B to form a native metal oxide 310 on the first electrode 210B. The native metal oxide 310 is formed at the interface between the first electrode 210B and the oxide semiconductor structure 300B. While forming the native metal oxide 310, a conductive region 302 with a higher carrier concentration is formed in the oxide semiconductor structure 300B. In some embodiments, the channel region 304 and the contact region 306 of the oxide semiconductor structure 300B contact the isolation structure 110 and the second electrode 220B, respectively, wherein the carrier concentration of the contact region 306 is greater than or equal to the carrier concentration of the channel region 304. The channel region 304 is located between the contact region 306 and the conductive region 302.

In some embodiments, during the process of depositing the oxide semiconductor structure 300B, the native metal oxide 310 and the conductive region 302 are spontaneously formed, but the present invention is not limited thereto. In other embodiments, additional heat treatment processes are performed to promote the diffusion of oxygen in the oxide semiconductor structure 300B into the first electrode 210B.

Referring to FIG. 4D , a gate dielectric layer 120 is formed on the oxide semiconductor structure 300B. In this embodiment, before forming the gate dielectric layer 120, a native metal oxide 310 has been formed between the oxide semiconductor structure 300B and the first electrode 210B, but the present invention is not limited thereto. In other embodiments, after forming the gate dielectric layer 120 or during the process of forming the gate dielectric layer 120, oxygen in the oxide semiconductor structure 300B is diffused into the first electrode 210B to form the native metal oxide 310 and the conductive region 302.

In some embodiments, the material of the isolation structure 110 includes oxide (e.g., silicon oxide). In some embodiments, after forming the gate dielectric layer 120, an additional heat treatment process is performed to diffuse the oxygen element in the isolation structure 110 into the oxide semiconductor structure 300B (e.g., diffuse into the channel region 304), thereby reducing the oxygen vacancy concentration in the channel region 304, thereby increasing the resistivity of the channel region 304 and reducing the leakage problem between the first electrode 210B and the second electrode 220B.

Finally, please return to FIG. 3 to form a gate 230 on the gate dielectric layer 120. At this point, the semiconductor device 10B is substantially completed.

FIG5 is a cross-sectional schematic diagram of a semiconductor device 10C according to an embodiment of the present invention. It must be noted that the embodiment of FIG5 uses the component numbers and some contents of the embodiment of FIG1, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the semiconductor device 10C of FIG. 5 and the semiconductor device 10A of FIG. 1 is that the second electrode 220C of the semiconductor device 10C has a multi-layer structure.

Referring to FIG. 5 , the second electrode 220C includes a metal layer 224 and an oxygen absorption layer 222. In the present embodiment, the oxygen absorption layer 222 covers the top surface of the metal layer 224. The oxide semiconductor structure 300C contacts the top surface and the side surface of the oxygen absorption layer 222. In the present embodiment, the metal layer 224 and the oxygen absorption layer 222 include different materials. For example, the material of the oxygen absorption layer 222 includes at least one of cobalt, titanium, beryllium, aluminum, manganese, chromium, vanadium, calcium and silicon, and the material of the metal layer 224 includes tin, copper, molybdenum, nickel or other suitable conductive materials.

In this embodiment, the portion of the semiconductor structure 300C in contact with the oxygen absorption layer 222 forms a conductive region 302, and a native metal oxide 310 is included between the semiconductor structure 300C and the oxygen absorption layer 222. In this embodiment, the portion of the semiconductor structure 300C in contact with the metal layer 224 forms a contact region 308. In some embodiments, the carrier concentration of the contact region 308 is lower than the carrier concentration of the conductive region 302. The conductive region 302, the contact region 308, the channel region 304, and the contact region 306 are connected in sequence.

FIG6 is a cross-sectional schematic diagram of a semiconductor device 10D according to an embodiment of the present invention. It must be noted that the embodiment of FIG6 uses the component numbers and some contents of the embodiment of FIG5, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the semiconductor device 10D of FIG. 6 and the semiconductor device 10C of FIG. 5 is that the oxygen absorption layer 222 of the semiconductor device 10D is located between the metal layer 224 and the isolation structure 110.

Referring to FIG. 6 , the second electrode 220D includes a metal layer 224 and an oxygen absorption layer 222. In this embodiment, the metal layer 224 covers the top surface of the oxygen absorption layer 222. The oxide semiconductor structure 300D contacts the top surface of the metal layer 224 and the side surface of the oxygen absorption layer 222. The contact region 308, the conductive region 302, the channel region 304 and the contact region 306 of the oxide semiconductor structure 300D are connected in sequence.

FIG. 7 is a cross-sectional schematic diagram of a semiconductor device 10E according to an embodiment of the present invention. It must be noted that the embodiment of FIG. 7 uses the component numbers and some contents of the embodiment of FIG. 5 , wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the semiconductor device 10E of FIG. 7 and the semiconductor device 10C of FIG. 5 is that the oxygen absorption layer 222 of the semiconductor device 10E separates the metal layer 224 from the oxide semiconductor structure 300E.

Referring to FIG. 7 , the second electrode 220E includes a metal layer 224 and an oxygen absorption layer 222. In this embodiment, the oxygen absorption layer 222 covers the top and side surfaces of the metal layer 224. The oxide semiconductor structure 300E contacts the top and side surfaces of the oxygen absorption layer 222.

FIG8A is a cross-sectional schematic diagram of a simulation structure of a semiconductor device of an embodiment of the present invention. FIG8B is a partial enlarged view of the virtual frame position of FIG8A. FIG9A is a data diagram of the electric field and Y-axis position of the semiconductor devices of Embodiments 1 to 3, wherein the Y-axis position corresponds to the position of arrow E in FIG8A, and the unit of the horizontal axis of FIG9A is micrometer, and the unit of the vertical axis is volt/centimeter (V/cm). FIG9B is a data diagram of the gate voltage and current (Id) of the semiconductor devices of Embodiments 1 to 3. In FIG9A and FIG9B, the semiconductor devices of Embodiments 1 to 3 have similar structures (such as the structure shown in FIG8A). In Examples 1 to 3, the material of the oxide semiconductor structure 300 includes indium gallium zinc oxide, wherein the carrier concentration of the channel region and the contact region respectively contacting the isolation structure 110 and the first electrode 210 (the source in Examples 1 to 3) is the same (for example, 1e16 to 1e18 cm ^-3 ), and the carrier concentration of the conductive region contacting the second electrode 220 (the drain in Examples 1 to 3) is greater than the carrier concentration of the channel region (for example, 5e18 to 1e22 cm ^-3 ). The difference between the first embodiment, the second embodiment and the third embodiment is that the carrier concentration of the conductive region of the oxide semiconductor structure 300 contacting the drain (ie, the second electrode 220) is different, wherein the carrier concentration of the conductive region of the third embodiment is the largest, while the carrier concentration of the conductive region of the first embodiment is the smallest.

When performing the simulation of FIG. 9A, the gate voltage applied to the gate 230 is 5V, and the voltage difference between the first electrode 210 and the second electrode 220 is 5V. When performing the simulation of FIG. 9B, the voltage difference between the first electrode 210 and the second electrode 220 is 5V, and the relationship between the current (Id) between the first electrode 210 and the second electrode 220 and the gate voltage is measured.

By comparing the electric field distributions of Examples 1 to 3, it can be found that the electric field of Example 1 at the second electrode 220 is the weakest. In other words, reducing the carrier concentration of the conductive region at the second electrode 220 (the drain in Examples 1 to 3) can effectively weaken the electric field at the second electrode 220. It can be seen that when the drain includes an oxygen barrier layer, the oxide semiconductor structure 300 can avoid generating an n+ doped region with a high carrier concentration at the position in contact with the drain, thereby reducing the problem of hot carrier effect caused by the electric field.

FIG. 10A is a data graph of the electric field and Y-axis position of the semiconductor devices of Examples 4 to 6, wherein the Y-axis position corresponds to the position of arrow E in FIG. 8A, and the unit of the horizontal axis of FIG. 10A is micrometer, and the unit of the vertical axis is volt/centimeter (V/cm). FIG. 10B is a data graph of the gate voltage and current (Id) of the semiconductor devices of Examples 4 to 6.

In FIG. 10A and FIG. 10B , the semiconductor devices of the fourth to sixth embodiments have similar structures (such as the structure shown in FIG. 8A ). In the fourth to sixth embodiments, the material of the oxide semiconductor structure 300 includes indium-gallium-zinc oxide, wherein the carrier concentration of the channel region and the contact region respectively contacting the isolation structure 110 and the second electrode 220 (the drain in the fourth to sixth embodiments) is the same (e.g., 1e16 to 1e18 cm ^-3 ), and the carrier concentration of the conductive region contacting the first electrode 210 (the source in the fourth to sixth embodiments) is greater than the carrier concentration of the channel region (e.g., 5e18 to 1e22 cm ^-3 ). The difference between the fourth embodiment, the fifth embodiment and the sixth embodiment is that the carrier concentration of the conductive region of the oxide semiconductor structure 300 that contacts (ie, the first electrode 210) is different, wherein the carrier concentration of the conductive region of the sixth embodiment is the largest, while the carrier concentration of the conductive region of the fourth embodiment is the smallest.

When performing the simulation of FIG. 10A, the gate voltage applied to the gate 230 is 5V, and the voltage difference between the first electrode 210 and the second electrode 220 is 5V. When performing the simulation of FIG. 10B, the voltage difference between the first electrode 210 and the second electrode 220 is 5V, and the relationship between the current (Id) between the first electrode 210 and the second electrode 220 and the gate voltage is measured.

By comparing the electric field distribution of Examples 4 to 6, it can be seen that changing the carrier concentration of the conductive region at the first electrode 210 (the source in Examples 4 to 6) has little effect on the electric field. By comparing the data graphs of the gate voltage and the current (Id) of Examples 4 to 6, it can be seen that increasing the carrier concentration of the conductive region at the first electrode 210 (the source in Examples 4 to 6) can effectively increase the current (Id). Based on the above, increasing the carrier concentration of the conductive region contacting the first electrode 210 (the source in Examples 4 to 6) helps to increase the current (Id) without causing a significant impact on the electric field. In other words, when the source includes an oxygen absorption layer, it is beneficial to generate an n+ doped region with high carrier concentration at the location where the oxide semiconductor structure contacts the source, thereby increasing the current (Id).

FIG. 11A is a data graph of the electric field and Y-axis position of the semiconductor devices of Examples 7 to 9, wherein the Y-axis position corresponds to the position of arrow E in FIG. 8A, and the unit of the horizontal axis of FIG. 11A is micrometer, and the unit of the vertical axis is volt/centimeter (V/cm). FIG. 11B and FIG. 11C are data graphs of the gate voltage and current (Id) of the semiconductor devices of Examples 7 to 9.

When performing the simulation of FIG. 11A, the gate voltage applied to the gate 230 is 5V, and the voltage difference between the first electrode 210 and the second electrode 220 is 5V. When performing the simulation of FIG. 11B and FIG. 11C, the voltage difference between the first electrode 210 and the second electrode 220 is 5V, and the relationship between the current (Id) between the first electrode 210 and the second electrode 220 and the gate voltage is measured.

In FIG. 11A , FIG. 11B and FIG. 11C , the semiconductor devices of the seventh to ninth embodiments have similar structures (such as the structure shown in FIG. 8A ). In the seventh to ninth embodiments, the material of the oxide semiconductor structure 300 includes indium-gallium-zinc oxide, wherein the carrier concentration of the channel region contacting the isolation structure 110 is, for example, 1e16 to 1e18 cm ⁻³ . In the seventh and eighth embodiments, the carrier concentration of the conductive region of the oxide semiconductor structure 300 contacting the first electrode 210 (the source in the seventh to ninth embodiments) is greater than the carrier concentration of the channel region (for example, 5e18 to 1e22 cm ⁻³ ). In the seventh embodiment, the carrier concentration of the contact region of the oxide semiconductor structure 300 contacting the second electrode 220 (drain) (e.g., 1e16-1e19 cm ^-3 ) is less than the carrier concentration of the conductive region contacted by the first electrode 210 (source). In the eighth embodiment, the carrier concentration of the contact region (also referred to as the conductive region) of the oxide semiconductor structure 300 contacting the second electrode 220 (drain) (e.g., 5e18-1e22 cm ^-3 ) is equal to the carrier concentration of the conductive region contacted by the first electrode 210 (source). In the ninth embodiment, the carrier concentrations of the regions of the oxide semiconductor structure 300 contacting the first electrode 210 and the second electrode 220 are equal to the carrier concentration of the channel region of the oxide semiconductor structure 300 contacting the isolation structure 110 (e.g., 1e16-1e19 cm ^-3 ). It can also be said that the oxide semiconductor structure 300 of the ninth embodiment does not have regions with different carrier concentrations.

By comparing the electric field distributions of Examples 7 to 9, it can be seen that the electric field near the second electrode 220 (drain) of Examples 7 and 9 is weaker than the electric field near the second electrode 220 (drain) of Example 8. Therefore, it can be seen that reducing the carrier concentration of the oxide semiconductor structure near the drain is beneficial to reducing the problem of hot carrier effect caused by the electric field.

Comparing the data graphs of gate voltage and current (Id) of Examples 7 to 9, it can be seen that the current (Id) between the first electrode 210 and the second electrode 220 of Examples 7 and 8 is significantly greater than the current (Id) between the first electrode 210 and the second electrode 220 of Example 9. It can be seen that increasing the carrier concentration of the oxide semiconductor structure near the source is beneficial to increasing the current of the semiconductor structure.

10A: Semiconductor devices

100:Substrate

102: Buffer layer

110: Isolation structure

110s: Side

120: Gate dielectric layer

210A: First electrode

210t,220t: Top surface

220A: Second electrode

230: Gate

300A: oxide semiconductor structure

302: Conductive area

304: Channel area

306: Contact area

310: Native metal oxides

t1,t2,t3,t4: thickness

Claims (8)

A semiconductor device, comprising: a first electrode; an isolation structure located on the first electrode; a second electrode located on the isolation structure, wherein the second electrode comprises a metal layer and an oxygen absorption layer, wherein the oxygen absorption layer comprises at least one of niobium, titanium, beryllium, aluminum, manganese, chromium, vanadium, calcium and silicon, wherein the metal layer and the oxygen absorption layer comprise different materials; An oxide semiconductor structure extends from the top surface of the second electrode to the top surface of the first electrode and contacts the side surface of the isolation structure, and the oxide semiconductor structure includes a conductive region contacting the oxygen absorption layer and a channel region contacting the isolation structure, wherein the carrier concentration of the conductive region is greater than the carrier concentration of the channel region, wherein the oxygen absorption layer is located between the metal layer and the isolation structure, and wherein the oxide semiconductor structure contacts the top surface of the metal layer and the side surface of the oxygen absorption layer; A gate dielectric layer located on the oxide semiconductor structure; and A gate electrode located on the gate dielectric layer. A semiconductor device, comprising: a first electrode; an isolation structure located on the first electrode; a second electrode located on the isolation structure, wherein the second electrode comprises a metal layer and an oxygen absorption layer, wherein the oxygen absorption layer covers the top surface of the metal layer, wherein the oxygen absorption layer comprises at least one of niobium, titanium, beryllium, aluminum, manganese, chromium, vanadium, calcium and silicon, wherein the metal layer and the oxygen absorption layer comprise different materials; An oxide semiconductor structure extends from the top surface of the second electrode to the top surface of the first electrode and contacts the side surface of the isolation structure, and the oxide semiconductor structure includes a conductive region contacting the oxygen absorption layer and a channel region contacting the isolation structure, wherein the carrier concentration of the conductive region is greater than the carrier concentration of the channel region, and the oxide semiconductor structure contacts the top surface and the side surface of the oxygen absorption layer; A gate dielectric layer is located on the oxide semiconductor structure; and A gate is located on the gate dielectric layer. A semiconductor device as described in claim 2, wherein the oxygen absorption layer covers the side of the metal layer, and the oxygen absorption layer separates the metal layer from the oxide semiconductor structure. A semiconductor device, comprising: a first electrode; an isolation structure, located on the first electrode; a second electrode, located on the isolation structure, wherein one of the first electrode and the second electrode comprises an oxygen absorption layer, wherein the oxygen absorption layer comprises at least one of niobium, titanium, curium, aluminum, manganese, chromium, vanadium, calcium and silicon, wherein the other of the first electrode and the second electrode comprises an oxygen barrier layer, wherein the material of the oxygen barrier layer comprises at least one of tin, copper, molybdenum and nickel; An oxide semiconductor structure extends from the top surface of the second electrode to the top surface of the first electrode and contacts the side surface of the isolation structure, and the oxide semiconductor structure includes a conductive region contacting the oxygen absorption layer and a channel region contacting the isolation structure, wherein the carrier concentration of the conductive region is greater than the carrier concentration of the channel region, wherein the interface between the oxygen absorption layer and the oxide semiconductor structure includes a native metal oxide, wherein the standard Gibbs free energy of formation of the native metal oxide is lower than the standard Gibbs free energy of formation of the oxide semiconductor structure; A gate dielectric layer is located on the oxide semiconductor structure; and A gate is located on the gate dielectric layer. A semiconductor device as described in claim 4, wherein the oxide semiconductor structure further includes a contact region contacting the oxygen barrier layer, wherein the carrier concentration of the contact region is between the carrier concentration of the channel region and the carrier concentration of the conductive region. A semiconductor device as described in claim 4, wherein the first electrode includes the oxygen absorption layer, and the conductive region contacts the isolation structure. A method for manufacturing a semiconductor device, comprising: Forming a stacked structure consisting of a first electrode, an isolation structure and a second electrode, wherein one of the first electrode and the second electrode comprises an oxygen absorption layer, wherein the oxygen absorption layer comprises at least one of niobium, titanium, curium, aluminum, manganese, chromium, vanadium, calcium and silicon; Forming an oxide semiconductor structure on the stacked structure, wherein the oxide semiconductor structure comprises a conductive region contacting the oxygen absorption layer and a channel region contacting the isolation structure, wherein the oxygen element in the conductive region diffuses into the oxygen absorption layer, so that the carrier concentration of the conductive region is greater than the carrier concentration of the channel region; Forming a gate dielectric layer on the oxide semiconductor structure; and Forming a gate electrode on the gate dielectric layer. A method for manufacturing a semiconductor device as described in claim 7, wherein the oxygen element in the conductive region diffuses into the oxygen absorption layer and forms a native metal oxide at the interface between the oxygen absorption layer and the conductive region, wherein the native metal oxide includes an oxide of at least one of cobalt, titanium, curium, aluminum, manganese, chromium, vanadium, calcium and silicon.