TWI879080B - Power supply device with high output stability - Google Patents
Power supply device with high output stability Download PDFInfo
- Publication number
- TWI879080B TWI879080B TW112134613A TW112134613A TWI879080B TW I879080 B TWI879080 B TW I879080B TW 112134613 A TW112134613 A TW 112134613A TW 112134613 A TW112134613 A TW 112134613A TW I879080 B TWI879080 B TW I879080B
- Authority
- TW
- Taiwan
- Prior art keywords
- potential
- coupled
- node
- output
- terminal
- Prior art date
Links
Images
Landscapes
- Dc-Dc Converters (AREA)
Abstract
Description
本發明係關於一種電源供應器,特別係關於一種高輸出穩定度之電源供應器。The present invention relates to a power supply, and more particularly to a power supply with high output stability.
電源供應器為筆記型電腦領域中不可或缺之元件。然而,當電源供應器進行高頻切換時,其內部之諧振電流往往會有失真(Distortion)之現象,此將造成電磁干擾(Electromagnetic Interference,EMI)等問題。有鑑於此,勢必要提出一種全新之解決方案,以克服先前技術所面臨之困境。Power supplies are indispensable components in the field of notebook computers. However, when the power supply performs high-frequency switching, the internal resonant current will often be distorted, which will cause problems such as electromagnetic interference (EMI). In view of this, it is necessary to propose a new solution to overcome the difficulties faced by previous technologies.
在較佳實施例中,本發明提出一種高輸出穩定度之電源供應器,包括:一分壓電路,根據一輸入電位來產生一分壓電位;一切換電路,根據該輸入電位、一第一驅動電位,以及一第二驅動電位來產生一切換電位;一變壓器,包括一主線圈、一第一副線圈,以及一第二副線圈,其中該變壓器內建一漏電感器和一激磁電感器,而該主線圈係經由該漏電感器接收該切換電位;一第一電容器,耦接至該激磁電感器,並提供一電容電位;一輸出級電路,耦接至該第一副線圈和該第二副線圈,並產生一輸出電位和一輸出電流;以及一偵測及控制電路,產生該第一驅動電位和該第二驅動電位;其中該偵測及控制電路更根據該分壓電位、該電容電位、該輸出電位,以及該輸出電流來決定是否降低該第一驅動電位或該第二驅動電位之一電位位準。In a preferred embodiment, the present invention provides a power supply with high output stability, including: a voltage divider circuit, which generates a voltage divider potential according to an input potential; a switching circuit, which generates a switching potential according to the input potential, a first drive potential, and a second drive potential; a transformer, including a main coil, a first secondary coil, and a second secondary coil, wherein the transformer has a built-in leakage inductor and an excitation inductor, and the main coil receives the switching potential through the leakage inductor. ; a first capacitor coupled to the excitation inductor and providing a capacitance potential; an output stage circuit coupled to the first sub-coil and the second sub-coil and generating an output potential and an output current; and a detection and control circuit generating the first driving potential and the second driving potential; wherein the detection and control circuit further determines whether to reduce the potential level of the first driving potential or the second driving potential according to the voltage division potential, the capacitance potential, the output potential, and the output current.
在一些實施例中,該分壓電路包括:一第一電阻器,具有一第一端和一第二端,其中該第一電阻器之該第一端係耦接至一輸入節點以接收該輸入電位,而該第一電阻器之該第二端係耦接至一第一節點以輸出該分壓電位;以及一第二電阻器,具有一第一端和一第二端,其中該第二電阻器之該第一端係耦接至該第一節點,而該第二電阻器之該第二端係耦接至一接地電位。In some embodiments, the voltage divider circuit includes: a first resistor having a first end and a second end, wherein the first end of the first resistor is coupled to an input node to receive the input potential, and the second end of the first resistor is coupled to a first node to output the divided potential; and a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the first node, and the second end of the second resistor is coupled to a ground potential.
在一些實施例中,該切換電路包括:一第一電晶體,具有一控制端、一第一端,以及一第二端,其中該第一電晶體之該控制端係用於接收該第一驅動電位,該第一電晶體之該第一端係耦接至一第二節點以輸出該切換電位,而該第一電晶體之該第二端係耦接至該輸入節點以接收該輸入電位;以及一第二電晶體,具有一控制端、一第一端,以及一第二端,其中該第二電晶體之該控制端係用於接收該第二驅動電位,該第二電晶體之該第一端係耦接至該接地電位,而該第二電晶體之該第二端係耦接至該第二節點。In some embodiments, the switching circuit includes: a first transistor having a control end, a first end, and a second end, wherein the control end of the first transistor is used to receive the first driving potential, the first end of the first transistor is coupled to a second node to output the switching potential, and the second end of the first transistor is coupled to the input node to receive the input potential; and a second transistor having a control end, a first end, and a second end, wherein the control end of the second transistor is used to receive the second driving potential, the first end of the second transistor is coupled to the ground potential, and the second end of the second transistor is coupled to the second node.
在一些實施例中,該漏電感器具有一第一端和一第二端,該漏電感器之該第一端係耦接至該第二節點以接收該切換電位,該漏電感器之該第二端係耦接至一第三節點,該主線圈具有一第一端和一第二端,該主線圈之該第一端係耦接至該第三節點,該主線圈之該第二端係耦接至一第四節點,該激磁電感器具有一第一端和一第二端,該激磁電感器之該第一端係耦接至該第三節點,該激磁電感器之該第二端係耦接至該第四節點,該第一電容器具有一第一端和一第二端,該第一電容器之該第一端係耦接至該第四節點以輸出該電容電位,該第一電容器之該第二端係耦接至該接地電位,該第一副線圈具有一第一端和一第二端,該第一副線圈之該第一端係耦接至一第五節點,該第一副線圈之該第二端係耦接至一共同節點,該第二副線圈具有一第一端和一第二端,該第二副線圈之該第一端係耦接至該共同節點,而該第二副線圈之該第二端係耦接至一第六節點。In some embodiments, the leakage inductor has a first end and a second end, the first end of the leakage inductor is coupled to the second node to receive the switching potential, the second end of the leakage inductor is coupled to a third node, the main coil has a first end and a second end, the first end of the main coil is coupled to the third node, the second end of the main coil is coupled to a fourth node, the excitation inductor has a first end and a second end, the first end of the excitation inductor is coupled to the third node, the second end of the excitation inductor is coupled to the fourth node, and the The first capacitor has a first end and a second end, the first end of the first capacitor is coupled to the fourth node to output the capacitance potential, the second end of the first capacitor is coupled to the ground potential, the first sub-coil has a first end and a second end, the first end of the first sub-coil is coupled to a fifth node, the second end of the first sub-coil is coupled to a common node, the second sub-coil has a first end and a second end, the first end of the second sub-coil is coupled to the common node, and the second end of the second sub-coil is coupled to a sixth node.
在一些實施例中,該輸出級電路包括:一第一二極體,具有一陽極和一陰極,其中該第一二極體之該陽極係耦接至該第五節點,而該第一二極體之該陰極係耦接至一輸出節點以輸出該輸出電位;一第二二極體,具有一陽極和一陰極,其中該第二二極體之該陽極係耦接至該第六節點,而該第二二極體之該陰極係耦接至該輸出節點;一第二電容器,具有一第一端和一第二端,其中該第二電容器之該第一端係耦接至該輸出節點,而該第二電容器之該第二端係耦接至一第七節點;以及一第三電阻器,具有一第一端和一第二端,其中該第三電阻器之該第一端係耦接至該共同節點,而該第三電阻器之該第二端係耦接至該第七節點;其中該輸出電流係流經該第二電容器和該第三電阻器。In some embodiments, the output stage circuit includes: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to the fifth node, and the cathode of the first diode is coupled to an output node to output the output potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to the sixth node, and the cathode of the second diode is coupled to the output node; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to the sixth node, and the cathode of the second diode is coupled to the output node; a capacitor having a first end and a second end, wherein the first end of the second capacitor is coupled to the output node, and the second end of the second capacitor is coupled to a seventh node; and a third resistor having a first end and a second end, wherein the first end of the third resistor is coupled to the common node, and the second end of the third resistor is coupled to the seventh node; wherein the output current flows through the second capacitor and the third resistor.
在一些實施例中,該偵測及控制電路包括:一放大器,放大該電容電位,以產生一放大電位。In some embodiments, the detection and control circuit includes: an amplifier that amplifies the capacitor potential to generate an amplified potential.
在一些實施例中,該偵測及控制電路更包括:一比較電路,將該共同節點處之一共同電位與該第七節點處之一感測電位互相比較,以產生一比較電位。In some embodiments, the detection and control circuit further includes: a comparison circuit that compares a common potential at the common node with a sensed potential at the seventh node to generate a comparison potential.
在一些實施例中,該偵測及控制電路更包括:一及閘,具有一第一輸入端、一第二輸入端、一第三輸入端、一第四輸入端,以及一輸出端,其中該及閘之該第一輸入端係用於接收該分壓電位,該及閘之該第二輸入端係用於接收該放大電位,該及閘之該第三輸入端係用於接收該比較電位,該及閘之該第四輸入端係用於接收該輸出電位,而該及閘之該輸出端係用於輸出一邏輯電位。In some embodiments, the detection and control circuit further includes: an AND gate having a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, and an output terminal, wherein the first input terminal of the AND gate is used to receive the divided potential, the second input terminal of the AND gate is used to receive the amplified potential, the third input terminal of the AND gate is used to receive the comparison potential, the fourth input terminal of the AND gate is used to receive the output potential, and the output terminal of the AND gate is used to output a logic potential.
在一些實施例中,該偵測及控制電路更包括:一微控制器,產生該第一驅動電位和該第二驅動電位,其中若該邏輯電位具有高邏輯位準,則該微控制器將於一既定時間內將該第一驅動電位或該第二驅動電位之該電位位準暫時降低一既定比例。In some embodiments, the detection and control circuit further includes: a microcontroller that generates the first driving potential and the second driving potential, wherein if the logic potential has a high logic level, the microcontroller will temporarily reduce the potential level of the first driving potential or the second driving potential by a predetermined ratio within a predetermined time.
在一些實施例中,該既定時間約為0.66μs,而該既定比例約為70%。In some embodiments, the predetermined time is approximately 0.66 μs, and the predetermined ratio is approximately 70%.
為讓本發明之目的、特徵和優點能更明顯易懂,下文特舉出本發明之具體實施例,並配合所附圖式,作詳細說明如下。In order to make the purpose, features and advantages of the present invention more clearly understood, specific embodiments of the present invention are specifically listed below and described in detail with reference to the accompanying drawings.
在說明書及申請專利範圍當中使用了某些詞彙來指稱特定的元件。本領域技術人員應可理解,硬體製造商可能會用不同的名詞來稱呼同一個元件。本說明書及申請專利範圍並不以名稱的差異來作為區分元件的方式,而是以元件在功能上的差異來作為區分的準則。在通篇說明書及申請專利範圍當中所提及的「包含」及「包括」一詞為開放式的用語,故應解釋成「包含但不僅限定於」。「大致」一詞則是指在可接受的誤差範圍內,本領域技術人員能夠在一定誤差範圍內解決所述技術問題,達到所述基本之技術效果。此外,「耦接」一詞在本說明書中包含任何直接及間接的電性連接手段。因此,若文中描述一第一裝置耦接至一第二裝置,則代表該第一裝置可直接電性連接至該第二裝置,或經由其它裝置或連接手段而間接地電性連接至該第二裝置。Certain terms are used in the specification and patent application to refer to specific components. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. This specification and patent application do not use differences in names as a way to distinguish components, but use differences in the functions of components as the criterion for distinction. The words "include" and "including" mentioned throughout the specification and patent application are open terms and should be interpreted as "including but not limited to". The word "substantially" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. In addition, the word "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is described herein as being coupled to a second device, it means that the first device may be directly electrically connected to the second device, or may be indirectly electrically connected to the second device via other devices or connection means.
第1圖係顯示根據本發明一實施例所述之電源供應器100之示意圖。例如,電源供應器100可應用於桌上型電腦、筆記型電腦,或一體成形電腦。如第1圖所示,電源供應器100包括:一分壓電路110、一切換電路120、一變壓器130、一第一電容器C1、一輸出級電路140,以及一偵測及控制電路150。必須注意的是,雖然未顯示於第1圖中,但電源供應器100更可包括其他元件,例如:一穩壓器或(且)一負回授電路。FIG. 1 is a schematic diagram showing a
分壓電路110可根據一輸入電位VIN來產生一分壓電位VD。例如,輸入電位VIN可為一直流電位,其電位位準可介於360V至440V之間,但亦不僅限於此。分壓電位VD可低於輸入電位VIN。切換電路120可根據輸入電位VIN、一第一驅動電位VG1,以及一第二驅動電位VG2來產生一切換電位VW。變壓器130包括一主線圈131、一第一副線圈132,以及一第二副線圈133。變壓器130更可內建一漏電感器LR和一激磁電感器LM,其中漏電感器LR、激磁電感器LM,以及主線圈131皆可位於變壓器130之同一側,而第一副線圈132和第二副線圈133則皆可位於變壓器130之相對另一側。主線圈131可經由漏電感器LR接收切換電位VW,而第一副線圈132和第二副線圈133則可回應於切換電位VW來進行操作。第一電容器C1係耦接至激磁電感器LM,其中第一電容器C1可提供一電容電位VP。在一些實施例中,漏電感器LR、激磁電感器LM,以及第一電容器C1三者可共同形成電源供應器100之一諧振槽(Resonant Tank)。輸出級電路140係耦接至第一副線圈132和第二副線圈133,並可產生一輸出電位VOUT和一輸出電流IOUT。例如,輸出電位VOUT可為另一直流電位,其電位位準可介於18V至20V之間,但亦不僅限於此。偵測及控制電路150可產生第一驅動電位VG1和第二驅動電位VG2。另外,偵測及控制電路150可用於監控其餘電路元件之操作狀態,其中偵測及控制電路150更可根據分壓電位VD、電容電位VP、輸出電位VOUT,以及輸出電流IOUT來決定是否降低第一驅動電位VG1或第二驅動電位VG2之一電位位準。根據實際量測結果,本發明所提之電源供應器100將可有效抑制其非理想失真現象,從而能大幅提升其自身之輸出穩定度。The
以下實施例將介紹電源供應器100之詳細結構及操作方式。必須理解的是,這些圖式和敘述僅為舉例,而非用於限制本發明之範圍。The following embodiments will introduce the detailed structure and operation of the
第2圖係顯示根據本發明一實施例所述之電源供應器200之電路圖。在第2圖之實施例中,在第2圖之實施例中,電源供應器200具有一輸入節點NIN和一輸出節點NOUT,並包括:一分壓電路210、一切換電路220、一變壓器230、一第一電容器C1、一輸出級電路240,以及一偵測及控制電路250。電源供應器200之輸入節點NIN可由一外部輸入電源處(未顯示)接收一輸入電位VIN,而電源供應器200之輸出節點NOUT則可用於輸出一輸出電位VOUT至一電子裝置(未顯示)。FIG. 2 is a circuit diagram of a
分壓電路210包括一第一電阻器R1和一第二電阻器R2。第一電阻器R1具有一第一端和一第二端,其中第一電阻器R1之第一端係耦接至輸入節點NIN,而第一電阻器R1之第二端係耦接至一第一節點N1以輸出一分壓電位VD。第二電阻器R2具有一第一端和一第二端,其中第二電阻器R2之第一端係耦接至第一節點N1,而第二電阻器R2之第二端係耦接至一接地電位VSS(例如:0V)。在一些實施例中,分壓電位VD和輸入電位VIN之間之關係可如下列方程式(1)所述:The
…………………………………(1) 其中「VD」代表分壓電位VD之電位位準,「VIN」代表輸入電位VIN之電位位準,「R1」代表第一電阻器R1之電阻值,而「R2」代表第二電阻器R2之電阻值。 ………………………………(1) Wherein “VD” represents the potential level of the divided potential VD, “VIN” represents the potential level of the input potential VIN, “R1” represents the resistance value of the first resistor R1, and “R2” represents the resistance value of the second resistor R2.
切換電路220包括一第一電晶體M1和一第二電晶體M2。例如,第一電晶體M1和第二電晶體M2可各自為一N型金氧半場效電晶體(N-type Metal-Oxide-Semiconductor Field-Effect Transistor,NMOSFET)。第一電晶體M1具有一控制端(例如:一閘極)、一第一端(例如:一源極),以及一第二端(例如:一汲極),其中第一電晶體M1之控制端係用於接收一第一驅動電位VG1,第一電晶體M1之第一端係耦接至一第二節點N2以輸出一切換電位VW,而第一電晶體M1之第二端係耦接至輸入節點NIN。第二電晶體M2具有一控制端(例如:一閘極)、一第一端(例如:一源極),以及一第二端(例如:一汲極),其中第二電晶體M2之控制端係用於接收一第二驅動電位VG2,第二電晶體M2之第一端係耦接至接地電位VSS,而第二電晶體M2之第二端係耦接至第二節點N2。在一些實施例中,第一驅動電位VG1和第二驅動電位VG2兩者可具有相同之切換頻率和互補(Complementary)之邏輯位準。The
變壓器230包括一主線圈231、一第一副線圈232,以及一第二副線圈233,其中變壓器230更可內建一漏電感器LR和一激磁電感器LM。漏電感器LR和激磁電感器LM皆可為變壓器230製造時所附帶產生之固有元件,其並非外部獨立元件。漏電感器LR、主線圈231,以及激磁電感器LM皆可位於變壓器230之同一側(例如:一次側),而第一副線圈232和第二副線圈233則皆可位於變壓器230之相對另一側(例如:二次側,其可與一次側互相隔離開來)。漏電感器LR具有一第一端和一第二端,其中漏電感器LR之第一端係耦接至第二節點N2以接收切換電位VW,而漏電感器LR之第二端係耦接至一第三節點N3。主線圈231具有一第一端和一第二端,其中主線圈231之第一端係耦接至第三節點N3,而主線圈231之第二端係耦接至一第四節點N4。激磁電感器LM具有一第一端和一第二端,其中激磁電感器LM之第一端係耦接至第三節點N3,而激磁電感器LM之第二端係耦接至第四節點N4。第一電容器C1具有一第一端和一第二端,其中第一電容器C1之第一端係耦接至第四節點N4以輸出一電容電位VP,而第一電容器C1之第二端係耦接至接地電位VSS。在一些實施例中,漏電感器LR、激磁電感器LM,以及第一電容器C1三者可共同形成電源供應器200之一諧振槽,其中一諧振電流IR可同時流經此諧振槽之漏電感器LR、激磁電感器LM,以及第一電容器C1。第一副線圈232具有一第一端和一第二端,其中第一副線圈232之第一端係耦接至一第五節點N5,而第一副線圈232之第二端係耦接至一共同節點NCM。例如,共同節點NCM可提供一共同電位VCM,其可被視為另一接地電位,並可與前述之接地電位VSS相同或相異。第二副線圈233具有一第一端和一第二端,其中第二副線圈233之第一端係耦接至共同節點NCM,而第二副線圈233之第二端係耦接至一第六節點N6。The
輸出級電路240包括一第一二極體D1、一第二二體體D2、一第二電容器C2,以及一第三電阻器R3。第一二極體D1具有一陽極和一陰極,其中第一二極體D1之陽極係耦接至第五節點N5,而第一二極體D1之陰極係耦接至輸出節點NOUT。第二二極體D2具有一陽極和一陰極,其中第二二極體D2之陽極係耦接至第六節點N6,而第二二極體D2之陰極係耦接至輸出節點NOUT。第二電容器C2具有一第一端和一第二端,其中第二電容器C2之第一端係耦接至輸出節點NOUT,而第二電容器C2之第二端係耦接至一第七節點N7。第三電阻器R3可提供相對較低之一電阻值(例如:小於或等於5Ω)。第三電阻器R3具有一第一端和一第二端,其中第三電阻器R3之第一端係耦接至共同節點NCM,而第三電阻器R3之第二端係耦接至第七節點N7。必須注意的是,輸出級電路240之一輸出電流IOUT可同時流經第二電容器C2和第三電阻器R3,使得第三電阻器R3能於第七節點N7處提供一感測電位VE。The
偵測及控制電路250包括:一放大器(Amplifier)252、一比較電路(Comparison Circuit)254、一及閘(AND Gate)256,以及一微控制器(Microcontroller Unit,MCU)258。The detection and
放大器252可根據一增益倍率K來放大電容電位VP,以產生一放大電位VA。例如,增益倍率K可大於1。在一些實施例中,放大電位VA和電容電位VP之間之關係可如下列方程式(2)所述:The
…………………………………………(2) 其中「VA」代表放大電位VA之電位位準,「VP」代表電容電位VP之電位位準,而「K」代表增益倍率K之數值。 …………………………………………(2) “VA” represents the potential level of the amplifier potential VA, “VP” represents the potential level of the capacitor potential VP, and “K” represents the value of the gain factor K.
比較電路254可將共同節點NCM處之共同電位VCM與第七節點N7處之感測電位VE互相比較,以產生一比較電位VB。在一些實施例中,比較電路254可包括一減法器(未顯示),其可藉由將感測電位VE減去共同電位VCM來取得跨越第三電阻器R3之一電位差ΔV。根據歐姆定律,電位差ΔV之大小可與輸出電流IOUT之電流值兩者大致呈正比關係。因此,比較電路254將可根據電位差ΔV來取得輸出電流IOUT之相關資訊。例如,若感測電位VE恰等於共同電位VCM(亦即,電位差ΔV恰等於0),則代表輸出電流IOUT恰等於0,而比較電路254將可輸出具有高邏輯位準之比較電位VB。反之,若感測電位VE不等於共同電位VCM(亦即,電位差ΔV不等於0),則代表輸出電流IOUT不等於0,而比較電路254將可輸出具有低邏輯位準之比較電位VB。The comparison circuit 254 can compare the common potential VCM at the common node NCM with the sensed potential VE at the seventh node N7 to generate a comparison potential VB. In some embodiments, the comparison circuit 254 can include a subtractor (not shown) that can obtain a potential difference ΔV across the third resistor R3 by subtracting the common potential VCM from the sensed potential VE. According to Ohm's law, the magnitude of the potential difference ΔV can be roughly proportional to the current value of the output current IOUT. Therefore, the comparison circuit 254 can obtain relevant information of the output current IOUT according to the potential difference ΔV. For example, if the sensed potential VE is exactly equal to the common potential VCM (i.e., the potential difference ΔV is exactly equal to 0), it means that the output current IOUT is exactly equal to 0, and the comparison circuit 254 can output the comparison potential VB with a high logic level. On the contrary, if the sensed potential VE is not equal to the common potential VCM (i.e., the potential difference ΔV is not equal to 0), it means that the output current IOUT is not equal to 0, and the comparison circuit 254 can output the comparison potential VB with a low logic level.
及閘256具有一第一輸入端、一第二輸入端、一第三輸入端、一第四輸入端,以及一輸出端,其中及閘256之第一輸入端係用於接收分壓電位VD,及閘256之第二輸入端係用於接收放大電位VA,及閘256之第三輸入端係用於接收比較電位VB,及閘256之第四輸入端係用於接收輸出電位VOUT,而及閘256之輸出端係用於輸出一邏輯電位VL。大致而言,當電源供應器200正常操作且輸出電流IOUT等於0時,及閘256將會產生具有高邏輯位準之邏輯電位VL。否則,及閘256將會產生具有低邏輯位準之邏輯電位VL。The AND
微控制器258可產生第一驅動電位VG1和第二驅動電位VG2。在一些實施例中,若邏輯電位VL具有低邏輯位準,則微控制器258將不會額外調整第一驅動電位VG1和第二驅動電位VG2;反之,若邏輯電位VL具有高邏輯位準,則微控制器258將於一既定時間TD內將第一驅動電位VG1或第二驅動電位VG2之電位位準暫時降低一既定比例DR。例如,既定時間TD可約為0.66μs,而既定比例DR可約為70%,但亦不僅限於此。The
第3圖係顯示傳統電源供應器之信號波形圖,其中橫軸代表時間(s),而縱軸代表電位位準(V)或電流值(A)。如第3圖所示,於第一驅動電位VG1之高邏輯期間,其對應之諧振電流IR可能會發生失真現象(如一第一虛線框301所指處),而於第二驅動電位VG2之高邏輯期間,其對應之諧振電流IR亦可能會發生失真現象(如一第二虛線框302所處)。因此,傳統電源供應器常面臨輸出穩定度不足之問題。FIG. 3 shows a signal waveform diagram of a conventional power supply, wherein the horizontal axis represents time (s) and the vertical axis represents potential level (V) or current value (A). As shown in FIG. 3, during the high logic period of the first driving potential VG1, the corresponding resonant current IR may be distorted (as indicated by a first dashed frame 301), and during the high logic period of the second driving potential VG2, the corresponding resonant current IR may also be distorted (as indicated by a second dashed frame 302). Therefore, conventional power supplies often face the problem of insufficient output stability.
第4圖係顯示根據本發明一實施例所述之電源供應器200之信號波形圖,其中橫軸代表時間(s),而縱軸代表電位位準(V)或電流值(A)。如第4圖所示,在流經第一二極體D1之一第一電流I1下降至0之後,微控制器258可於既定時間TD內將第一驅動電位VG1之電位位準暫時降低既定比例DR。例如,若既定比例DR為70%,則降低後之第一驅動電位VG1之電位位準將僅為其原先電位位準之30%。另外,在流經第二二極體D2之一第二電流I2下降至0之後,微控制器258亦可於既定時間TD內將第二驅動電位VG2之電位位準暫時降低既定比例DR。例如,若既定比例DR為70%,則降低後之第二驅動電位VG2之電位位準將僅為其原先電位位準之30%。必須注意的是,降低後之第一驅動電位VG1或降低後之第二驅動電位VG2均可避免切換電路220完全導通,從而可緩衝(Buffer)電源供應器200之諧振電流IR。根據第4圖之量測結果,在本發明之設計下,電源供應器200之諧振電流IR幾乎不會再出現非理想失真之現象,故其整體之輸出穩定度將可大幅提升。FIG. 4 is a signal waveform diagram of the
本發明提出一種新穎之電源供應器。根據實際量測結果,使用前述設計之電源供應器其整體之輸出穩定度將有明顯改善,故其很適合應用於各種各式之裝置當中。The present invention proposes a novel power supply. According to actual measurement results, the overall output stability of the power supply using the above design will be significantly improved, so it is very suitable for application in various types of devices.
值得注意的是,以上所述之電位、電流、電阻值、電感值、電容值,以及其餘元件參數均非為本發明之限制條件。設計者可以根據不同需要調整這些設定值。本發明之電源供應器並不僅限於第1-4圖所圖示之狀態。本發明可以僅包括第1-4圖之任何一或複數個實施例之任何一或複數項特徵。換言之,並非所有圖示之特徵均須同時實施於本發明之電源供應器當中。雖然本發明之實施例係使用金氧半場效電晶體為例,但本發明並不僅限於此,本技術領域人士可改用其他種類之電晶體,例如:接面場效電晶體,或是鰭式場效電晶體等等,而不致於影響本發明之效果。It is worth noting that the potential, current, resistance, inductance, capacitance, and other component parameters described above are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The power supply of the present invention is not limited to the states shown in Figures 1-4. The present invention may only include any one or more features of any one or more embodiments of Figures 1-4. In other words, not all of the features shown in the diagrams need to be implemented in the power supply of the present invention at the same time. Although the embodiments of the present invention use metal oxide semi-conductor field effect transistors as an example, the present invention is not limited to this. People skilled in the art can use other types of transistors, such as junction field effect transistors, or fin field effect transistors, etc., without affecting the effects of the present invention.
在本說明書以及申請專利範圍中的序數,例如「第一」、「第二」、「第三」等等,彼此之間並沒有順序上的先後關係,其僅用於標示區分兩個具有相同名字之不同元件。Ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., have no sequential relationship with each other, and are only used to mark and distinguish two different components with the same name.
本發明雖以較佳實施例揭露如上,然其並非用以限定本發明的範圍,任何熟習此項技藝者,在不脫離本發明之精神和範圍內,當可做些許的更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention is disclosed as above with the preferred embodiments, it is not intended to limit the scope of the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached patent application.
100,200:電源供應器 110,210:分壓電路 120,220:切換電路 130,230:變壓器 131,231:主線圈 132,232:第一副線圈 133,233:第二副線圈 140,240:輸出級電路 150,250:偵測及控制電路 252:放大器 254:比較電路 256:及閘 258:微控制器 301:第一虛線框 302:第二虛線框 C1:第一電容器 C2:第二電容器 D1:第一二極體 D2:第一二極體 DR:既定比例 I1:第一電流 I2:第二電流 IOUT:輸出電流 IR:諧振電流 K:增益倍率 LM:激磁電感器 LR:漏電感器 M1:第一電晶體 M2:第二電晶體 N1:第一節點 N2:第二節點 N3:第三節點 N4:第四節點 N5:第五節點 N6:第六節點 N7:第七節點 NCM:共同節點 NIN:輸入節點 NOUT:輸出節點 R1:第一電阻器 R2:第二電阻器 R3:第三電阻器 TD:既定時間 VA:放大電位 VB:比較電位 VCM:共同電位 VD:分壓電位 VE:感測電位 VG1:第一驅動電位 VG2:第二驅動電位 VIN:輸入電位 VL:邏輯電位 VOUT:輸出電位 VP:電容電位 VSS:接地電位 VW:切換電位 ΔV:電位差 100,200: Power supply 110,210: Voltage divider circuit 120,220: Switching circuit 130,230: Transformer 131,231: Main coil 132,232: First secondary coil 133,233: Second secondary coil 140,240: Output stage circuit 150,250: Detection and control circuit 252: Amplifier 254: Comparison circuit 256: AND gate 258: Microcontroller 301: First dashed frame 302: Second dashed frame C1: First capacitor C2: Second capacitor D1: First diode D2: First diode DR: Predetermined ratio I1: First current I2: Second current IOUT: Output current IR: Resonance current K: Gain factor LM: Magnetizing inductor LR: Leakage inductor M1: First transistor M2: Second transistor N1: First node N2: Second node N3: Third node N4: Fourth node N5: Fifth node N6: Sixth node N7: Seventh node NCM: Common node NIN: Input node NOUT: Output node R1: First resistor R2: Second resistor R3: Third resistor TD: Determined time VA: Amplified potential VB: Comparison potential VCM: Common potential VD: Voltage divider potential VE: Sense potential VG1: First drive potential VG2: Second drive potential VIN: Input potential VL: logic potential VOUT: output potential VP: capacitor potential VSS: ground potential VW: switching potential ΔV: potential difference
第1圖係顯示根據本發明一實施例所述之電源供應器之示意圖。 第2圖係顯示根據本發明一實施例所述之電源供應器之電路圖。 第3圖係顯示傳統電源供應器之信號波形圖。 第4圖係顯示根據本發明一實施例所述之電源供應器之信號波形圖。 FIG. 1 is a schematic diagram showing a power supply according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a power supply according to an embodiment of the present invention. FIG. 3 is a signal waveform diagram showing a conventional power supply. FIG. 4 is a signal waveform diagram showing a power supply according to an embodiment of the present invention.
100:電源供應器 110:分壓電路 120:切換電路 130:變壓器 131:主線圈 132:第一副線圈 133:第二副線圈 140:輸出級電路 150:偵測及控制電路 C1:第一電容器 IOUT:輸出電流 LM:激磁電感器 LR:漏電感器 VD:分壓電位 VIN:輸入電位 VG1:第一驅動電位 VG2:第二驅動電位 VOUT:輸出電位 VP:電容電位 VW:切換電位 100: Power supply 110: Voltage divider circuit 120: Switching circuit 130: Transformer 131: Main coil 132: First secondary coil 133: Second secondary coil 140: Output stage circuit 150: Detection and control circuit C1: First capacitor IOUT: Output current LM: Magnetizing inductor LR: Leakage inductor VD: Voltage divider potential VIN: Input potential VG1: First drive potential VG2: Second drive potential VOUT: Output potential VP: Capacitor potential VW: Switching potential
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW112134613A TWI879080B (en) | 2023-09-12 | 2023-09-12 | Power supply device with high output stability |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW112134613A TWI879080B (en) | 2023-09-12 | 2023-09-12 | Power supply device with high output stability |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW202512638A TW202512638A (en) | 2025-03-16 |
| TWI879080B true TWI879080B (en) | 2025-04-01 |
Family
ID=95828595
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW112134613A TWI879080B (en) | 2023-09-12 | 2023-09-12 | Power supply device with high output stability |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI879080B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW202315297A (en) * | 2021-09-23 | 2023-04-01 | 台達電子工業股份有限公司 | Isolated resonant dc-dc converter |
| TWI812407B (en) * | 2022-08-17 | 2023-08-11 | 宏碁股份有限公司 | Power supply device with high output stability |
| US20230275523A1 (en) * | 2019-04-24 | 2023-08-31 | Power Integrations, Inc. | Mode operation detection for control of a power converter with an active clamp switch |
-
2023
- 2023-09-12 TW TW112134613A patent/TWI879080B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20230275523A1 (en) * | 2019-04-24 | 2023-08-31 | Power Integrations, Inc. | Mode operation detection for control of a power converter with an active clamp switch |
| TW202315297A (en) * | 2021-09-23 | 2023-04-01 | 台達電子工業股份有限公司 | Isolated resonant dc-dc converter |
| TWI812407B (en) * | 2022-08-17 | 2023-08-11 | 宏碁股份有限公司 | Power supply device with high output stability |
Also Published As
| Publication number | Publication date |
|---|---|
| TW202512638A (en) | 2025-03-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI790937B (en) | Power supply device for suppressing magnetic saturation | |
| US11336191B1 (en) | Power supply device with low loss | |
| TW202349837A (en) | Power supply device with fast discharge function | |
| TWI850814B (en) | Power supply device with high output voltage stability | |
| TWI837944B (en) | Power supply device with high output stability | |
| TWI812354B (en) | Power supply device with high efficiency | |
| TW202505346A (en) | Power supply device for reducing power consumption | |
| TW202435550A (en) | Power supply device with high output stability | |
| TWI879080B (en) | Power supply device with high output stability | |
| US11362510B2 (en) | Power supply device for eliminating malfunction of overcurrent protection | |
| TWI837701B (en) | Boost converter for increasing output stability | |
| TWI837663B (en) | Power supply device for suppressing magnetic saturation | |
| TWI879606B (en) | Power supply device with low loss | |
| US11171567B1 (en) | Power supply device for eliminating ringing effect | |
| TWI879622B (en) | Power supply device for suppressing electromagnetic interference | |
| TWI857781B (en) | Power supply device with high conversion efficiency | |
| CN117097133A (en) | Power supply device for inhibiting magnetic saturation | |
| TWI891526B (en) | Power supply device with high output stability | |
| TWI879623B (en) | Power supply device for suppressing electromagnetic interference | |
| TWI891527B (en) | Power supply device with high output stability | |
| TWI844373B (en) | Power supply device with low switching loss | |
| TWI886000B (en) | Power supply device with high output stability | |
| TWI865371B (en) | Power supply device with high output stability | |
| TWI715487B (en) | Power supply device for eliminating ringing effect | |
| TWI871925B (en) | Power supply device with high output stability |