TWI871925B - Power supply device with high output stability - Google Patents

Abstract

A power supply device with high output stability includes a bridge rectifier, a voltage divider circuit, a tunable capacitive element, a boost inductor, a power switch element, an output stage circuit, a feedback compensation circuit, and a detection and control circuit. The bridge rectifier generates a rectified voltage according to a first input voltage and a second input voltage. The voltage divider circuit generates a first divided voltage according to the rectified voltage. The equivalent capacitance of the tunable capacitive element is determined according to a first control voltage and a second control voltage. The boost inductor is coupled to the tunable capacitive element. The output stage circuit is coupled to the boost inductor, and generates an output voltage. The detection and control circuit generates the first control voltage and the second control voltage according to the first divided voltage.

Description

High output stability power supply

The present invention relates to a power supply, and more particularly to a power supply with high output stability.

Power supplies are indispensable components in the field of laptop computers. However, if the output stability of the power supply is insufficient, it is easy to cause the overall operating performance of the related laptop to decline. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by previous technologies.

In a preferred embodiment, the present invention provides a power supply with high output stability, comprising: a bridge rectifier, generating a rectified potential according to a first input potential and a second input potential; a voltage divider circuit, generating a first divided potential according to the rectified potential; an adjustable capacitor element, storing the rectified potential, wherein an equivalent capacitance value of the adjustable capacitor element is determined according to a first control potential and a second control potential; a boost inductor, coupled to the adjustable capacitor element; A power switch selectively couples the boost inductor to a common node according to a pulse width modulation potential; an output stage circuit coupled to the boost inductor and generates an output potential; a feedback compensation circuit generates a feedback potential and a capacitor potential according to the output potential; and a detection and control circuit generates the pulse width modulation potential, the first control potential, and the second control potential according to the first divided potential, the feedback potential, and the capacitor potential.

In some embodiments, the bridge rectifier includes: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential , and the cathode of the second diode is coupled to the first node; a third diode having an anode and a cathode, wherein the anode of the third diode is coupled to a ground potential, and the cathode of the third diode is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node.

In some embodiments, the voltage divider circuit includes: a first resistor having a first end and a second end, wherein the first end of the first resistor is coupled to the first node to receive the rectified potential, and the second end of the first resistor is coupled to a second node to output the first divided potential; and a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the second node, and the second end of the second resistor is coupled to the ground potential.

In some embodiments, the adjustable capacitance element includes: a first capacitor having a first end and a second end, wherein the first end of the first capacitor is coupled to the first node to receive the rectified potential, and the second end of the first capacitor is coupled to the ground potential; a first transistor having a control end, a first end, and a second end, wherein the control end of the first transistor is used to receive the first control potential, the first end of the first transistor is coupled to a third node, and the second end of the first transistor is coupled to the first node; a second capacitor having a first end and a second end, wherein the first end of the second capacitor is coupled to the third node, and the second end of the second capacitor is coupled to the ground potential. The second end is coupled to the ground potential; a second transistor having a control end, a first end, and a second end, wherein the control end of the second transistor is used to receive the second control potential, the first end of the second transistor is coupled to a fourth node, and the second end of the second transistor is coupled to the first node; and a third capacitor having a first end and a second end, wherein the first end of the third capacitor is coupled to the fourth node, and the second end of the third capacitor is coupled to the ground potential; wherein the boost inductor has a first end and a second end, the first end of the boost inductor is coupled to the first node, and the second end of the boost inductor is coupled to a fifth node.

In some embodiments, the power switch includes: a third transistor having a control end, a first end, and a second end, wherein the control end of the third transistor is used to receive the pulse width modulation potential, the first end of the third transistor is coupled to the common node, and the second end of the third transistor is coupled to the fifth node.

In some embodiments, the output stage circuit includes: a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the fifth node, and the cathode of the fifth diode is coupled to an output node to output the output potential; and a fourth capacitor having a first end and a second end, wherein the first end of the fourth capacitor is coupled to the output node, and the second end of the fourth capacitor is coupled to the common node.

In some embodiments, the feedback compensation circuit includes: a third resistor having a first end and a second end, wherein the first end of the third resistor is coupled to the output node to receive the output potential, and the second end of the third resistor is coupled to a sixth node to output a second divided voltage potential; a fourth resistor having a first end and a second end, wherein the first end of the fourth resistor is coupled to the sixth node, and the second end of the fourth resistor is coupled to the common node; a fifth capacitor having a first end and a second end, wherein the first end of the fifth capacitor is coupled to a seventh node, and the second end of the fifth capacitor is coupled to the sixth node; a voltage regulator having an anode, a cathode, and a reference terminal, wherein the anode of the voltage regulator is coupled to the common node The output node is connected to the output node, the cathode of the voltage regulator is coupled to the seventh node, and the reference terminal of the voltage regulator is coupled to the sixth node; a linear optical coupler, comprising a light-emitting diode and a bipolar junction transistor, wherein the light-emitting diode has an anode and a cathode, the anode of the light-emitting diode is coupled to the output node, the cathode of the light-emitting diode is coupled to the seventh node, and the bipolar junction transistor is coupled to the output node. The crystal has a collector and an emitter, the collector of the bipolar junction transistor is used to output the feedback potential, and the emitter of the bipolar junction transistor is coupled to an eighth node; and a sixth capacitor has a first end and a second end, wherein the first end of the sixth capacitor is coupled to the eighth node to output the capacitance potential, and the second end of the sixth capacitor is coupled to the ground potential.

In some embodiments, the detection and control circuit includes: an amplifier circuit, which amplifies the capacitor potential by a first gain factor to generate a first amplified potential, and amplifies the capacitor potential by a second gain factor to generate a second amplified potential, wherein the first gain factor is greater than the second gain factor; a first comparator, having a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal of the first comparator is used to receive the first amplified potential, and the negative input terminal of the first comparator is used to receive the first amplified potential. The negative input terminal of a comparator is used to receive the first divided voltage, and the output terminal of the first comparator is used to output a first comparison potential; and a second comparator has a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal of the second comparator is used to receive the second amplified potential, the negative input terminal of the second comparator is used to receive the first divided voltage, and the output terminal of the second comparator is used to output a second comparison potential.

In some embodiments, the detection and control circuit further includes: a first AND gate having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first AND gate is used to receive the first comparison potential, the second input terminal of the first AND gate is used to receive the first amplified potential, and the output terminal of the first AND gate is used to output a first logic potential; and a second AND gate having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second AND gate is used to receive the second comparison potential, the second input terminal of the second AND gate is used to receive the second amplified potential, and the output terminal of the second AND gate is used to output a second logic potential.

In some embodiments, the detection and control circuit further includes: a microcontroller, which generates the pulse width modulation potential, the first control potential, and the second control potential according to the first logic potential, the second logic potential, and the feedback potential; wherein if the first divided voltage potential is higher than the first amplified potential, the first control potential and the second control potential are both low logic levels; wherein if the first divided voltage potential is between the second amplified potential and the first amplified potential, the first control potential is a high logic level and the second control potential is a low logic level; wherein if the first divided voltage potential is lower than the second amplified potential, the first control potential and the second control potential are both high logic levels.

In order to make the purpose, features and advantages of the present invention more clearly understood, specific embodiments of the present invention are specifically listed below and described in detail with reference to the accompanying drawings.

Certain terms are used in the specification and patent application to refer to specific components. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. This specification and patent application do not use differences in names as a way to distinguish components, but use differences in the functions of components as the criterion for distinction. The words "include" and "including" mentioned throughout the specification and patent application are open terms and should be interpreted as "including but not limited to". The word "substantially" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. In addition, the word "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is described herein as being coupled to a second device, it means that the first device may be directly electrically connected to the second device, or may be indirectly electrically connected to the second device via other devices or connection means.

FIG. 1 is a schematic diagram showing a power supply 100 according to an embodiment of the present invention. For example, the power supply 100 can be applied to a desktop computer, a laptop computer, or an all-in-one computer. As shown in FIG. 1, the power supply 100 includes: a bridge rectifier 110, a voltage divider circuit 120, an adjustable capacitor element 130, a boost inductor LU, a power switch 140, an output stage circuit 150, a feedback compensation circuit 160, and a detection and control circuit 170. It should be noted that, although not shown in FIG. 1, the power supply 100 may further include other components, such as: a voltage regulator or (and) a negative feedback circuit.

The bridge rectifier 110 can generate a rectified potential VR according to a first input potential VIN1 and a second input potential VIN2, wherein an AC voltage with an arbitrary frequency and an arbitrary amplitude can be formed between the first input potential VIN1 and the second input potential VIN2. For example, the frequency of the AC voltage can be approximately 50 Hz or 60 Hz, and the root mean square (RMS) value of the AC voltage can be approximately between 90 V and 264 V, but is not limited thereto. The voltage divider circuit 120 can generate a first divided potential VD1 according to the rectified potential VR. The adjustable capacitor element 130 is used to store the rectified potential VR, wherein an equivalent capacitance value CE of the adjustable capacitor element 130 is determined according to a first control potential VC1 and a second control potential VC2. The boost inductor LU is coupled to the adjustable capacitance element 130. The power switch 140 can selectively couple the boost inductor LU to a common node NCM according to a pulse width modulation (PWM) potential VM. For example, if the pulse width modulation potential VM is a high logic level (i.e., logic "1"), the power switch 140 can couple the boost inductor LU to the common node NCM (i.e., the power switch 140 can be similar to a short circuit path); conversely, if the pulse width modulation potential VM is a low logic level (i.e., logic "0"), the power switch 140 will not couple the boost inductor LU to the common node NCM (i.e., the power switch 140 can be similar to an open circuit path). The output stage circuit 150 is coupled to the boost inductor LU and can be used to generate an output potential VOUT. For example, the output potential VOUT may be a DC potential, and its potential level may be between 18V and 20V, but is not limited thereto. The feedback compensation circuit 160 may generate a feedback potential VF and a capacitance potential VP according to the output potential VOUT. The detection and control circuit 170 may generate a pulse width modulation potential VM, a first control potential VC1, and a second control potential VC2 according to the first divided potential VD1, the feedback potential VF, and the capacitance potential VP. Under the design of the present invention, even if the power supply 100 operates in a high temperature environment, it can still automatically compensate for the non-ideal attenuation of the equivalent capacitance value CE, thereby improving the overall output stability.

The following embodiments will introduce the detailed structure and operation of the power supply 100. It must be understood that these drawings and descriptions are only examples and are not intended to limit the scope of the present invention.

FIG. 2 is a circuit diagram of a power supply 200 according to an embodiment of the present invention. In the embodiment of FIG. 2, the power supply 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes a bridge rectifier 210, a voltage divider circuit 220, an adjustable capacitor element 230, a boost inductor LU, a power switch 240, an output stage circuit 250, a feedback compensation circuit 260, and a detection and control circuit 270. The first input node NIN1 and the second input node NIN2 of the power supply 200 can receive a first input potential VIN1 and a second input potential VIN2 from an external input power source (not shown), respectively. The output node NOUT of the power supply 200 can be used to output an output potential VOUT to an electronic device (not shown).

The bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The first diode D1 has an anode and a cathode, wherein the anode of the first diode D1 is coupled to the first input node NIN1, and the cathode of the first diode D1 is coupled to a first node N1 to output a rectified potential VR. The second diode D2 has an anode and a cathode, wherein the anode of the second diode D2 is coupled to the second input node NIN2, and the cathode of the second diode D2 is coupled to the first node N1. The third diode D3 has an anode and a cathode, wherein the anode of the third diode D3 is coupled to a ground potential VSS (e.g., 0V), and the cathode of the third diode D3 is coupled to the first input node NIN1. The fourth diode D4 has an anode and a cathode, wherein the anode of the fourth diode D4 is coupled to the ground potential VSS, and the cathode of the fourth diode D4 is coupled to the second input node NIN2.

The voltage divider circuit 220 includes a first resistor R1 and a second resistor R2. The first resistor R1 has a first end and a second end, wherein the first end of the first resistor R1 is coupled to the first node N1 to receive the rectified potential VR, and the second end of the first resistor R1 is coupled to the second node N2 to output a first divided potential VD1. The second resistor R2 has a first end and a second end, wherein the first end of the second resistor R2 is coupled to the second node N2, and the second end of the second resistor R2 is coupled to the ground potential VSS.

The adjustable capacitance element 230 has an equivalent capacitance value CE and includes: a first transistor M1, a second transistor M2, a first capacitor C1, a second capacitor C2, and a third capacitor C3. For example, the first transistor M1 and the second transistor M2 can each be an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET). The first capacitor C1 has a first end and a second end, wherein the first end of the first capacitor C1 is coupled to the first node N1 to receive the rectified potential VR, and the second end of the first capacitor C1 is coupled to the ground potential VSS. The first transistor M1 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the first transistor M1 is used to receive a first control potential VC1, the first terminal of the first transistor M1 is coupled to a third node N3, and the second terminal of the first transistor M1 is coupled to the first node N1. The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C2 is coupled to the third node N3, and the second terminal of the second capacitor C2 is coupled to the ground potential VSS. The second transistor M2 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the second transistor M2 is used to receive a second control potential VC2, the first terminal of the second transistor M2 is coupled to a fourth node N4, and the second terminal of the second transistor M2 is coupled to the first node N1. The third capacitor C3 has a first terminal and a second terminal, wherein the first terminal of the third capacitor C3 is coupled to the fourth node N4, and the second terminal of the third capacitor C3 is coupled to the ground potential VSS. It should be noted that, according to different levels of the first control potential VC1 and the second control potential VC2, the second capacitor C2 and the third capacitor C3 can be selectively coupled in parallel with the first capacitor C1, thereby changing the equivalent capacitance value CE of the adjustable capacitance element 230.

The boost inductor LU has a first end and a second end, wherein the first end of the boost inductor LU is coupled to the first node N1, and the second end of the boost inductor LU is coupled to a fifth node N5.

The power switch 240 includes a third transistor M3. For example, the third transistor M3 may be an N-type metal oxide semi-conductor field effect transistor. The third transistor M3 has a control end (e.g., a gate), a first end (e.g., a source), and a second end (e.g., a drain), wherein the control end of the third transistor M3 is used to receive a pulse width modulation potential VM, the first end of the third transistor M3 is coupled to a common node NCM, and the second end of the third transistor M3 is coupled to the fifth node N5. For example, the common node NCM may provide a common potential, which may be regarded as another ground potential, and may be the same as or different from the aforementioned ground potential VSS.

The output stage circuit 250 includes a fifth diode D5 and a second capacitor C2. The fifth diode D5 has an anode and a cathode, wherein the anode of the fifth diode D5 is coupled to the fifth node N5, and the cathode of the fifth diode D5 is coupled to the output node NOUT. The fourth capacitor C4 has a first terminal and a second terminal, wherein the first terminal of the fourth capacitor C4 is coupled to the output node NOUT, and the second terminal of the fourth capacitor C4 is coupled to the common node NCM.

In some embodiments, the feedback compensation circuit 260 includes: a voltage regulator 262, a linear optical coupler 264, a fifth capacitor C5, a sixth capacitor C6, a third resistor R3, and a fourth resistor R4.

The third resistor R3 has a first end and a second end, wherein the first end of the third resistor R3 is coupled to the output node NOUT to receive the output potential VOUT, and the second end of the third resistor R3 is coupled to a sixth node N6 to output a second divided potential VD2. The fourth resistor R4 has a first end and a second end, wherein the first end of the fourth resistor R4 is coupled to the sixth node N6, and the second end of the fourth resistor R4 is coupled to the common node NCM. The fifth capacitor C5 has a first end and a second end, wherein the first end of the fifth capacitor C5 is coupled to a seventh node N7, and the second end of the fifth capacitor C5 is coupled to the sixth node N6.

In some embodiments, the voltage regulator 262 is implemented by a TL431 electronic component. Specifically, the voltage regulator 262 has an anode, a cathode, and a reference terminal, wherein the anode of the voltage regulator 262 is coupled to the common node NCM, the cathode of the voltage regulator 262 is coupled to the seventh node N7, and the reference terminal of the voltage regulator 262 is coupled to the sixth node N6.

In some embodiments, the linear optical coupler 264 is implemented by a PCX electronic component. In detail, the linear optical coupler 264 includes a light emitting diode DL and a bipolar junction transistor Q1 (e.g., NPN type). The light emitting diode DL has an anode and a cathode, wherein the anode of the light emitting diode DL is coupled to the output node NOUT, and the cathode of the light emitting diode DL is coupled to the seventh node N7. The bipolar junction transistor Q1 has a collector and an emitter, wherein the collector of the bipolar junction transistor Q1 is used to output a feedback potential VF, and the emitter of the bipolar junction transistor Q1 is coupled to an eighth node N8.

In addition, the sixth capacitor C6 has a first end and a second end, wherein the first end of the sixth capacitor C6 is coupled to the eighth node N8 to output a capacitance potential VP, and the second end of the sixth capacitor C6 is coupled to the ground potential VSS. It should be noted that the capacitance potential VP is associated with the aforementioned feedback potential VF. In some embodiments, the capacitance potential VP can be almost equal to the aforementioned feedback potential VF.

In some embodiments, the detection and control circuit 270 includes: an amplifier circuit 271, a first comparator 272, a second comparator 273, a first AND gate 274, a second AND gate 275, and a microcontroller unit (MCU) 276.

The amplifier circuit 271 can amplify the capacitance potential VP by a first gain factor K1 to generate a first amplified potential VA1. In addition, the amplifier circuit 271 can further amplify the capacitance potential VP by a second gain factor K2 to generate a second amplified potential VA2, wherein the first gain factor K1 is greater than the second gain factor K2. For example, the value of the first gain factor K1 can be between 5.5 and 6.5, and the value of the second gain factor K2 can be between 2.5 and 3.5, but is not limited thereto. In some embodiments, the amplifier circuit 271 can operate according to the following equations (1) and (2):

………………………………(1)

………………………………………(2) Wherein “VA1” represents the potential level of the first amplified potential VA1, “VA2” represents the potential level of the second amplified potential VA2, “VP” represents the potential level of the capacitor potential VP, “K1” represents the value of the first gain factor K1, and “K2” represents the value of the second gain factor K2.

The first comparator 272 has a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal of the first comparator 272 is used to receive the first amplified potential VA1, the negative input terminal of the first comparator 272 is used to receive the first divided potential VD1, and the output terminal of the first comparator 272 is used to output a first comparison potential VB1. For example, if the first divided potential VD1 is lower than or equal to the first amplified potential VA1, the first comparator 272 will be able to output the first comparison potential VB1 with a high logic level; conversely, if the first divided potential VD1 is higher than the first amplified potential VA1, the first comparator 272 will be able to output the first comparison potential VB1 with a low logic level.

The second comparator 273 has a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal of the second comparator 273 is used to receive the second amplified potential VA2, the negative input terminal of the second comparator 273 is used to receive the first divided potential VD1, and the output terminal of the second comparator 273 is used to output a second comparison potential VB2. For example, if the first divided potential VD1 is lower than or equal to the second amplified potential VA2, the second comparator 273 will be able to output the second comparison potential VB2 with a high logic level; conversely, if the first divided potential VD1 is higher than the second amplified potential VA2, the second comparator 273 will be able to output the second comparison potential VB2 with a low logic level.

The first AND gate 274 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first AND gate 274 is used to receive the first comparison potential VB1, the second input terminal of the first AND gate 274 is used to receive the first amplified potential VA1, and the output terminal of the first AND gate 274 is used to output a first logic potential VL1. For example, if the first comparison potential VB1 and the first amplified potential VA1 are both high logic levels, the first AND gate 274 will be able to output the first logic potential VL1 with a high logic level; conversely, if either the first comparison potential VB1 or the first amplified potential VA1 is a low logic level, the first AND gate 274 will be able to output the first logic potential VL1 with a low logic level.

The second AND gate 275 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second AND gate 275 is used to receive the second comparison potential VB2, the second input terminal of the second AND gate 275 is used to receive the second amplified potential VA2, and the output terminal of the second AND gate 275 is used to output a second logic potential VL2. For example, if the second comparison potential VB2 and the second amplified potential VA2 are both high logic levels, the second AND gate 275 will be able to output the second logic potential VL2 with a high logic level; conversely, if either the second comparison potential VB2 or the second amplified potential VA2 is a low logic level, the second AND gate 275 will be able to output the second logic potential VL2 with a low logic level.

The microcontroller 276 can generate a pulse width modulation potential VM, a first control potential VC1, and a second control potential VC2 according to the first logic potential VL1, the second logic potential VL2, and the feedback potential VF. In detail, the microcontroller 276 can operate in three different modes, which can be described in the following embodiments.

In some embodiments, if the first divided voltage VD1 is higher than the first amplified voltage VA1, it means that the temperature of the power supply 200 is generally normal. At this time, the first logic potential VL1 and the second logic potential VL2 are both low logic levels. Since the equivalent capacitance CE of the adjustable capacitor element 230 does not need to be adjusted, the microcontroller 276 can output the first control potential VC1 and the second control potential VC2 with low logic levels to simultaneously disable the first transistor M1 and the second transistor M2.

In other embodiments, if the first divided voltage VD1 is between the second amplified voltage VA2 and the first amplified voltage VA1, it means that the temperature of the power supply 200 is relatively high, and the capacitance value of the first capacitor C1 becomes smaller (non-ideal phenomenon). At this time, the first logic potential VL1 is a high logic level, and the second logic potential VL2 is a low logic level. In response, the microcontroller 276 will be able to output a first control potential VC1 with a high logic level to enable the first transistor M1, and can output a second control potential VC2 with a low logic level to disable the second transistor M2. Under this design, the second capacitor C2 can be coupled in parallel with the first capacitor C1, thereby increasing the equivalent capacitance value CE of the capacitor element 230.

In other embodiments, if the first divided voltage VD1 is lower than the second amplified voltage VA2, it means that the temperature of the power supply 200 is very high and the capacitance value of the first capacitor C1 becomes very small (a serious non-ideal phenomenon). At this time, the first logic potential VL1 and the second logic potential VL2 are both high logic levels. In response, the microcontroller 276 will be able to output the first control potential VC1 and the second control potential VC2 with high logic levels to enable the first transistor M1 and the second transistor M2 at the same time. Under this design, both the second capacitor C2 and the third capacitor C3 can be coupled in parallel with the first capacitor C1, thereby greatly increasing the equivalent capacitance value CE of the capacitor element 230.

In some embodiments, the microcontroller 276 may operate according to the following Table 1: Normal Mode High temperature mode Ultra high temperature mode The first voltage divider potential VD1 First logic potential VL1 Low logic level High logic level High logic level Second logic potential VL2 Low logic level Low logic level High logic level The first control potential VC1 Low logic level High logic level High logic level The second control potential VC2 Low logic level Low logic level High logic level Equivalent Capacitance CE Table 1: Different operating modes of microcontrollers

In some embodiments, the detection and control circuit 270 further includes a fourth transistor M4 and a fifth resistor R5. For example, the fourth transistor M4 may be an N-type metal oxide semi-conductor field effect transistor. The fourth transistor M4 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control degree of the fourth transistor M4 is used to receive the second control potential VC2, the first terminal of the fourth transistor M4 is coupled to the ground potential VSS, and the second terminal of the fourth transistor M4 is coupled to a ninth node N9. The fifth resistor R5 has a first terminal and a second terminal, wherein the first terminal of the fifth resistor R5 is coupled to the ninth node N9, and the second terminal of the fifth resistor R5 is coupled to the sixth node N6. The microcontroller 276 can also indirectly monitor the second divided voltage VD2 at the sixth node N6. If the second control potential VC2 is a high logic level, the fourth transistor M4 will be enabled to quickly pull down the second divided voltage VD2. In addition, the microcontroller 276 can also calculate how many times the second divided voltage VD2 has been pulled down in total. In some embodiments, if the second divided voltage VD2 is pulled down a predetermined number of times (for example, 5 times), the microcontroller 276 can also automatically cut off its power supply to protect the power supply 200 from accidental damage to its internal components due to too many high temperature times, but it is not limited to this.

The present invention proposes a novel power supply. According to actual measurement results, even when operating in a high temperature environment, the power supply using the above-mentioned design can still effectively improve the overall output stability, so it is very suitable for application in various types of devices.

It is worth noting that the potential, current, resistance, inductance, capacitance, and other component parameters described above are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The power supply of the present invention is not limited to the state shown in Figures 1-2. The present invention may only include any one or more features of any one or more embodiments of Figures 1-2. In other words, not all of the features shown in the diagram need to be implemented in the power supply of the present invention at the same time. Although the embodiments of the present invention use metal oxide semi-conductor field effect transistors as an example, the present invention is not limited to this. People in the technical field can use other types of transistors, such as junction field effect transistors, or fin field effect transistors, etc., without affecting the effect of the present invention.

Ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., have no sequential relationship with each other, and are only used to mark and distinguish two different components with the same name.

Although the present invention is disclosed as above with the preferred embodiments, it is not intended to limit the scope of the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached patent application.

100,200: Power supply 110,210: Bridge rectifier 120,220: Voltage divider circuit 130,230: Adjustable capacitor element 140,240: Power switch 150,250: Output stage circuit 160,260: Feedback compensation circuit 170,270: Detection and control circuit 262: Voltage regulator 264: Linear optocoupler 271: Amplifier circuit 272: First comparator 273: Second comparator 274: First AND gate 275: Second AND gate 276: Microcontroller C1: First capacitor C2: Second capacitor C3: Third capacitor C4: Fourth capacitor C5: Fifth capacitor C6: Sixth capacitor CE: Equivalent capacitance D1: First diode D2: Second diode D3: Third diode D4: Fourth diode D5: Fifth diode DL: Light-emitting diode K1: First gain factor K2: Second gain factor LU: Boost inductor M1: First transistor M2: Second transistor M3: Third transistor M4: Fourth transistor N1: First node N2: Second node N3: Third node N4: Fourth node N5: Fifth node N6: Sixth node N7: Seventh node N8: Eighth node N9: Ninth node NCM: Common node NIN1: First input node NIN2: Second input node NOUT: Output node Q1: bipolar junction transistor R1: first resistor R2: second resistor R3: third resistor R4: fourth resistor R5: fifth resistor VA1: first amplifier potential VA2: second amplifier potential VB1: first comparison potential VB2: second comparison potential VC1: first control potential VC2: first control potential VD1: first voltage division potential VD2: second voltage division potential VF: feedback potential VIN1: first input potential VIN2: second input potential VL1: first logic potential VL2: second logic potential VM: pulse width modulation potential VOUT: output potential VP: capacitor potential VR: rectifier potential VSS: ground potential

FIG. 1 is a schematic diagram showing a power supply according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a power supply according to an embodiment of the present invention.

100: Power supply

110: Bridge rectifier

120: Voltage divider circuit

130: Adjustable capacitor element

140: Power switch

150: Output stage circuit

160: Feedback compensation circuit

170: Detection and control circuit

CE: equivalent capacitance value

LU:Boost Inductor

NCM: Common Node

VC1: first control potential

VC2: first control potential

VD1: first voltage divider potential

VF: Feedback potential

VIN1: first input potential

VIN2: Second input potential

VM: Pulse Width Modulation Potential

VOUT: output voltage

VP: Capacitor potential

VR: Rectification potential

Claims (10)

A power supply with high output stability, comprising: A bridge rectifier, generating a rectified potential according to a first input potential and a second input potential; A voltage divider circuit, generating a first divided potential according to the rectified potential; An adjustable capacitance element, storing the rectified potential, wherein an equivalent capacitance value of the adjustable capacitance element is determined according to a first control potential and a second control potential; A boost inductor, coupled to the adjustable capacitance element; A power switch, selectively coupling the boost inductor to a common node according to a pulse width modulation potential; An output stage circuit, coupled to the boost inductor, and generating an output potential; A feedback compensation circuit generates a feedback potential and a capacitance potential according to the output potential; and a detection and control circuit generates the pulse width modulation potential, the first control potential, and the second control potential according to the first divided potential, the feedback potential, and the capacitance potential. A power supply as described in claim 1, wherein the bridge rectifier comprises: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; A third diode having an anode and a cathode, wherein the anode of the third diode is coupled to a ground potential, and the cathode of the third diode is coupled to the first input node; and A fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node. A power supply as described in claim 2, wherein the voltage divider circuit comprises: a first resistor having a first end and a second end, wherein the first end of the first resistor is coupled to the first node to receive the rectified potential, and the second end of the first resistor is coupled to a second node to output the first divided potential; and a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the second node, and the second end of the second resistor is coupled to the ground potential. A power supply as described in claim 2, wherein the adjustable capacitance element comprises: A first capacitor having a first end and a second end, wherein the first end of the first capacitor is coupled to the first node to receive the rectified potential, and the second end of the first capacitor is coupled to the ground potential; A first transistor having a control end, a first end, and a second end, wherein the control end of the first transistor is used to receive the first control potential, the first end of the first transistor is coupled to a third node, and the second end of the first transistor is coupled to the first node; A second capacitor having a first end and a second end, wherein the first end of the second capacitor is coupled to the third node, and the second end of the second capacitor is coupled to the ground potential; A second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is used to receive the second control potential, the first terminal of the second transistor is coupled to a fourth node, and the second terminal of the second transistor is coupled to the first node; and A third capacitor having a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the fourth node, and the second terminal of the third capacitor is coupled to the ground potential; wherein the boost inductor has a first terminal and a second terminal, the first terminal of the boost inductor is coupled to the first node, and the second terminal of the boost inductor is coupled to a fifth node. A power supply as described in claim 4, wherein the power switch comprises: A third transistor having a control end, a first end, and a second end, wherein the control end of the third transistor is used to receive the pulse width modulation potential, the first end of the third transistor is coupled to the common node, and the second end of the third transistor is coupled to the fifth node. A power supply as described in claim 4, wherein the output stage circuit comprises: a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the fifth node, and the cathode of the fifth diode is coupled to an output node to output the output potential; and a fourth capacitor having a first end and a second end, wherein the first end of the fourth capacitor is coupled to the output node, and the second end of the fourth capacitor is coupled to the common node. A power supply as described in claim 6, wherein the feedback compensation circuit includes: a third resistor having a first end and a second end, wherein the first end of the third resistor is coupled to the output node to receive the output potential, and the second end of the third resistor is coupled to a sixth node to output a second divided voltage potential; a fourth resistor having a first end and a second end, wherein the first end of the fourth resistor is coupled to the sixth node, and the second end of the fourth resistor is coupled to the common node; a fifth capacitor having a first end and a second end, wherein the first end of the fifth capacitor is coupled to a seventh node, and the second end of the fifth capacitor is coupled to the sixth node; A voltage regulator having an anode, a cathode, and a reference terminal, wherein the anode of the voltage regulator is coupled to the common node, the cathode of the voltage regulator is coupled to the seventh node, and the reference terminal of the voltage regulator is coupled to the sixth node; A linear optical coupler includes a light-emitting diode and a bipolar junction transistor, wherein the light-emitting diode has an anode and a cathode, the anode of the light-emitting diode is coupled to the output node, the cathode of the light-emitting diode is coupled to the seventh node, the bipolar junction transistor has a collector and an emitter, the collector of the bipolar junction transistor is used to output the feedback potential, and the emitter of the bipolar junction transistor is coupled to an eighth node; and a sixth capacitor, having a first end and a second end, wherein the first end of the sixth capacitor is coupled to the eighth node to output the capacitance potential, and the second end of the sixth capacitor is coupled to the ground potential. A power supply as described in claim 1, wherein the detection and control circuit comprises: an amplifier circuit, which amplifies the capacitance potential by a first gain factor to generate a first amplified potential, and amplifies the capacitance potential by a second gain factor to generate a second amplified potential, wherein the first gain factor is greater than the second gain factor; a first comparator, having a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal of the first comparator is used to receive the first amplified potential, the negative input terminal of the first comparator is used to receive the first divided potential, and the output terminal of the first comparator is used to output a first comparison potential; and A second comparator has a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal of the second comparator is used to receive the second amplified potential, the negative input terminal of the second comparator is used to receive the first divided potential, and the output terminal of the second comparator is used to output a second comparison potential. A power supply as described in claim 8, wherein the detection and control circuit further comprises: a first AND gate having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first AND gate is used to receive the first comparison potential, the second input terminal of the first AND gate is used to receive the first amplified potential, and the output terminal of the first AND gate is used to output a first logic potential; and a second AND gate having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second AND gate is used to receive the second comparison potential, the second input terminal of the second AND gate is used to receive the second amplified potential, and the output terminal of the second AND gate is used to output a second logic potential. A power supply as described in claim 9, wherein the detection and control circuit further comprises: A microcontroller, which generates the pulse width modulation potential, the first control potential, and the second control potential according to the first logic potential, the second logic potential, and the feedback potential; wherein if the first divided potential is higher than the first amplified potential, the first control potential and the second control potential are both low logic levels; wherein if the first divided potential is between the second amplified potential and the first amplified potential, the first control potential is a high logic level and the second control potential is a low logic level; wherein if the first divided potential is lower than the second amplified potential, the first control potential and the second control potential are both high logic levels.

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