CN118818244A - Fault detection method for measuring machine and semiconductor chip - Google Patents

Abstract

A measuring machine comprises a cavity, a development board, a probe station, a microscope, a circuit board and two probes. The development plate is positioned outside the cavity. The probe station is located in the cavity. The microscope is located within the cavity and above the probe station. The circuit board is positioned on the probe platform and is configured to be electrically connected with the semiconductor chip and the development board, wherein the semiconductor chip is positioned under the lens of the microscope. The two probes are located above the probe station and configured to contact the semiconductor chip. In the fault detection method of the measuring machine and the semiconductor chip, a development board is used as a source of measuring signals, and a clock generator in the development board can generate signals with higher speed, so that more abnormal hot spots can be found in physical fault analysis. The abnormal hot spots can be observed by a microscope, the temperature of the abnormal hot spots is measured by a probe, the operation mode is simple, and the possible failure area of the semiconductor chip during operation can be more effectively found out compared with the traditional method.

Description

Fault detection method for measuring machine and semiconductor chip

Technical Field

The present disclosure relates to a measuring machine and a semiconductor chip fault detection method.

Background Art

The demand for mobile phones, computers and tablet computers has grown rapidly in recent years, causing a sharp increase in consumer demand for memory. In these electronic devices, dynamic random access memory (DRAM) plays a very important role as a bridge between the central processing unit (CPU) and flash memory. Therefore, the signal integrity of the dynamic random access memory must meet the requirements of the system, otherwise the above-mentioned electronic devices will not be able to operate.

Usually when doing fault analysis tests on memory chips, there is a test link that uses a test machine (such as MOSAID test machine) with a cavity (such as THEMOS, PHEMOS, etc.) to perform physical failure analysis (PFA) to find out the abnormal temperature rise phenomenon of the memory chip under high-speed operation. However, the test rate of the current test machine is about 416 megabytes per second, which is lower than the speed of normal memory operation. For physical failure analysis of abnormal hot spots, the higher the data transmission speed, the more abnormal hot spots can be found.

Summary of the invention

A technical aspect of the present disclosure is a measuring machine.

According to one embodiment of the present disclosure, a measuring machine includes a cavity, a development board, a probe station, a microscope, a circuit board, and two probes. The development board is located outside the cavity. The probe station is located in the cavity. The microscope is located in the cavity and above the probe station. The circuit board is located on the probe station and is configured to electrically connect a semiconductor chip and the development board, wherein the semiconductor chip is located directly below the lens of the microscope. The two probes are located above the probe station and are configured to contact the semiconductor chip.

In one embodiment of the present disclosure, the measuring machine further comprises a cable, which extends from the circuit board in the cavity to the development board outside the cavity, and the cable electrically connects the development board and the circuit board.

In one embodiment of the present disclosure, the measuring machine further comprises a slot. The slot is located on the circuit board and electrically connected to the circuit board, and the slot is configured for inserting a semiconductor chip.

In one embodiment of the present disclosure, the slot is vertically aligned with the lens of the microscope.

In one embodiment of the present disclosure, the two probes are temperature probes.

Another technical aspect of the present disclosure is a method for detecting a fault in a semiconductor chip.

According to one embodiment of the present disclosure, a fault detection method for a semiconductor chip includes electrically connecting the semiconductor chip to a circuit board; placing the circuit board on a probe station in a cavity, wherein a microscope is located in the cavity and above the probe station, and the semiconductor chip is located directly below the lens of the microscope; electrically connecting the circuit board to a development board via a cable, wherein the development board is located outside the cavity; using the development board to provide an inspection signal to the semiconductor chip; locating the positions of two probes according to an image of the semiconductor chip obtained by the microscope, wherein the two probes are located above the probe station; and using the two probes to measure a measurement signal for the semiconductor chip.

In one embodiment of the present disclosure, the semiconductor chip fault detection method further includes opening a cover of the semiconductor chip before electrically connecting the semiconductor chip to the development board.

In one embodiment of the present disclosure, the semiconductor chip fault detection method further includes inserting the semiconductor chip into a socket, wherein the socket is electrically connected to a circuit board.

In one embodiment of the present disclosure, locating the positions of the two probes according to an image of the semiconductor chip obtained by a microscope includes observing at least one hot spot of the semiconductor chip using a microscope; and locating the positions of the two probes according to the hot spot in the image observed by the microscope.

In one embodiment of the present disclosure, using two probes to measure a measurement signal on a semiconductor chip includes using two probes to measure a temperature of a hot spot.

In the above-mentioned embodiments of the present disclosure, since a development board is used as a source of measurement signals in the fault detection method of the measuring machine and the semiconductor chip, the clock generator in the development board can generate faster signals, so more abnormal hot spots can be found in the physical property fault analysis. These abnormal hot spots can be observed through a microscope and their temperatures can be measured by a probe. The operation is simple and can more effectively find out the possible failure areas when the semiconductor chip is operating than the traditional method.

BRIEF DESCRIPTION OF THE DRAWINGS

The aspects of the present disclosure are best understood from the following embodiments when read in conjunction with the accompanying drawings. Note that various features are not drawn to scale in accordance with standard practice in this industry. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic diagram of a measuring machine according to an embodiment of the present disclosure.

FIG. 2 is a side view of the vicinity of a lens of a microscope when the measuring machine of FIG. 1 is in use.

FIG. 3 is a flow chart of a semiconductor chip failure detection method according to an embodiment of the present disclosure.

FIG. 4 is a schematic diagram of the semiconductor chip in FIG. 2 before the cover is opened.

FIG. 5 is a schematic diagram showing the semiconductor chip in FIG. 4 after the cover is opened.

FIG. 6 is a partially enlarged top view of the semiconductor chip in FIG. 2 after the cover is opened.

DETAILED DESCRIPTION

The following disclosed embodiments provide many different embodiments, or examples, for implementing the different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these examples are only examples and are not intended to be limiting. In addition, the present invention may repeat element symbols and/or letters in each example. This repetition is used for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and/or configurations discussed.

Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for descriptive purposes to describe the relationship of one element or feature to another element or feature as illustrated in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation illustrated in the accompanying drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

FIG. 1 is a schematic diagram of a measuring machine 100 according to an embodiment of the present disclosure. FIG. 2 is a side view of the vicinity of the lens 142 of the microscope 140 when the measuring machine 100 of FIG. 1 is in use. Referring to FIG. 1 and FIG. 2, the measuring machine 100 includes a cavity 110, a development board 120, a probe station 130, a microscope 140, a circuit board 150, and two probes 160a, 160b. The development board 120 is located outside the cavity 110. The probe station 130 is located inside the cavity 110. The microscope 140 is located inside the cavity 110 and above the probe station 130. The circuit board 150 is located on the probe station 130 and is electrically connected to the development board 120. When measuring the semiconductor chip 170, the circuit board 150 can be electrically connected to the semiconductor chip 170, and the semiconductor chip 170 is located directly below the lens 142 of the microscope 140. Two probes 160a and 160b are located above the probe station 130, and the two probes 160a and 160b are configured to contact the semiconductor chip 170. Through the above configuration, the circuit board 150 and the semiconductor chip 170 are located in the cavity 110. The circuit board 150 and the development board 120 are electrically connected through the cable 190, and the cable 190 extends from the circuit board 150 in the cavity 110 to the development board 120 outside the cavity 110.

The measuring machine 100 further includes a slot 180. The slot 180 is located on the circuit board 150 and is electrically connected to the circuit board 150. The slot 180 is configured for inserting the semiconductor chip 170. Depending on the different semiconductor chips 170, there will be different slots 180 for inserting the semiconductor chip 170. For example, when the semiconductor chip is a fourth-generation double data rate synchronous dynamic random access memory (Double Data Rate Fourth-generation Synchronous DRAM, DDR4 SDRAM), there will be a slot 180 dedicated to this type of semiconductor chip 170. In addition, there will be undefined pins on the development board 120. Before the measurement starts, these undefined pins will be defined through the human-machine interface in the development board 120 to correspond to the pins of the semiconductor chip 170, and then the development board 120 and the semiconductor chip 170 will be electrically connected through the circuit board 150 and the cable 190. In some embodiments, the slot 180 is aligned with the lens 142 of the microscope 140 in a vertical direction.

In some embodiments, the two probes 160a and 160b are temperature probes that can measure the temperature of an abnormal hot spot (refer to FIG. 6 ) generated by the semiconductor chip 170 under high-speed operation. When in use, the probe (such as the probe 160a) is used to contact an abnormal hot spot, or an area suspected of being an abnormal hot spot, to obtain its temperature signal to determine whether it is overheated. When measuring, since the brightness and temperature of the abnormal hot spot are easily affected by the surrounding environment, and the development board 120 itself has a light source, and the development board 120 may generate heat source interference during operation, the development board 120 is placed outside the cavity 110, and then electrically connected to the semiconductor chip 170 through the cable 190, the circuit board 150 and the slot 180, the interference from the light source and heat source of the development board 120 can be isolated, and the accuracy of observing the abnormal hot spot of the semiconductor chip 170 can be improved.

It should be understood that the connection relationship, materials and functions of the components described above will not be repeated, but will be described first. In the following description, a method for detecting a semiconductor chip failure using the measuring machine 100 will be described.

FIG3 illustrates a flow chart of a fault detection method for a semiconductor chip according to an embodiment of the present disclosure. Referring to FIG3 , the fault detection method for a semiconductor chip includes the following steps: First, in step S1, the semiconductor chip is electrically connected to a circuit board. Then, in step S2, the circuit board is placed on a probe station in a cavity, wherein a microscope is located in the cavity and above the probe station, and the semiconductor chip is located directly below the lens of the microscope. Then, in step S3, the circuit board is electrically connected to a development board via a cable, wherein the development board is located outside the cavity. Next, in step S4, the development board is used to provide an inspection signal to the semiconductor chip. Then, in step S5, the positions of the two probes are located according to the image obtained by the microscope of the semiconductor chip, wherein the two probes are located above the probe station. And finally, in step S6, the measurement signal of the semiconductor chip is measured using two probes.

In some embodiments, the semiconductor chip fault detection method is not limited to the above steps S1 to S6. For example, each of steps S1 to S6 may include other more detailed steps. In some embodiments, steps S1 to S6 may further include other steps between two previous and next steps, or may further include other steps before step S1 and further include other steps after step S6. In the following description, the above steps will be described in detail.

FIG4 is a schematic diagram of the semiconductor chip 170 of FIG2 before the cover is opened. FIG5 is a schematic diagram of the semiconductor chip 170 of FIG4 after the cover is opened. Referring to FIG2, FIG4 and FIG5, before the semiconductor chip 170 is electrically connected to the development board 120, the semiconductor chip 170 will be first decapped, and at least the packaging glue on the top 174 of the semiconductor chip 170 (as shown in FIG4 The portion above the dotted line) is stripped off to expose the internal circuit. This decapping step can be performed by dry etching or wet etching, but is not limited to this. The semiconductor chip 170 after the cover is opened will then be inserted into the socket 180, wherein the socket 180 is electrically connected to the circuit board 150. In this way, the semiconductor chip 170 is electrically connected to the circuit board 150.

1 and 2, then, the circuit board 150 is placed on the probe station 130 in the cavity 110, wherein the microscope 140 is located in the cavity 110 and above the probe station 130, and the semiconductor chip 170 is located directly below the lens 142 of the microscope 140. Then, the circuit board 150 is electrically connected to the development board 120 through the cable 190, wherein the development board 120 is located outside the cavity 110. In this way, the semiconductor chip 170 is electrically connected to the development board 120 through the cable 190, the circuit board 150 and the slot 180. In the next step, the development board 120 can be used to provide an inspection signal to the semiconductor chip 170.

Referring to FIG. 1 , FIG. 2 and FIG. 6 , the positions of the two probes 160 a and 160 b are then located according to the image obtained by the microscope 140 of the semiconductor chip 170 , wherein the two probes 160 a and 160 b are located above the probe station 130 . This step is to use the microscope 140 to observe the hot spots 172 a and 172 b of the semiconductor chip 170 , and to locate the positions of the two probes 160 a and 160 b respectively according to the hot spots 172 a and 172 b in the image observed by the microscope 140 . The above-mentioned “positioning” may mean moving the probes 160 a and 160 b to positions where they can contact the hot spots 172 a and 172 b respectively. After locating the positions of the two probes 160 a and 160 b, the two probes 160 a and 160 b may be used to measure measurement signals. This measurement signal is, for example, a temperature signal of the hot spots 172 a and 172 b. By measuring the temperature signals of the hot spots 172 a and 172 b, the failure location near the hot spots 172 a and 172 b may be found.

Since the development board is used as the source of the measurement signal in the fault detection method of the measuring machine and semiconductor chip, the clock generator in the development board can generate faster signals, so more abnormal hot spots can be found in the physical property failure analysis. These abnormal hot spots can be observed through a microscope and their temperature can be measured by a probe. The operation is simple and can more effectively find the possible failure area when the semiconductor chip is operating than the traditional method.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and/or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

【Explanation of symbols】

100: Measuring machine

110: Cavity

120: Development Board

130: Probe Station

140: Microscope

142: Lens

150: Circuit board

160a, 160b: Probe

170: Semiconductor Chip

172a, 172b: Hotspot

174: Top

180: Slot

190: Cable

S1, S2, S3, S4, S5, S6: steps.

Claims (10)

1. A measuring machine, comprising: Cavity; a development board, located outside the cavity; a probe station, located in the cavity; A microscope, located in the cavity and above the probe station; a circuit board, located on the probe station, configured to electrically connect a semiconductor chip and the development board, wherein the semiconductor chip is located directly below the lens of the microscope; and Two probes are located above the probe station and are configured to contact the semiconductor chip. 2. The measuring machine according to claim 1, further comprising: A cable extends from the circuit board in the cavity to the development board outside the cavity and electrically connects the development board and the circuit board. 3. The measuring machine according to claim 1, further comprising: The slot is located on the circuit board and electrically connected to the circuit board. The slot is configured for the semiconductor chip to be inserted. 4 . The measuring machine according to claim 3 , wherein the slot is vertically aligned with the lens of the microscope. 5 . The measuring machine according to claim 1 , wherein the two probes are temperature probes. 6. A semiconductor chip fault detection method, comprising: electrically connecting the semiconductor chip to the circuit board; The circuit board is placed on a probe station in a cavity, wherein a microscope is located in the cavity and above the probe station, and the semiconductor chip is located directly below a lens of the microscope; The circuit board is electrically connected to a development board via a cable, wherein the development board is located outside the cavity; Using the development board to provide a check signal to the semiconductor chip; Positioning two probes according to the image of the semiconductor chip obtained by the microscope, wherein the two probes are located above the probe station; and A measurement signal is measured on the semiconductor chip using the two probes. 7. The semiconductor chip fault detection method according to claim 6, further comprising: Before the semiconductor chip is electrically connected to the development board, the semiconductor chip is uncovered. 8. The semiconductor chip fault detection method according to claim 6, further comprising: The semiconductor chip is inserted into a socket, wherein the socket is electrically connected to the circuit board. 9. The semiconductor chip fault detection method according to claim 6, wherein locating the positions of the two probes according to the image of the semiconductor chip obtained by the microscope comprises: Observing at least one hot spot of the semiconductor chip using the microscope; and The positions of the two probes are located according to the hot spots in the image observed by the microscope. 10 . The semiconductor chip fault detection method according to claim 9 , wherein using the two probes to measure the measurement signal on the semiconductor chip comprises using the two probes to measure the temperature of the hot spot.