TWI870665B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device includes a circuit board, a bottom plate, a plurality of landing pads, a stack, a plurality of support pillars, and a plurality of memory pillars. The circuit board includes a plurality of circuit structures and a plurality of wires, the circuit structures are electrically connected to the corresponding wires, and the circuit board has a peripheral area, an array area and a staircase area disposed between the peripheral area and the array area. The bottom plate is disposed over the circuit board, and the bottom plate includes a bottom conductive layer. The landing pads are embedded in at least a top portion of the bottom conductive layer and contact the bottom conductive layer in the staircase area. The stack is disposed on the bottom plate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked along a first direction. The support pillars pass through the stack along the first direction in the staircase area and extend to the landing pads. The memory pillars pass through the stack along the first direction in the array area.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a memory device and a manufacturing method thereof.

Recently, as the demand for better memory devices has gradually increased, various three-dimensional (3D) memory devices, such as three-dimensional NAND (3D NAND) memory devices having a multi-layer stacked structure, have been provided. Such three-dimensional memory devices can achieve higher storage capacity and have better electrical characteristics, such as good data retention reliability and operation speed.

The conventional 3D NAND memory device has a very complicated manufacturing process. Therefore, how to simplify the manufacturing process of the 3D NAND memory device is still the focus of current research.

The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor device and a manufacturing method thereof with a more simplified manufacturing process.

According to an embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a circuit board, a base plate, a plurality of landing pads, a stack, a plurality of support pillars, and a plurality of memory pillars. The circuit board includes a plurality of circuit structures and a plurality of wires, the circuit structures are electrically connected to the corresponding wires, and the circuit board has a peripheral area, an array area, and a step area arranged between the peripheral area and the array area. The base plate is arranged on the circuit board, and the base plate includes a bottom conductive layer. The landing pad is embedded in at least a top portion of the bottom conductive layer in the step area and contacts the bottom conductive layer. The stack is arranged on the bottom plate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked along a first direction. The support column passes through the stack along the first direction in the step area and extends to the landing pad. The memory column passes through the stack along the first direction in the array area.

According to another embodiment of the present invention, a method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device includes the following steps. First, a circuit board is formed, the circuit board includes a plurality of circuit structures and a plurality of wires, the circuit structures are electrically connected to the corresponding wires, and the circuit board has a peripheral area, an array area, and a step area arranged between the peripheral area and the array area. Secondly, a base plate is formed, the base plate is arranged on the circuit board, and the base plate includes a bottom conductive layer. A plurality of landing pads are formed, and the landing pads are embedded in at least a top portion of the bottom conductive layer in the step area and contact the bottom conductive layer. A stack is formed, the stack is disposed on a base plate, the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked along a first direction. A plurality of support pillars are formed, the support pillars pass through the stack along the first direction in the step region and extend to the landing pad. Thereafter, a plurality of memory pillars are formed, the memory pillars pass through the stack along the first direction in the array region.

In order to better understand the above and other aspects of the present invention, the following embodiments are specifically described in detail with reference to the accompanying drawings:

In the detailed description below, various specific details are provided for ease of explanation to provide an overall understanding of the embodiments of the present disclosure. However, it should be understood that one or more embodiments can be implemented without using these specific details. In other cases, known structures and components are shown in schematic diagrams to simplify the drawings.

Generally speaking, the manufacturing method of a three-dimensional inversion memory device includes a gate replacement process. Since multiple sacrificial layers are removed in the gate replacement process, support pillars need to be set in the step region to maintain the stability of the overall structure. In some comparative examples, the support pillars set in the step region are formed by an independent process, such as forming an oxide pillar that passes through the stacked structure. According to an embodiment of the present case, the formation of the support pillars can be integrated into the process of other components (such as the formation of vertical contacts in the peripheral area), so compared to the comparative example in which the support pillars are formed by an independent process, the manufacturing method of the memory device of the present case can save more time and money costs.

FIG. 1 to FIG. 17B illustrate a manufacturing flow chart of a semiconductor device 10 according to an embodiment of the present invention. Among them, FIG. 1 to FIG. 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A and 17A correspond to a plane formed by a first direction (e.g., Z direction) and a second direction (e.g., X direction). FIG. 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B and 17B correspond to a plane formed by a first direction (e.g., Z direction) and a third direction (e.g., Y direction). The first direction, the second direction and the third direction may be different from each other, may be staggered with each other, for example, perpendicular to each other.

Please refer to FIG. 1, which shows a schematic diagram of forming a circuit board 110. The steps of forming the circuit board 110 include providing a substrate 112, forming a plurality of circuit structures 114 and a plurality of wires 116 on the substrate 112, and forming an insulating material 118 covering the substrate 112, the circuit structures 114 and the wires 116. The wires 116 are electrically connected to the corresponding circuit structures 114. The circuit structures 114 include metal oxide semiconductors (CMOS). The insulating material 118 may include oxide. The circuit board 110 corresponds to the peripheral area PA, the step area SA and the array area AA, and the step area SA is arranged between the peripheral area PA and the array area AA.

Please refer to FIG. 2, which shows a schematic diagram of forming the bottom plate 120 on the circuit board 110. For example, a first conductive layer 121, a first insulating layer 123, a second conductive layer 125, a second insulating layer 127, and a third conductive layer 129 may be sequentially formed on the circuit board 110 in a first direction (e.g., Z direction) by multiple deposition processes. That is, the bottom plate 120 may include the first conductive layer 121, the first insulating layer 123, the second conductive layer 125, the second insulating layer 127, and the third conductive layer 129. In the present embodiment, the materials of the first conductive layer 121, the second conductive layer 125, and the third conductive layer 129 may include polysilicon. The materials of the first insulating layer 123 and the second insulating layer 127 may include oxides. It should be understood that the present invention is not limited thereto.

Referring to FIG. 3 , the first conductive layer 121, the second conductive layer 125, and the third conductive layer 129 are removed at predetermined positions by an etching process to form a plurality of openings, and then an insulating material is filled in the openings to form a plurality of bottom support members 122 in the step area SA. The bottom support member 122 may be made of an insulating material, and the insulating material may include an oxide. In the step area SA, the bottom support member 122 passes through the first conductive layer 121, the second conductive layer 125, and the third conductive layer 129 in the first direction.

4 , a plurality of top openings 124p are formed in the top portion of the third conductive layer 129 in the step region SA. Each top opening 124p is partially recessed in the third conductive layer 129 without exposing the upper surface of the second insulating layer 127. The top openings 124p are separated from each other, for example, adjacent top openings 124p may be separated from each other by at least a portion of the bottom support member 122.

5 , a plurality of through openings 126p are formed in the step area SA through the first conductive layer 121, the first insulating layer 123, the second conductive layer 125, the second insulating layer 127 and the third conductive layer 129 (i.e. through the bottom plate 120). Each through opening 126p exposes the upper surface of the corresponding conductive line 116. The through openings 126p are separated from each other.

Referring to FIG. 6 , a conductive material is filled into the top opening 124p and the through opening 126p by at least one deposition process, and a planarization process is performed to form a plurality of landing pads 124 and a plurality of discharge pillars 126, respectively. That is, the landing pads 124 are embedded in at least the top portion of the third conductive layer 129, and adjacent landing pads 124 are separated from each other by at least a portion of the bottom support 122. The top surface of the landing pad 124 is substantially coplanar with the top surface of the discharge pillar 126. The discharge column 126 passes through the first conductive layer 121, the first insulating layer 123, the second conductive layer 125, the second insulating layer 127 and the third conductive layer 129 and is electrically connected to the corresponding wire 116. The discharge column 126 can be used to discharge the charge accumulated in the process. The landing pad 124 can provide a better etching selectivity in a subsequent etching process (described in detail below).

Please refer to FIGS. 7A and 7B simultaneously, a stacked structure 130' is formed on the bottom plate 120 (i.e., on the third conductive layer 129). The steps of forming the stacked structure 130' include forming a plurality of insulating layers 132 and a plurality of sacrificial layers 135 alternately stacked in a first direction (i.e., the Z direction) by a plurality of deposition processes. The bottommost layer of the stacked structure 130' is, for example, an insulating layer 132. The material of the insulating layer 132 may include oxide, and the material of the sacrificial layer 135 may include nitride. After forming the stacked structure 130', a plurality of memory pillars MP are formed in the array area AA through the stacked structure 130' and through a portion of the first conductive layer 121 of the base plate 120. Each memory pillar MP may include a memory layer 136, a channel layer 138, an insulating pillar 140, and a pad 142. The channel layer 138 surrounds the insulating pillar 140 and covers the bottom surface of the insulating pillar 140. The memory layer 136 surrounds the channel layer 138 and covers the bottom surface of the channel layer 138. The pad 142 is disposed on the channel layer 138 and electrically contacts the channel layer 138. After forming the memory pillars MP, a plurality of top isolation members SSLC extending along the second direction (e.g., the X direction) are formed. The top isolation members SSLC pass through the top portion of the stacked structure 130' along the first direction (e.g., the Z direction). After the top isolation members SSLC are formed, the sacrificial layer 135 of the step area SA is patterned so that the sacrificial layer 135 of the step area SA becomes a step-shaped structure to expose the predetermined position of the landing area of the word line. Thereafter, an insulating material 144 is covered on the step-shaped structure formed by the sacrificial layer 135.

In one embodiment, the material of the memory layer 136 may include a tunneling layer, a charge trapping layer, and a blocking layer. The tunneling layer may include silicon oxide, or a silicon oxide/silicon nitride combination (e.g., Oxide/Nitride/Oxide or ONO). The charge trapping layer may include silicon nitride (SiN) or other materials capable of trapping charges. The blocking layer may include silicon oxide, aluminum oxide, and/or a combination of these materials. The material of the channel layer 138 and the pad 142 may include polysilicon. The material of the insulating pillar 140 and the top isolation member SSLC may include oxide.

8A and 8B, a plurality of first openings 150p and a plurality of second openings 160p are formed in the step area SA and the peripheral area PA respectively, passing through the stack structure 130' along the first direction. In the step area SA, the first opening 150p exposes the corresponding landing pad 124 (at least the top portion of the third conductive layer 129 embedded in the bottom plate 120). In the peripheral area PA, the second opening 160p exposes the corresponding wire 116 of the circuit board 110. The first opening 150p and the second opening 160p are formed, for example, by an etching process (e.g., dry etching).

Referring to FIGS. 9A and 9B , a first liner 1521 and a second liner 1621 are formed in the first opening 150p and the second opening 160p, respectively. For example, the first liner 1521 and the second liner 1621 disposed on the sidewalls of the first opening 150p and the second opening 160p, respectively, can be formed by a deposition process. The material of the first liner 1521 and the second liner 1621 can include oxide. In one embodiment, oxide can be first deposited in the first opening 150p and the second opening 160p, and then unnecessary oxide can be removed by an etching process, leaving only the oxide on the sidewalls of the first opening 150p and the second opening 160p, so as to form the first liner 1521 and the second liner 1621. The first opening 150p and the second opening 160p expose the corresponding landing pad 124 and the corresponding conductive line 116 of the circuit board 110 .

Please refer to FIGS. 10A and 10B at the same time. In one example, the conductive material is filled in the first opening 150p and the second opening 160p (i.e., the space surrounded by the first liner 1521 and the second liner 1621), respectively. Therefore, the first conductive pillar 1522 and the second conductive pillar 1622 are formed. In this way, the support pillar 152 can be formed in the step area SA and the vertical contact 162 can be formed in the peripheral area PA by the same process (e.g., the same etching process and deposition process). The support pillar 152 includes a first conductive pillar 1522 and a first liner 1521 surrounding the first conductive pillar 1522. The first conductive post 1522 of the support post 152 contacts the corresponding landing pad 124 embedded in the third conductive layer 129 of the base plate 120. The vertical contact 162 includes a second conductive post 1622 and a second liner 1621 surrounding the second conductive post 1622. The vertical contact 162 electrically contacts the corresponding wire 116 of the circuit board 110.

In another example, the materials filled in the first opening 150p and the second opening 160p (i.e., the space surrounded by the first liner 1521 and the second liner 1621) in separate processes may be different. The material filled in the first opening 150p may include a dielectric material, such as an oxide or a nitride. The support column 152 is a dielectric column. The material filled in the second opening 160p may be a conductive material, such as tungsten or polysilicon. The vertical contact 162 includes a second conductive column 1622 and a second liner 1621 surrounding the second conductive column 1622. The vertical contact 162 electrically contacts the corresponding wire 116 of the circuit board 110.

11A and 11B, a plurality of trenches LT are formed along a first direction (e.g., Z direction) through the stacked structure 130' and extending along a second direction (e.g., X direction). The plurality of trenches LT stop on the second conductive layer 125 of the bottom plate 120. For example, the trenches LT can be formed by an etching process (e.g., dry etching).

Please refer to FIGS. 12A and 12B simultaneously. The second conductive layer 125 in the bottom plate 120 is removed through the trench LT by an etching process, and the first insulating layer 123 and the second insulating layer 127 are removed. In this step, a portion of the bottom plate 120 is removed to form an opening between the first conductive layer 123 and the third conductive layer 129, so the bottom support 122 is required to maintain the stability of the structure. In some embodiments, a portion of the memory layer 136 corresponding to the memory pillar MP between the first conductive layer 123 and the third conductive layer 129 is removed. A portion of the channel layer 138 of the corresponding memory pillar MP is exposed at the opening.

Please refer to FIGS. 13A and 13B at the same time. Through a deposition process, a conductive material is filled in the positions where the second conductive layer 125, the first insulating layer 123, and the second insulating layer 127 are removed. The conductive material is, for example, polycrystalline silicon. In this way, the conductive material connects the first conductive layer 121 and the third conductive layer 129 to each other. The conductive material, the first conductive layer 121, and the third conductive layer 129 together form a bottom conductive layer CSL (which can serve as a common source line). An interface may exist between the first conductive layer 121 and the conductive material. Similarly, an interface may exist between the third conductive layer 129 and the conductive material. A portion of the channel layer 138 of the corresponding memory pillar MP contacts the bottom conductive layer CSL. The channel layer 138 covering the bottom surface of the insulating pillar 140 of the memory pillar MP is embedded in the bottom conductive layer CSL. The memory layer 136 covering the bottom surface of the channel layer 138 of the memory pillar MP is embedded in the bottom conductive layer CSL. The discharge pillar 126 passes through the first conductive layer 121, the first insulating layer 123, the second conductive layer 125, the second insulating layer 127 and the third conductive layer 129 and is electrically connected to the corresponding wire 116. In the process of FIGS. 13A and 13B , the conductive material may be first filled into the second conductive layer 125, the positions where the first insulating layer 123 and the second insulating layer 127 are removed, and the trench LT, and then the conductive material in the trench LT is removed by an etching back process to expose the trench LT again.

Please refer to FIGS. 14A and 14B at the same time. The sacrificial layer 135 in the array area AA and the step area SA is removed through the trench LT by an etching process. In this step, since the present case has supporting pillars 152, the supporting pillars 152 can provide sufficient supporting force. Even if the sacrificial layer 135 is removed, the supporting pillars 152 can still maintain the stability of the entire structure and not easily collapse.

Referring to FIGS. 15A and 15B , conductive material is filled into the position where the sacrificial layer 135 is removed. Therefore, in the array area AA and the step area SA, a stack 130 is formed in which the conductive layer 134 and the insulating layer 132 are alternately stacked. In one embodiment, the conductive material of the conductive layer 134 may include tungsten. In the peripheral area PA, the sacrificial layer 135 and the insulating layer 132 alternately stacked in the stack structure 130' are retained, that is, the sacrificial layer 135 in the peripheral area PA is not removed. The steps shown in FIGS. 14A to 15B can also be called a gate replacement process.

Please refer to FIGS. 16A and 16B simultaneously, the trench LT is slightly enlarged, and an insulating material and a conductive material are sequentially filled into the trench LT. The filled trench LT includes an insulating sidewall L3 on the sidewall of the trench LT. The filled trench LT includes a first conductive layer L1 and a second conductive layer L2 surrounded by the insulating sidewall L3. The first conductive layer L1 and the second conductive layer L2 in the filled trench LT are electrically in contact with the bottom conductive layer CSL (as a common source line). The materials of the first conductive layer L1 and the second conductive layer L2 may be different from each other. For example, the first conductive layer L1 may be polysilicon, and the material of the second conductive layer L2 may be metal, such as tungsten. The material of the insulating sidewall L3 may include oxide, but the present invention is not limited thereto.

Referring to FIGS. 17A and 17B , a plurality of extended contacts 174 are formed and disposed on the landing area of the step area SA. The plurality of extended contacts 174 contact the corresponding conductive layer 134. The back end of line (BEOL) process is performed to form the internal connection 172 and the extended contact 174 contacting the pad 142. A plurality of connectors 176 are formed to connect the corresponding vertical contacts 162 in the peripheral area PA. In the back end of line (BEOL), the support column 152 is not connected to any internal connection 172. It should be understood that the back-end process also includes the step of forming more wires/conductive layers/plugs (not shown). The internal connection 172, the extended contact 174 and the connector 176 can be electrically connected to other circuits (not shown) through more wires/conductive layers/plugs. Those having ordinary knowledge in the art can manufacture them in a known manner, which will not be elaborated here.

Through the above steps, a semiconductor device 10 according to an embodiment of the present invention is formed, as shown in FIGS. 17A-17B. The semiconductor device 10 includes a circuit board 110, a base plate 120, a stacking structure 130', a stack 130, a memory pillar MP, a support pillar 152, and a vertical contact 162. The base plate 120 is disposed on the circuit board 110. The stacking structure 130' and the stack 130 are disposed side by side on the base plate 120, and the stacking structure 130' and the stack 130 are adjacent to each other. The support pillar 152 and the vertical contact 162 pass through the stack 130 and the stacking structure 130' respectively along a first direction (e.g., Z direction). The memory pillars MP pass through the stack 130 along a first direction (eg, Z direction).

Please refer to Figures 17A-17B again, the circuit board 110 includes a substrate 112, a plurality of circuit structures 114, a plurality of wires 116 and an insulating material 118. The circuit structure 114 is disposed on the substrate 112, and the wires 116 are electrically connected to the corresponding circuit structure 114. The insulating material 118 covers the substrate 112, the circuit structure 114 and the wires 116. The circuit board 110 corresponds to the peripheral area PA, the step area SA and the array area AA. The step area SA is disposed between the peripheral area PA and the array area AA. A plurality of memory pillars MP pass through the stack 130 along a first direction in the array area AA.

The bottom plate 120 may include a bottom conductive layer CSL (e.g., in the step area SA and the array area AA). The bottom conductive layer CSL may serve as a common source line in the semiconductor device 10. The semiconductor device 10 further includes a plurality of landing pads 124, a plurality of discharge pillars 126, and a plurality of bottom supports 122. The entire landing pad 124 is embedded in at least a top portion of the bottom conductive layer CSL in the step area SA and directly contacts (physically and electrically contacts) the bottom conductive layer CSL. The discharge pillars 126 pass through the bottom conductive layer CSL along a first direction (e.g., the Z direction) and electrically contact the bottom conductive layer CSL and the corresponding wires 116. A lot of charges may be accumulated during the process of manufacturing the semiconductor device 10. The discharge pillar 126 can discharge these accumulated charges downward to avoid excessive voltage difference between the upper and lower conductors. The bottom support member 122 is disposed in the step area SA and passes through the bottom conductive layer CSL along a first direction (e.g., Z direction). The bottom support members 122 are separated from each other and can maintain the stability of the structure during the process of forming the bottom conductive layer CSL, for example, providing support force in the steps shown in Figures 12A and 12B. In this embodiment, the discharge column 126 includes a conductive material, and the landing pad 124 includes a conductive material. The discharge column 126 and the landing pad 124 can be formed in the same process (such as etching and deposition process, as shown in Figures 5-6). The conductive material of the discharge column 126 can be the same as the conductive material of the landing pad 124, but the present invention is not limited to this.

In the array area AA and the step area SA, the stack 130 includes a plurality of conductive layers 134 and a plurality of insulating layers 132 alternately stacked along a first direction. The stack structure 130′ includes a plurality of sacrificial layers 135 and a plurality of insulating layers 132 alternately stacked along the first direction. The insulating layers 132 of the stack 130 and the insulating layers 132 of the stack structure 130′ are connected to each other. The conductive layers 134 of the stack 130 and the sacrificial layers 135 of the stack structure 130′ are connected to each other in the step area SA or in the peripheral area PA. The conductive layer 134 may include one or more series select lines at the top portion of the stack 130, a plurality of word lines at the middle portion of the stack 130, and one or more ground select lines at the bottom portion of the stack 130.

The support post 152 and the vertical contact member 162 pass through the stack 130 and the stack structure 130' along a first direction (e.g., Z direction). In more detail, the support post 152 passes through the stack 130 and the bottommost conductive layer 134 (i.e., the bottommost ground selection line) in the stack 130, and extends to the landing pad 124 on the bottom conductive layer CSL. The support post 152 can directly contact (physically and electrically contact) the landing pad 124. In other words, there is a landing pad 124 between the bottom conductive layer CSL and the support post 152. The bottom surface of the landing pad 124 in the step area SA is lower than the top surface of the bottom conductive layer CSL in the array area AA, that is, the distance DA between the bottom surface of the landing pad 124 in the step area SA and the bottom surface of the bottom conductive layer CSL in the first direction is smaller than the distance DB between the top surface of the bottom conductive layer CSL in the array area AA and the bottom surface of the bottom conductive layer CSL in the first direction. In the first direction (e.g., the Z direction), the support post 152 in the step area SA overlaps with the landing pad 124. In one embodiment, the support post 152 may include a conductive material. Specifically, the support post 152 includes a first conductive post 1522 and a first liner 1521 surrounding the first conductive post 1522. In this embodiment, the first conductive post 1522 directly contacts the landing pad 124. The material of the first conductive post 1522 may be the same as the material of the landing pad 124 (e.g., tungsten), but the present invention is not limited thereto. In other embodiments, the material of the first conductive post 1522 may be different from the material of the landing pad 124. In another embodiment, the support post 152 is a dielectric post. Since there is a landing pad 124 under the supporting column 152, during the process of forming the supporting column 152, when an opening (such as the first opening 150 shown in FIG. 8A) is formed in the etching process, the landing pad 124 can provide a good etching selectivity. Compared with the comparative example without the landing pad, the etching depth of the present case can be better controlled, and the formation of the etching opening can be appropriately stopped on the landing pad 124.

The vertical contact 162 passes through the stacked structure 130' and the bottom plate 120 (i.e., passes through the bottom conductive layer CSL) along a first direction (e.g., Z direction) and extends to the corresponding wire 116. The vertical contact 162 includes a second conductive column 1622 and a second liner 1621 surrounding the second conductive column 1622. In this embodiment, the material of the second conductive column 1622 may be the same as the material of the first conductive column 1522 (e.g., tungsten), and the material of the second liner 1621 may be the same as the material of the first liner 1521 (e.g., oxide), but the present invention is not limited thereto. The support pillars 152 and the vertical contacts 162 can be formed in the same process (as shown in FIGS. 8A to 10A ). That is, the formation of the support pillars 152 and the vertical contacts 162 can be integrated in the same deep etching process, and there is no need to manufacture the support pillars 152 in an additional process.

In the stack 130 corresponding to the array area AA, each conductive layer 134 intersects the memory layer 136 and the channel layer 138 to form a memory cell string extending along a first direction (e.g., Z direction). The channel layer 138 is electrically connected to the bottom conductive layer CSL. Each memory pillar MP includes a memory cell string connected in series in a NAND type, but the present invention is not limited thereto. Furthermore, the trench LT and the top isolation member SSLC extend along the first direction (e.g., Z direction) and the second direction (e.g., X direction), dividing the stack 130 into a predetermined number of blocks and sub-blocks (not shown). Each trench LT includes a first conductive layer L1 (e.g., polysilicon), a second conductive layer L2 (e.g., tungsten), and an insulating sidewall L3 (e.g., oxide), and the insulating sidewall L3 allows the first conductive layer L1 and the second conductive layer L2 to be isolated from an adjacent layer (e.g., conductive layer 134). The first conductive layer L1 is electrically in contact with the bottom conductive layer CSL below. The top isolation member SSLC (e.g., oxide) passes through the conductive layer 134 corresponding to the top portion of the stack 130 along a first direction (e.g., Z direction) to define a series selection line.

In the step region SA of the stack 130, the conductive layer 134 has a step-shaped structure to provide a landing area connected to the extended contact 174 so that the extended contact 174 is electrically connected to the corresponding conductive layer 134. The extended contact 174 may include a word line contact.

18A to 18F illustrate a manufacturing process flow chart of a semiconductor device 20 according to another embodiment of the present invention. In particular, FIGS. 18A to 18F correspond to a plane formed by a second direction (eg, X direction) and a third direction (eg, Y direction).

The semiconductor device 20 has the same and similar manufacturing process and structure as the semiconductor device 10, except that the semiconductor device 20 further includes a vertical support member 180 in the step area SA.

Referring to FIG. 18A , after forming the bottom plate 120 on the circuit board 110, the first conductive layer 121, the second conductive layer 125, and the third conductive layer 129 at predetermined positions are removed to form a plurality of openings, and then an insulating material is filled in the openings, and a plurality of bottom support members 122 (e.g., oxide) are formed in the step area SA, as shown in the steps and related contents of FIGS. 1 to 3. In addition, a plurality of holes 180p may be formed in the step area SA. The hole 180p indicates the predetermined position of the vertical support member 180. For a clearer distinction, the cross-section of the hole 180p is represented by a square, and the cross-section of the bottom support member 122 is represented by a circle. However, the shapes of the cross-sections of the hole 180p and the bottom support member 122 are not limited thereto.

Referring to FIG. 18B , a plurality of landing pads 124 and a plurality of discharge posts 126 are formed. The structures, functions and formation steps of the landing pads 124 and the discharge posts 126 are shown in FIGS. 4-5 and related contents. Adjacent landing pads 124 are separated by bottom supports 122. As shown in FIG. 18B , in this embodiment, the discharge posts 126 can be further away from the array area AA than the landing pads 124.

Please refer to FIG. 18C to form a memory pillar MP and a top isolation member SSLC. The structure, function and formation steps of the memory pillar MP and the top isolation member SSLC are shown in FIGS. 7A and 7B and their related contents.

Referring to FIG. 18D , the support column 152, the vertical contact member 162 and the vertical support member 180 are formed by the same process. The structure, function and formation steps of the support column 152 and the vertical contact member 162 are shown in FIGS. 8A to 10B and related contents. The support column 152 in the step area SA is formed on the landing pad 124. The vertical contact member 162 extends through the base plate 120 along a first direction (e.g., Z direction) to the corresponding wire 116. The formation method and structure of the vertical support member 180 located in the step area SA are similar to the formation method and structure of the vertical contact member 162 located in the peripheral area PA. The vertical support member 180 located in the step area SA extends through the base plate 120 along a first direction (e.g., Z direction) to the corresponding wire 116. The vertical support member 180 includes a third conductive column (not shown) and a third inner liner (not shown) surrounding the third conductive column. In one example, the material of the third conductive column (not shown) is the same as the material of the first conductive column 1522 and the second conductive column 1622. The material of the third inner liner (not shown) is a dielectric material. In some examples, the material of the third inner liner (not shown) is the same as the material of the first inner liner 1521 and the second inner liner 1621. The third conductive column (not shown) is electrically in contact with the corresponding wire 116. The vertical contact 162 in the peripheral area PA may have a signal transmission function (e.g., signal transmission of a word line). The support pillars 152 in the step area SA have the function of supporting the overall structure during the gate replacement process. The vertical support members 180 in the step area SA not only have the function of signal transmission, but also have the function of supporting the overall structure during the gate replacement process.

Referring to FIG. 18E , a trench LT is formed and a gate replacement process is performed. The steps of forming the trench LT and the gate replacement process are shown in FIGS. 11A to 16B and related contents. The trench LT extends from the array area AA to the step area SA along the second direction (eg, the X direction).

Referring to FIG. 18F, a plurality of extended contacts 174 are formed in the step area SA. After that, the back-end process is performed. The formation method of the back-end process is shown in FIGS. 17A-17B and related contents.

As shown in FIG. 18F , in the step area SA, the discharge column 126 is farther from the trench LT than the supporting column 152. For example, in the step area SA, a first distance D1 is provided between the end of the trench LT and the center point of the discharge column 126 in the second direction (e.g., the X direction). A second distance D2 is provided between the end of the trench LT and the center point of the supporting column 152 (e.g., the supporting column 152 closest to the discharge column 126) in the second direction (e.g., the X direction). The first distance D1 is greater than the second distance D2.

FIG. 19 shows a cross-sectional view of a landing pad 224 according to another embodiment of the present invention. FIG. 20A shows a top view of a landing pad 324 according to another embodiment of the present invention, and FIG. 20B shows a cross-sectional view of a landing pad 324 according to another embodiment of the present invention. FIG. 19 and FIG. 20B correspond to a plane formed by a first direction (e.g., Z direction) and a second direction (e.g., X direction). FIG. 20A corresponds to a plane formed by a second direction (e.g., X direction) and a third direction (e.g., Y direction).

Referring to FIG. 19 , the landing pad 224 is different from the landing pad 124 shown in FIG. 6 in that the landing pad 224 is a double-layer structure, including an insulating portion 2241 and a conductive portion 2242. The insulating portion 2241 covers the sidewalls and the bottom of the conductive portion 2242, exposing the upper surface of the conductive portion 2242, so that the landing pad 224 is electrically isolated from the third conductive layer 129 below (that is, electrically isolated from the bottom conductive layer CSL formed subsequently). In this embodiment, the material of the insulating portion 2241 may include oxide, and the material of the conductive portion 2242 may include a conductive material, such as tungsten. The upper surface of the landing pad 224 is still a conductive material, so it can provide a good etching selectivity like the landing pad 124. Furthermore, the insulating portion 2241 of the landing pad 224 also has the advantage of reducing the RC delay of the bottom conductive layer.

20A and 20B, the landing pad 324 includes an insulating portion 3241 and a conductive portion 3242. The material of the insulating portion 3241 may include an oxide, and the material of the conductive portion 3242 may include a conductive material, such as tungsten. The difference between the landing pad 324 and the landing pad 224 is that the landing pad 324 extends downward from the third conductive layer 129 to the first conductive layer 121, that is, the landing pad 324 can extend to the bottom of the bottom conductive layer CSL. In this way, the landing pad 324 can be used as a support member in the process of forming the bottom conductive layer CSL (as shown in FIGS. 12A and 12B), so the bottom support member 122 can be omitted. Similarly, the landing pad 324 can provide a good etching selectivity and has the advantage of reducing the resistance and capacitance delay of the bottom conductive layer CSL.

In summary, although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined in the attached patent application.

10,20: semiconductor device 110: circuit board 112: substrate 114: circuit structure 116: wire 118: insulating material 120: bottom plate 121: first conductive layer 122: bottom support 123: first insulating layer 124,224,324: landing pad 124p: top opening 125: second conductive layer 126: discharge column 126p: through opening 127: second insulating layer 129: third conductive layer 130: stacking 130’: stacking structure 132: insulating layer 134: Conductive layer 135: Sacrificial layer 136: Memory layer 138: Channel layer 140: Insulation column 142: Solder pad 144: Insulation material 150p: First opening 152: Support column 160p: Second opening 162: Vertical contact 172: Inner connection 174: Extended contact 176: Connector 180p: Hole 180: Vertical support 1521: First inner liner 1522: First conductive column 1621: Second inner liner 1622: Second conductive column 2241,3241: Insulation part 2242,3242: Conductive part AA: Array area CSL: Bottom conductive layer DA,DB: Distance L1: First conductive layer L2: Second conductive layer L3: Insulation sidewall MP: Memory pillar PA: Peripheral area SA: Step area SSLC: Top isolation element D1: First distance D2: Second distance

Figures 1 to 17B illustrate a manufacturing flow chart of a semiconductor device according to an embodiment of the present invention; Figures 18A to 18F illustrate a manufacturing flow chart of a semiconductor device according to another embodiment of the present invention; Figure 19 illustrates a cross-sectional view of a landing pad according to another embodiment of the present invention; Figure 20A illustrates a top view of a landing pad according to another embodiment of the present invention; and Figure 20B illustrates a cross-sectional view of a landing pad according to another embodiment of the present invention.

10: semiconductor device 110: circuit board 112: substrate 114: circuit structure 116: wire 118: insulating material 120: bottom plate 121: first conductive layer 122: bottom support 123: first insulating layer 124: landing pad 124p: top opening 125: second conductive layer 126: discharge column 126p: through opening 127: second insulating layer 129: third conductive layer 130: stacking 130': stacking structure 132: insulating layer 134: conductive layer 135: Sacrificial layer 136: Memory layer 138: Channel layer 140: Insulation column 142: Pad 144: Insulation material 150p: First opening 152: Support column 160p: Second opening 162: Vertical contact 172: Inner connection 174: Extended contact 176: Connector 1521: First inner liner 1522: First conductive column 1621: Second inner liner 1622: Second conductive column AA: Array area CSL: Bottom conductive layer DA, DB: Distance MP: Memory column PA: Peripheral area SA: Staircase area

Claims (10)

A semiconductor device comprises: A circuit board comprising a plurality of circuit structures and a plurality of conductors, wherein the circuit structures are electrically connected to the corresponding conductors, and the circuit board has a peripheral area, an array area, and a step area disposed between the peripheral area and the array area; A base plate disposed on the circuit board, and the base plate comprises a bottom conductive layer; A plurality of landing pads, wherein each landing pad is entirely embedded in at least a top portion of the bottom conductive layer in the step area and contacts the bottom conductive layer; A stack is disposed on the base plate, the stack comprising a plurality of conductive layers and a plurality of insulating layers alternately stacked along a first direction; A plurality of support pillars pass through the stack along the first direction in the step region and extend to the landing pads; and A plurality of memory pillars pass through the stack along the first direction in the array region. The semiconductor device as described in claim 1 further includes a plurality of vertical contacts extending along the first direction in the peripheral area and electrically contacting the corresponding wires, wherein the support pillars and the vertical contacts include the same conductive material. A semiconductor device as described in claim 1, wherein each of the landing pads has a conductive portion. The semiconductor device as described in claim 3 further includes an insulating portion covering the side walls and bottom of the conductive portion. The semiconductor device as described in claim 1 further comprises a plurality of discharge columns, which pass through the bottom conductive layer along the first direction in the step region and are electrically in contact with the corresponding conductive lines. A semiconductor device as described in claim 5, wherein a top surface of the landing pads is substantially coplanar with a top surface of the discharge pillars. The semiconductor device as described in claim 5 further includes at least one trench, the at least one trench passes through the stack along the first direction and extends from the array region to the step region along a second direction, the second direction being different from the first direction, wherein the discharge pillars are farther away from the at least one trench than the support pillars. A method for manufacturing a semiconductor device, comprising: Forming a circuit board, the circuit board comprising a plurality of circuit structures and a plurality of wires, the circuit structures being electrically connected to the corresponding wires, and the circuit board having a peripheral region, an array region, and a step region disposed between the peripheral region and the array region; Forming a base plate on the circuit board, the base plate comprising a bottom conductive layer; Forming a plurality of landing pads, the landing pads being entirely embedded in at least a top portion of the bottom conductive layer in the step region and contacting the bottom conductive layer; A stack is formed on the base plate, the stack comprising a plurality of conductive layers and a plurality of insulating layers alternately stacked along a first direction; A plurality of support pillars are formed, the support pillars pass through the stack along the first direction in the step region and extend to the landing pads; and A plurality of memory pillars are formed, the memory pillars pass through the stack along the first direction in the array region. The method for manufacturing a semiconductor device as described in claim 8, wherein the step of forming the base plate further includes: Forming a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer and a third conductive layer on the circuit board in sequence in the first direction. The method for manufacturing a semiconductor device as described in claim 8 further includes: forming a plurality of top openings in a top portion of a third conductive layer in the step region, the top openings being separated from each other; and filling a conductive material into the top openings to form the landing pads.

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