TWI897316B - Semiconductor structure for 3d memory and manufacturing method thereof - Google Patents

Abstract

Provided are a semiconductor structure for a three-dimensional (3D) memory and a manufacturing method thereof. The semiconductor structure may be used in a 3D AND flash memory. The semiconductor structure includes a substrate, a circuit structure layer, a first conductive layer, a stacked structure, an oxide layer, a first insulating wall and a plurality of first dummy pillars. The substrate has a memory device region and a peripheral region surrounding the memory device region, and the memory device region includes a memory array region and a staircase region. The circuit structure layer is disposed on the substrate. The first conductive layer is disposed on the circuit structure layer. The stacked structure is disposed on the first conductive layer in the memory device region and includes a plurality of second conductive layers and a plurality of insulating layers alternately stacked, and the stacked structure in the staircase region has a staircase profile. The oxide layer is disposed on the first conductive layer and surrounds the stacked structure. The first insulating wall is disposed in the oxide layer, penetrates through the first conductive layer, and surrounds the stacked structure. The plurality of first dummy pillars are disposed in the peripheral region and the staircase region, wherein each first dummy pillar in the peripheral region penetrates through the oxide layer and the first conductive layer, and each first dummy pillar in the staircase region penetrates through the stacked structure and the first conductive layer.

Description

Semiconductor structure for three-dimensional memory and manufacturing method thereof

The present invention relates to a semiconductor structure and a method for manufacturing the same, and in particular to a semiconductor structure for three-dimensional memory and a method for manufacturing the same.

Non-volatile memory (such as flash memory) is widely used in personal computers and other electronic devices because it preserves stored data even after power is removed. Advances in process technology, circuit design, and programming algorithms have significantly reduced the size of memory components, allowing for higher integration densities.

However, due to process limitations, the size of traditional planar memory devices is no longer able to meet the demands of device miniaturization. Therefore, research and development is underway to develop three-dimensional flash memory devices (3D memory devices), evolving the memory device type from two-dimensional memory devices with a planar gate structure to three-dimensional memory devices with a vertical channel (VC) structure.

In current 3D flash memory device manufacturing processes, after thermal treatment of the peripheral nitride layer, the hydrogen contained in the nitride layer can cause threshold voltage shifting in P-type metal-oxide-semiconductor (MOS) transistors.

Therefore, as the size of electronic devices continues to shrink and users' performance requirements for electronic devices continue to increase, technicians in this field continue to improve the size and performance of memory devices used in electronic devices.

The present invention provides a semiconductor structure for three-dimensional memory and a method for manufacturing the same, wherein the nitride layer in the peripheral region surrounding the memory element region is removed to resolve the problem of the nitride layer causing threshold voltage shifting in the P-type metal oxide semiconductor transistor after thermal treatment.

The semiconductor structure for three-dimensional memory of the present invention includes a substrate, a circuit structure layer, a first conductive layer, a stacked structure, an oxide layer, a first insulating wall, and a plurality of first dummy pillars. The substrate has a memory element region and a peripheral region surrounding the memory element region, and the memory element region includes a memory array region and a staircase region. The circuit structure layer is disposed on the substrate. The first conductive layer is disposed on the circuit structure layer. The stacked structure is disposed on the first conductive layer in the memory element region and includes a plurality of alternately stacked second conductive layers and a plurality of insulating layers. The stacked structure in the staircase region has a staircase profile. The oxide layer is disposed on the first conductive layer and surrounds the stacked structure. The first insulating wall is disposed in the oxide layer, penetrates the first conductive layer, and surrounds the stacked structure. The plurality of first dummy pillars are disposed in the peripheral region and the step region, wherein each first dummy pillar in the peripheral region penetrates the oxide layer and the first conductive layer, and each first dummy pillar in the step region penetrates the stacked structure and the first conductive layer.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, it further includes a plurality of supporting pillars disposed in the step region and penetrating the stacked structure and the first conductive layer.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, it further includes a plurality of second insulating walls arranged parallel to each other in the stacked structure to divide the stacked structure into a plurality of blocks arranged parallel to each other.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, in each of the blocks, the first dummy pillar is located on a first side of the memory array region, and the plurality of supporting pillars are located on a second side of the memory array region opposite to the first side.

In one embodiment of the semiconductor structure for a three-dimensional memory of the present invention, the first dummy pillar in each block is adjacent to the supporting pillar in the adjacent block, and the supporting pillar in each block is adjacent to the first dummy pillar in the adjacent block.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, it further includes a plurality of vertical channel structures disposed in the memory array region and penetrating the stacked structure and the first conductive layer.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, the first insulating wall is located in the memory element region and adjacent to the boundary between the memory element region and the peripheral region, and is spaced a distance from the bottommost second conductive layer in the stacked structure.

The method for manufacturing a semiconductor structure for a three-dimensional memory of the present invention includes the following steps: providing a substrate, wherein the substrate has a memory element region and a peripheral region surrounding the memory element region, and the memory element region includes a memory array region and a step region. forming a circuit structure layer on the substrate. forming a first conductive layer on the circuit structure layer. forming a stacked structure on the first conductive layer in the memory element region, wherein the stacked structure includes a plurality of alternately stacked second conductive layers and a plurality of insulating layers, and the stacked structure in the step region has a step profile. forming an oxide layer on the first conductive layer, wherein the oxide layer surrounds the stacked structure. A first insulating wall is formed in the oxide layer, wherein the first insulating wall penetrates the first conductive layer and surrounds the stacked structure. A plurality of first dummy pillars are formed in the peripheral region and the step region, wherein each of the first dummy pillars in the peripheral region penetrates the oxide layer and the first conductive layer, and each of the first dummy pillars in the step region penetrates the oxide layer, the stacked structure, and the first conductive layer.

In one embodiment of the present invention's method for fabricating a semiconductor structure for a three-dimensional memory, the method for forming the stacked structure and the oxide layer includes the following steps: forming a first initial stacked structure on the first conductive layer, wherein the first initial stacked structure includes the plurality of insulating layers and the plurality of sacrificial layers stacked alternately; removing portions of the insulating layers and the sacrificial layers to expose the first conductive layer in the peripheral region; and forming a second initial stacked structure in the memory device region, wherein the second initial stacked structure in the step region has the step profile; forming the oxide layer on the first conductive layer; and replacing the plurality of sacrificial layers with the plurality of second conductive layers.

In one embodiment of the method for fabricating a semiconductor structure for a three-dimensional memory of the present invention, after forming the oxide layer and before replacing the plurality of sacrificial layers with the plurality of second conductive layers, the method further includes forming a plurality of vertical channel structures in the memory array region, wherein each of the vertical channel structures penetrates the second initial stacking structure and the first conductive layer.

In one embodiment of the method for fabricating a semiconductor structure for a three-dimensional memory of the present invention, after forming the plurality of vertical channel structures and before replacing the plurality of sacrificial layers with the plurality of second conductive layers, the method further includes forming the plurality of first dummy pillars in the peripheral region and the step region, wherein each of the first dummy pillars in the peripheral region penetrates the oxide layer and the first conductive layer, and each of the first dummy pillars in the step region penetrates the second initial stacked structure and the first conductive layer.

In one embodiment of the method for fabricating a semiconductor structure for a three-dimensional memory of the present invention, when forming the plurality of vertical channel structures, the method further includes forming a plurality of supporting pillars in the step region, wherein each of the supporting pillars penetrates the second initial stacking structure and the first conductive layer.

In one embodiment of the present invention, the method for fabricating a semiconductor structure for a three-dimensional memory further includes the following steps after forming the plurality of first dummy pillars: Forming a first slit in the oxide layer, wherein the first slit penetrates the oxide layer and the first conductive layer and surrounds the second initial stacking structure; Forming a plurality of second slits parallel to each other in the second initial stacking structure to divide the second initial stacking structure into a plurality of blocks arranged parallel to each other; and Replacing the plurality of sacrificial layers with the plurality of second conductive layers. An insulating material is filled into the first slit and the plurality of second slits to form the first insulating wall in the first slit and a plurality of second insulating walls in the second slit.

In one embodiment of the method for fabricating a semiconductor structure for a three-dimensional memory of the present invention, after forming the oxide layer and before replacing the plurality of sacrificial layers with the plurality of second conductive layers, the method further includes forming the plurality of first dummy pillars in the peripheral region and the step region, wherein each of the first dummy pillars in the step region penetrates the second initial stacked structure and the first conductive layer.

In one embodiment of the method for fabricating a semiconductor structure for a three-dimensional memory of the present invention, after forming the plurality of first dummy pillars and before replacing the plurality of sacrificial layers with the plurality of second conductive layers, the method further includes forming a plurality of vertical channel structures in the memory array region, wherein each of the vertical channel structures penetrates the second initial stacking structure and the first conductive layer.

In one embodiment of the method for fabricating a semiconductor structure for a three-dimensional memory of the present invention, when forming the plurality of vertical channel structures, the method further includes forming a plurality of supporting pillars in the step region, wherein each of the supporting pillars penetrates the second initial stacking structure and the first conductive layer.

In one embodiment of the present invention, the method for fabricating a semiconductor structure for a three-dimensional memory further includes the following steps after forming the plurality of vertical channel structures: forming a first slit in the oxide layer, wherein the first slit penetrates the first conductive layer and surrounds the second initial stacking structure; forming a plurality of second parallel slits in the second initial stacking structure to divide the second initial stacking structure into a plurality of parallel blocks; and replacing the plurality of sacrificial layers with the plurality of second conductive layers. An insulating material is filled into the first slit and the plurality of second slits to form the first insulating wall in the first slit and a plurality of second insulating walls in the second slit.

In one embodiment of the present invention's method for fabricating a semiconductor structure for a three-dimensional memory, the method for forming the stacked structure, the oxide layer, and the plurality of first dummy pillars includes the following steps: forming a first initial stacked structure on the circuit structure layer, wherein the initial stacked structure includes the plurality of insulating layers and the plurality of sacrificial layers stacked alternately; removing portions of the insulating layers and the sacrificial layers to form a second initial stacked structure in the memory device region, wherein the second initial stacked structure in the step region has the step profile; and forming a first oxide material layer to cover the second initial stacked structure. The plurality of first dummy pillars are formed in the peripheral region and the step region, wherein each of the first dummy pillars in the peripheral region penetrates the first initial stacking structure and the first conductive layer, and each of the first dummy pillars in the step region penetrates the first oxide material layer, the second initial stacking structure, and the first conductive layer. A plurality of holes are formed in the peripheral region, penetrating the first initial stacking structure and the first conductive layer. The plurality of sacrificial layers in the peripheral region are replaced with a second oxide material layer through the plurality of holes to form the oxide layer. A plurality of second dummy pillars are formed in the plurality of openings. The plurality of sacrificial layers in the memory device region are replaced with a plurality of second conductive layers.

In one embodiment of the method for fabricating a semiconductor structure for a three-dimensional memory of the present invention, before forming the plurality of first dummy pillars, the method further includes forming a plurality of vertical channel structures in the memory array region, wherein each of the vertical channel structures penetrates the second initial stacking structure and the first conductive layer.

In one embodiment of the method for fabricating a semiconductor structure for a three-dimensional memory of the present invention, when forming the plurality of vertical channel structures, the method further includes forming a plurality of supporting pillars in the step region, wherein each of the supporting pillars penetrates the second initial stacking structure and the first conductive layer.

In one embodiment of the method for fabricating a semiconductor structure for a three-dimensional memory of the present invention, after forming the plurality of first dummy pillars and before forming the plurality of holes, the method further includes forming a plurality of vertical channel structures in the memory array region, wherein each of the vertical channel structures penetrates the second initial stacking structure and the first conductive layer.

In one embodiment of the method for fabricating a semiconductor structure for a three-dimensional memory of the present invention, when forming the plurality of vertical channel structures, the method further includes forming a plurality of supporting pillars in the step region, wherein each of the supporting pillars penetrates the second initial stacking structure and the first conductive layer.

In one embodiment of the present invention, the method for fabricating a semiconductor structure for a three-dimensional memory further includes the following steps after forming the plurality of second dummy pillars: Forming a first slit in the oxide layer, wherein the first slit penetrates the first conductive layer and surrounds the second initial stacking structure; Forming a plurality of second slits parallel to each other in the second initial stacking structure to divide the second initial stacking structure into a plurality of blocks arranged parallel to each other; and Replacing the plurality of sacrificial layers with the plurality of second conductive layers. An insulating material is filled into the first slit and the plurality of second slits to form the first insulating wall in the first slit and a plurality of second insulating walls in the second slit.

In one embodiment of the method for fabricating a semiconductor structure for a three-dimensional memory of the present invention, the first insulating wall is located in the memory element region and adjacent to the boundary between the memory element region and the peripheral region, and is spaced a distance from the bottommost second conductive layer in the stacked structure.

Based on the above, in the semiconductor structure for three-dimensional memory and its manufacturing method of the present invention, the stacked nitride layer in the peripheral region surrounding the memory element area is removed, eliminating the stacked structure of oxide and nitride layers in the peripheral region. This effectively prevents the nitride layer in the peripheral region from causing a critical voltage shift in the semiconductor devices (particularly P-type metal oxide semiconductor transistors) in the circuit structure layer after heat treatment.

100: Base

100a: Memory device area

100b: Peripheral area

102: Circuit structure layer

104: First conductive layer

106a: Insulating layer

106b: Sacrifice Layer

108, 504: Oxide layer

110: Vertical channel structure

112, 114: Dielectric layer

116: Support Pillar

118: The First Virtual Pillar

120: Second conductive layer

122, 510: Spacer layer

124a: First Insulation Wall

124b: Second Insulation Wall

126, 508: Polysilicon layer

500: First oxide material layer

502: Second oxide material layer

506: Second Virtual Pillar

AR: Memory Array Area

AG1, AG2, AG3: Air Gap

BL: Bit Line

BLOCK:Block

CH: Channel layer

D: Drain column

H: Hole

MC: Memory Unit

MSC, MSC1, MSC2: memory array

S, SP: Source Pillar

SC: Stairway Area

SL: source line

SLT1: First Slit

SLT2: Second Slit

ST1: First initial stacking structure

ST2: Second initial stacking structure

ST3: Stacked Structure

WL: word line

Figures 1A to 1E are schematic cross-sectional views of the manufacturing process of a semiconductor structure for a three-dimensional memory according to the first embodiment of the present invention.

Figures 2A to 2E are schematic top views of the manufacturing process of a semiconductor structure for a three-dimensional memory according to the first embodiment of the present invention, wherein Figures 1A to 1E are drawn along the A-A line in Figures 2A to 2E.

Figures 3A and 3B respectively show variations of the first dummy column in the first embodiment of the present invention.

Figures 4A and 4B show variations of the first insulating wall and the second insulating wall in the first embodiment of the present invention.

Figures 5A to 5E are schematic cross-sectional views of the manufacturing process of a semiconductor structure for a three-dimensional memory according to the second embodiment of the present invention.

Figures 6A, 6B, and 6C respectively show variations of the second dummy column in the second embodiment of the present invention.

FIG7 is a circuit diagram of a 3D AND flash memory array including the semiconductor structure of this embodiment.

The following examples are illustrated in detail with accompanying figures. However, these examples are not intended to limit the scope of the present invention. Furthermore, the figures are for illustrative purposes only and are not drawn to scale. For ease of understanding, identical components will be labeled with the same reference numerals throughout the following description.

The terms "include," "including," "have," etc. used in this document are open-ended terms, meaning "including but not limited to."

When terms such as "first," "second," etc. are used to describe elements, they are used solely to distinguish these elements from one another and do not limit the order or importance of these elements. Therefore, in some cases, a first element could be referred to as a second element, and a second element could be referred to as a first element, without departing from the scope of the present invention.

Furthermore, directional terms such as "upper" and "lower" are used herein solely to refer to the directions of the drawings and are not intended to limit the present invention. Therefore, it should be understood that "upper" and "lower" are used interchangeably, and that when an element, such as a layer or film, is placed "on" another element, the element may be placed directly on the other element, or intervening elements may be present. On the other hand, when an element is said to be placed "directly" on another element, there are no intervening elements between the two elements.

The terms used herein are intended to describe exemplary embodiments only and are not intended to limit the present disclosure. In this context, the singular includes the plural unless the context otherwise requires.

Figures 1A to 1E are schematic cross-sectional views of the manufacturing process for a semiconductor structure for a three-dimensional memory according to the first embodiment of the present invention. Figures 2A to 2E are schematic top-down views of the manufacturing process for a semiconductor structure for a three-dimensional memory according to the first embodiment of the present invention, with Figures 1A to 1E being drawn along the A-A line in Figures 2A to 2E.

First, referring to both Figures 1A and 2A , a substrate 100 is provided. In this embodiment, the substrate 100 includes a memory device region 100a and a peripheral region 100b surrounding the memory device region 100a. Furthermore, in this embodiment, the memory device region 100a includes a memory array region AR and a step region SC. In this embodiment, the substrate 100 may be a silicon substrate. As shown in Figure 2A , when viewed from above the substrate 100, the peripheral region 100b surrounds the memory device region 100a. Furthermore, within the memory device region 100a, the step region SC surrounds the memory array region AR.

Next, a circuit structure layer 102 is formed on the substrate 100. The circuit structure layer 102 may include various commonly known semiconductor components. For example, the circuit structure layer 102 may include transistors formed on the surface of the substrate 100, interconnect structures electrically connected to the transistors, and an interlayer dielectric layer (ILD layer) covering the transistors and the interconnect structures, but the present invention is not limited thereto. Furthermore, for clarity and because the detailed structure of the circuit structure layer 102 is well known to those skilled in the art, the detailed structure of the circuit structure layer 102 is not shown in the figures.

Next, a first conductive layer 104 is formed on the circuit structure layer 102. In this embodiment, the first conductive layer 104 may be a ground layer and may be electrically connected to the circuit structure layer 102 via conductive vias, but the present invention is not limited thereto. The first conductive layer 104 may be a polysilicon layer, but the present invention is not limited thereto. In addition, a dielectric layer (not shown) may be formed between the first conductive layer 104 and the circuit structure layer 102. Depending on the actual situation, the first conductive layer 104 may be omitted in other embodiments.

Next, a first initial stacking structure ST1 is formed on the first conductive layer 104. The first initial stacking structure ST1 includes a plurality of alternating insulating layers 106a and a plurality of sacrificial layers 106b. In this embodiment, both the bottom and top layers of the first initial stacking structure ST1 are insulating layers 106a, but the present invention is not limited thereto. Furthermore, in FIG1A , the number and thickness of the insulating and sacrificial layers 106a, 106b are merely exemplary and are not intended to limit the present invention. In this embodiment, the insulating layer 106a is a silicon oxide layer, and the sacrificial layer 106b is a silicon nitride layer, but the present invention is not limited thereto.

Next, referring to both FIG1B and FIG2B , portions of the insulating layer 106a and the sacrificial layer 106b are removed to expose the first conductive layer 104 in the peripheral region 100b and near the boundary between the peripheral region 100b and the memory device region 100a. A second initial stacking structure ST2 is formed in the memory device region 100a. Furthermore, after removing portions of the insulating layer 106a and the sacrificial layer 106b, the resulting second initial stacking structure ST2 has a staircase profile, i.e., the second initial stacking structure ST2 has multiple steps in the step region SC. The method of forming the second initial stacking structure ST2 to have a stepped profile is well known to those skilled in the art and will not be further described here.

Next, an oxide layer 108 is formed on the substrate 100 to cover the exposed first conductive layer 104 and the second initial stack structure ST2 in the memory device region 100a. In Figure 2B , the first conductive layer 104, sacrificial layer 106b, and oxide layer 108 are omitted for clarity and ease of understanding. In this embodiment, the oxide layer 108 is a silicon oxide layer. The oxide layer 108 can be formed, for example, by forming an oxide material layer on the substrate 100 and then performing a planarization process to ensure that the formed oxide layer 108 has a flat top surface. The planarization process can be, for example, a chemical mechanical polishing (CMP) process.

As a result, an oxide layer 108 exists in the peripheral region 100b, but no nitride layer exists.

In the semiconductor structure of the present invention formed in this step, the peripheral region 100b contains an oxide layer but no nitride layer. Therefore, subsequent heat treatment of the semiconductor structure of the present invention will not cause a critical voltage shift in the semiconductor elements (particularly P-type metal oxide semiconductor transistors) in the circuit structure layer 102.

Then, referring to both Figures 1C and 2C , after forming the oxide layer 108, a plurality of vertical channel structures 110 are formed in the memory array region AR. The vertical channel structures 110 penetrate the oxide layer 108, the second initial stack structure ST2, and the first conductive layer 104. In Figure 2C , the first conductive layer 104, the sacrificial layer 106b, and the oxide layer 108 are omitted for clarity and ease of understanding.

Specifically, in this embodiment, in the memory array region AR, a vertical channel structure 110 extends downward from the top surface of the oxide layer 108 through the oxide layer 108, the second initial stack structure ST2, and the first conductive layer 104. The vertical channel structure 110 may include a channel layer CH, a source pillar S, a drain pillar D, and dielectric pillars separating the source pillar S and the drain pillar D from each other. In this embodiment, the channel layer CH may be a polysilicon layer, and the source pillar S and the drain pillar D may be made of metal or doped polysilicon. Furthermore, in this embodiment, the dielectric pillars may include a dielectric layer 112 and a dielectric layer 114 located above the dielectric layer 112. The dielectric layer 112 may be an oxide layer, and the dielectric layer 114 may be a nitride layer. The formation methods of the channel layer CH, source pillar S, drain pillar D, and dielectric pillars are well known to those skilled in the art and will not be further described here.

Furthermore, in this embodiment, when forming the vertical channel structure 110, a plurality of supporting pillars 116 can be simultaneously formed in the step region SC. The supporting pillars 116 penetrate the oxide layer 108, the second initial stack structure ST2, and the first conductive layer 104.

Specifically, in this embodiment, support pillars 116 extend downward from the top surface of oxide layer 108 in step region SC, penetrating oxide layer 108, the corresponding terrace portion of second initial stack structure ST2, and first conductive layer 104. Support pillars 116 may include dielectric layer 112 and dielectric layer 114 within dielectric layer 112. Support pillars 116 provide support to second initial stack structure ST2 in step region SC. The method for forming support pillars 116 is well known to those skilled in the art and will not be further described here.

In FIG2C , the number and layout of the vertical channel structure 110 and the supporting pillars 116 are merely exemplary and are not limited to the present invention.

Next, referring to both Figures 1D and 2D , after forming the vertical channel structure 110 and support pillars 116, a plurality of first dummy pillars 118 are formed in the peripheral region 100b and the step region SC. The first dummy pillars 118 in the peripheral region 100b penetrate the oxide layer 108 and the first conductive layer 104, while the first dummy pillars 118 in the step region SC penetrate the oxide layer 108, the second initial stack structure ST2, and the first conductive layer 104. In Figure 2D , the first conductive layer 104, the sacrificial layer 106b, and the oxide layer 108 are omitted for clarity and ease of understanding.

Specifically, in this embodiment, in the peripheral region 100b, first dummy pillars 118 extend downward from the top surface of the oxide layer 108, through the oxide layer 108 and the first conductive layer 104. Furthermore, in the step region SC, first dummy pillars 118 extend downward from the top surface of the oxide layer 108, through the oxide layer 108, the corresponding terrace portion of the second initial stacking structure ST2, and the first conductive layer 104. In this embodiment, the material of the first dummy pillars 118 may be an oxide. The first dummy pillars 118 in the step region SC can provide support for the second initial stacking structure ST2 in the step region SC. The method for forming the first dummy pillars 118 is well known to those skilled in the art and will not be further described herein.

In this embodiment, the first dummy pillar 118 is a pillar made of oxide, but the present invention is not limited thereto. In other embodiments, the first dummy pillar 118 may have other structures depending on the actual situation.

For example, as shown in FIG3A , spacers 122 can be formed within first dummy pillars 118 formed of oxide. The material of spacers 122 can be polysilicon or nitride. In this embodiment, when spacers 122 are made of nitride, since first dummy pillars 118 contain only a small amount of nitride, semiconductor devices (particularly P-type metal oxide semiconductor transistors) within circuit structure layer 102 will not experience a critical voltage shift after subsequent heat treatment. Furthermore, in another embodiment, as shown in FIG3B , air gaps AG1 can be formed within first dummy pillars 118.

Furthermore, in other embodiments, after forming the first dummy pillar 118, a via hole may be formed in the first dummy pillar 118 as needed. This is well known to those skilled in the art and will not be further described here.

Next, referring to both Figures 1E and 2E , after forming the first dummy pillar 118, a first slit SLT1 and a plurality of parallel second slits SLT2 are formed in the oxide layer 108. In this embodiment, the first slit SLT1 penetrates the oxide layer 108 and the first conductive layer 104 and surrounds the second initial stack structure ST2. Furthermore, the second slits SLT2 penetrate the oxide layer 108, the second initial stack structure ST2, and the first conductive layer 104 to divide the second initial stack structure ST2 into a plurality of parallel blocks. The first slit SLT1 is not connected to the second slits SLT2. In Figure 2E , the number and layout of the blocks are exemplary only and are not intended to limit the present invention. Furthermore, in Figure 2E , the first conductive layer 104, sacrificial layer 106b, and oxide layer 108 are omitted for clarity and ease of understanding.

Specifically, in this embodiment, the first slit SLT1 extends downward from the top surface of the oxide layer 108, through the oxide layer 108 and the first conductive layer 104, and is located in the memory device region 100a, adjacent to the boundary between the memory device region 100a and the peripheral region 100b. The slit is spaced a distance from the bottommost sacrificial layer 106b in the second initial stack structure ST2. However, the present invention is not limited thereto. In other embodiments, the first slit SLT1 may be located in the peripheral region 100b, adjacent to the boundary between the memory device region 100a and the peripheral region 100b. Alternatively, the first slit SLT1 may be located at the boundary between the memory device region 100a and the peripheral region 100b.

In this embodiment, the second slit SLT2 extends downward from the top surface of the oxide layer 108 through the oxide layer 108, the second initial stack structure ST2, and the first conductive layer 104, thereby dividing the second initial stack structure ST2 into a plurality of blocks arranged parallel to each other. In each block, the first dummy pillars 118 are located on a first side of the memory array region AR, and the support pillars 116 are located on a second side of the memory array region AR, opposite the first side. For example, as shown in FIG2E , in the blocks of the first and third rows, the first dummy pillar 118 is located on the right side of the memory array area AR, and the support pillar 116 is located on the left side of the memory array area AR. In the blocks of the second row, the first dummy pillar 118 is located on the left side of the memory array area AR, and the support pillar 116 is located on the right side of the memory array area AR. However, the present invention is not limited to this. Furthermore, the first dummy pillar 118 in each block is adjacent to the support pillar 116 in the adjacent block, and the support pillar 116 in each block is adjacent to the first dummy pillar 118 in the adjacent block. In other embodiments, depending on actual needs, the support pillars 116 and the first dummy pillars 118 may have other layout designs. Alternatively, the second slit SLT2 may not be formed.

Next, after forming the first and second slits SLT1 and SLT2, a replacement process and charge storage structure formation step are performed through the first and second slits SLT1 and SLT2 to replace the sacrificial layer 106b in the second initial stack structure ST2 with the second conductive layer 120 and form a charge storage structure between the second conductive layer 120 and the channel layer CH. The above-mentioned replacement process and charge storage structure formation step are well known to those skilled in the art and will not be further described here.

As a result, a stacked structure ST3 composed of a plurality of alternating insulating layers 106a and a plurality of second conductive layers 120 is formed on the first conductive layer 104 in the memory device region 100a. The stacked structure ST3 has the same step profile as the second initial stacked structure ST2. Furthermore, the formed stacked structure ST3 is surrounded by an oxide layer 108.

In Figure 1E , the charge storage structure is not shown for clarity. The charge storage structure can be a composite structure composed of an oxide layer, a nitride layer, and an oxide layer. When the semiconductor structure of this embodiment is applied to a three-dimensional memory, the second conductive layer 120 in the memory array region AR can serve as the gate of the three-dimensional memory, while in the step region SC, the second conductive layer 120 can serve as the word line of the three-dimensional memory.

After performing the above-mentioned replacement process and charge storage structure formation step, an insulating material is filled into the first slit SLT1 and the second slit SLT2 to form a first insulating wall 124a in the first slit SLT1 and a second insulating wall 124b in the second slit SLT2. Specifically, in this embodiment, a first insulating wall 124a is formed in the oxide layer 108, penetrating the oxide layer 108 and the first conductive layer 104 and surrounding the stacked structure ST3. The first insulating wall 124a is located in the memory device region 100a, adjacent to the boundary between the memory device region 100a and the peripheral region 100b, and spaced a distance from the bottom-most second conductive layer 120 in the stacked structure ST3. Thus, a three-dimensional memory device including the semiconductor structure of the present invention is formed.

In this embodiment, the material of the first insulating wall 124a and the second insulating wall 124b may be oxide or nitride, but the present invention is not limited thereto. In other embodiments, the first insulating wall 124a and the second insulating wall 124b may have other structures depending on the actual situation.

For example, as shown in FIG4A , the polysilicon layer 126 can be formed within a first insulating wall 124 a and a second insulating wall 124 b made of oxide or nitride. If the first insulating wall 124 a and the second insulating wall 124 b are made of nitride, since the first insulating wall 124 a and the second insulating wall 124 b are not large-scale components, i.e., there is no large amount of nitride present, the semiconductor components (particularly P-type metal oxide semiconductor transistors) in the circuit structure layer 102 will not experience a critical voltage shift after subsequent thermal treatment. In addition, in another embodiment, as shown in FIG4B , the air gap AG2 may be formed in the first insulating wall 124a and the second insulating wall 124b.

In this embodiment, the first dummy pillars 118 are formed after the vertical channel structure 110 and the supporting pillars 116 are formed, but the present invention is not limited thereto. In other embodiments, the first dummy pillars 118 may be formed before the vertical channel structure 110 and the supporting pillars 116 are formed. Specifically, after the oxide layer 108 shown in FIG. 1B is formed, the first dummy pillars 118 are formed in the peripheral region 100b and the step region SC. After the first dummy pillars 118 are formed, the vertical channel structure 110 is formed in the memory array region AR, and the supporting pillars 116 are formed in the step region SC. Thereafter, the steps described in FIG. 1E and FIG. 2E are performed.

Figures 5A to 5E are schematic cross-sectional views of the fabrication process for a semiconductor structure for a three-dimensional memory device according to a second embodiment of the present invention. In this embodiment, components identical to those in the first embodiment are denoted by the same reference numerals and will not be further described.

First, referring to Figure 5A , after forming the first initial stacking structure ST1 shown in Figure 1A , portions of the insulating layer 106a and sacrificial layer 106b are removed to form a second initial stacking structure ST2 in the memory device region 100a , while retaining the first initial stacking structure ST1 in the peripheral region 100b . Furthermore, in this embodiment, the first conductive layer 104 in the memory device region 100a adjacent to the boundary between the peripheral region 100b and the memory device region 100a is exposed.

Then, a first oxide material layer 500 is formed on the substrate 100 to cover the second initial stack structure ST2 in the memory device region 100a, the first initial stack structure ST1 in the peripheral region 100b, and the exposed first conductive layer 104. In this embodiment, the first oxide material layer 500 is a silicon oxide layer. The first oxide material layer 500 can be formed, for example, by forming an oxide material layer on the substrate 100 and then performing a planarization process to ensure that the formed first oxide material layer 500 has a flat top surface. The planarization process can be, for example, a chemical mechanical polishing process.

Next, referring to FIG5B , as described in FIG1C , after forming the first oxide material layer 500 , a plurality of vertical channel structures 110 are formed in the memory array region AR, and a plurality of supporting pillars 116 are simultaneously formed in the step region SC.

After forming the vertical channel structure 110 and support pillars 116, a plurality of first dummy pillars 118 are formed in the peripheral region 100b and the step region SC. In this embodiment, in the peripheral region 100b, the first dummy pillars 118 penetrate the first oxide material layer 500, the first initial stacking structure ST1, and the first conductive layer 104. In the step region SC, the first dummy pillars 118 penetrate the first oxide material layer 500, the second initial stacking structure ST2, and the first conductive layer 104.

Specifically, in this embodiment, in the peripheral region 100 b, the first dummy pillar 118 extends downward from the top surface of the first oxide material layer 500 through the first oxide material layer 500, the first initial stacking structure ST1, and the first conductive layer 104. Furthermore, in the step region SC, the first dummy pillar 118 extends downward from the top surface of the first oxide material layer 500 through the first oxide material layer 500, the corresponding stepped portion of the second initial stacking structure ST2, and the first conductive layer 104. The first dummy pillars 118 located in the peripheral region 100b can be used to provide support for the first initial stacking structure ST1 in the peripheral region 100b, and the first dummy pillars 118 located in the step region SC can be used to provide support for the second initial stacking structure ST2 in the step region SC.

Then, referring to FIG. 5C , a plurality of holes H are formed in the peripheral region 100b, penetrating the first oxide material layer 500, the first initial stacking structure ST1, and the first conductive layer 104. Specifically, in this embodiment, the holes H extend downward from the top surface of the first oxide material layer 500 through the first oxide material layer 500, the first initial stacking structure ST1, and the first conductive layer 104, exposing the sacrificial layer 106b in the first initial stacking structure ST1.

Next, referring to Figure 5D , after forming the hole H, a replacement process is performed through the hole H to replace the sacrificial layer 106b in the peripheral region 100b with the second oxide material layer 502. In this way, the first oxide material layer 500, the second oxide material layer 502, and the insulating layer 106a form an oxide layer 504 covering the first conductive layer 104 in the peripheral region 100b. Subsequently, the hole H is filled with an oxide material to form a second dummy pillar 506.

As a result, the peripheral region 100b contains an oxide layer 504 and the first and second dummy pillars 118 and 506 formed of oxide material, but no nitride layer (sacrificial layer 106b) exists. In other words, the stacked structure in the peripheral region 100b consists of the stacked insulating layer 106a and the second oxide material layer 502.

In the semiconductor structure of the present invention formed in this step, an oxide layer exists in the peripheral region 100b, but no nitride layer. Therefore, subsequent heat treatment of the semiconductor structure of the present invention will not cause a critical voltage shift in the semiconductor devices (particularly P-type metal oxide semiconductor transistors) in the circuit structure layer 102.

In this embodiment, the second dummy pillar 506 is a pillar made of oxide, but the present invention is not limited thereto. In other embodiments, the second dummy pillar 506 may have other structures depending on the actual situation.

For example, as shown in FIG6A , a polysilicon layer 508 may be formed in a second dummy pillar 506 formed of oxide. Furthermore, in another embodiment, as shown in FIG6B , a spacer layer 510 may be formed in the second dummy pillar 506 formed of oxide. The material of the spacer layer 510 may be polysilicon or nitride. Furthermore, in another embodiment, as shown in FIG6C , an air gap AG3 may be formed in the second dummy pillar 206.

Next, referring to Figure 5E , after forming the second dummy pillar 206, a first slit SLT1 and a plurality of parallel second slits SLT2 are formed in the first oxide material layer 500. A replacement process and charge storage structure formation step are performed using the first slit SLT1 and the second slits SLT2 to replace the sacrificial layer 106b in the second initial stack structure ST2 with the second conductive layer 120, and to form a charge storage structure between the second conductive layer 120 and the channel layer CH.

As a result, a stacked structure ST3 composed of a plurality of alternating insulating layers 106a and a plurality of second conductive layers 120 is formed on the first conductive layer 104 in the memory device region 100a. The stacked structure ST3 has the same step profile as the second initial stacked structure ST2. Furthermore, the formed stacked structure ST3 is surrounded by an oxide layer 504.

After the replacement process and charge storage structure formation steps described above, insulating material is filled into the first slit SLT1 and the second slit SLT2 to form a first insulating wall 124a in the first slit SLT1 and a second insulating wall 124b in the second slit SLT2. In this way, a three-dimensional memory device including the semiconductor structure of the present invention is formed.

In this embodiment, the first dummy pillars 118 are formed after forming the vertical channel structure 110 and the supporting pillars 116, but the present invention is not limited thereto. In other embodiments, the first dummy pillars 118 may be formed before forming the vertical channel structure 110 and the supporting pillars 116. Thereafter, the steps described in Figures 1E and 2E are performed to form a three-dimensional memory including the semiconductor structure of the present invention.

In summary, in the semiconductor structure for three-dimensional memory and its fabrication method of the present invention, the nitride layer is removed from the initial stacked structure in the peripheral region surrounding the memory device area, eliminating the stacked structure of oxide and nitride layers in the peripheral region. Consequently, after subsequent heat treatment, the nitride layer in the peripheral region can be effectively prevented from causing a critical voltage shift in semiconductor devices (particularly P-type metal oxide semiconductor transistors) in the circuit structure layer.

Furthermore, even though nitride material (e.g., nitride spacers) may be present in peripheral devices (e.g., dummy pillars), the presence of such material is minimal. Therefore, subsequent thermal treatment does not cause a critical voltage shift in semiconductor devices (particularly P-type metal oxide semiconductor transistors) within the circuit structure layer.

The following describes the circuit structure of a three-dimensional memory array MSC including the semiconductor structure of this embodiment.

FIG7 is a circuit diagram of a 3D AND flash memory array including the semiconductor structure of this embodiment.

Referring to Figure 7 , two blocks, BLOCK ⁽ⁱ⁾ and BLOCK ^(i+1), of a vertical AND memory array MSC are arranged in rows and columns. Block BLOCK ⁽ⁱ⁾ includes memory array MSC1. A column (e.g., column m+1) of memory array MSC1 is a collection of AND memory cells MC that share a common word line (e.g., WL ⁽ⁱ⁾ _m+1 ). The AND memory cells MC in each column (e.g., the m+1th column) of the memory array MSC1 correspond to a common word line (e.g., WL ⁽ⁱ⁾ _m+1 ) and are coupled to different source poles (e.g., SP ⁽ⁱ⁾ _n and SP ⁽ⁱ⁾ _n+1 ) and drain poles (e.g., DP ⁽ⁱ⁾ _n and DP ⁽ⁱ⁾ _n+1 ), such that the AND memory cells MC are logically arranged in a row along the common word line (e.g., WL ⁽ⁱ⁾ _m+1 ).

A row (e.g., the nth row) of memory array MSC1 is a collection of AND memory cells MC having a common source pole (e.g., SP ⁽ⁱ⁾ _n ) and a common drain pole (e.g., DP ⁽ⁱ⁾ _n ). The AND memory cells MC in each row (e.g., the nth row) of memory array MSC1 correspond to different word lines (e.g., WL ⁽ⁱ⁾ _m+1 and WL ⁽ⁱ⁾ _m ) and are coupled to a common source pole (e.g., SP ⁽ⁱ⁾ _n ) and a common drain pole (e.g., DP ⁽ⁱ⁾ _n ). Therefore, the AND memory cells MC in memory array MSC1 are logically arranged in a row along the common source pole (e.g., SP ⁽ⁱ⁾ _n ) and the common drain pole (e.g., DP ⁽ⁱ⁾ _n ). In the physical layout, depending on the fabrication method used, the rows or columns may be twisted, arranged in a honeycomb pattern or otherwise for high density or other reasons.

In FIG7 , in block BLOCK ⁽ⁱ⁾ , the AND memory cells MC in the nth row of memory array MSC1 share a common source pole (e.g., SP ⁽ⁱ⁾ _n ) and a common drain pole (e.g., DP ⁽ⁱ⁾ _n ). The AND memory cells MC in the n+1th row share a common source pole (e.g., SP ⁽ⁱ⁾ _n+1 ) and a common drain pole (e.g., DP ⁽ⁱ⁾ _n+1 ).

A common source pillar (e.g., SP ⁽ⁱ⁾ _n ) is coupled to a common source line (e.g., _SLn ); a common drain pillar (e.g., DP ⁽ⁱ⁾ _n ) is coupled to a common bit line (e.g., _BLn ). A common source pillar (e.g., SP ⁽ⁱ⁾ _n+1 ) is coupled to a common source line (e.g., SLn ₊₁ ); a common drain pillar (e.g., DP ⁽ⁱ⁾ _n+1 ) is coupled to a common bit line (e.g., BLn ₊₁ ).

Similarly, block BLOCK ⁽ⁱ⁺¹⁾ includes a memory array MSC2, which is similar to memory array MSC1 in block BLOCK ⁽ⁱ⁾ . A row (e.g., row m+1) of memory array MSC2 is a set of AND memory cells MC having a common word line (e.g., WL ⁽ⁱ⁺¹⁾ _m+1 ). The AND memory cells MC in each row (e.g., row m+1) of memory array MSC2 correspond to the common word line (e.g., WL ⁽ⁱ⁺¹⁾ _m+1 ) and are coupled to different source poles (e.g., SP ⁽ⁱ⁺¹⁾ _n and SP ⁽ⁱ⁺¹⁾ _n+1 ) and drain poles (e.g., DP ⁽ⁱ⁺¹⁾ _n and DP ⁽ⁱ⁺¹⁾ _n+1 ). A row (e.g., the nth row) of memory array MSC2 comprises a set of AND memory cells MC having a common source (e.g., SP ⁽ⁱ⁺¹⁾ _n ) and a common drain (e.g., DP ⁽ⁱ⁺¹⁾ _n ). These AND memory cells MC are connected in parallel and are also referred to as a memory string. The AND memory cells MC in each row (e.g., the nth row) of memory array MSC2 correspond to different word lines (e.g., WL ⁽ⁱ⁺¹⁾ _m+1 and WL ⁽ⁱ⁺¹⁾ _m ) and are coupled to a common source (e.g., SP ⁽ⁱ⁺¹⁾ _n ) and a common drain (e.g., DP ⁽ⁱ⁺¹⁾ _n ). Therefore, the AND memory cells MC of the memory array MSC2 are logically arranged in a row along a common source pole (eg, SP ⁽ⁱ⁺¹⁾ _n ) and a common drain pole (eg, DP ⁽ⁱ⁺¹⁾ _n ).

Blocks BLOCK ⁽ⁱ⁺¹⁾ and BLOCK ⁽ⁱ⁾ share a common source line (e.g., SL _n and SL _n+1 ) and a common bit line (e.g., BL _n and BL _n+1 ). Therefore, source line SL _n and bit line BL _n are coupled to the n-th row of AND memory cells MC in AND memory array MSC1 of block BLOCK ⁽ⁱ⁾ , and are also coupled to the n-th row of AND memory cells MC in AND memory array MSC2 of block BLOCK ⁽ⁱ⁺¹⁾ . Similarly, source line SLn ₊₁ and bit line BLn ₊₁ are coupled to the AND memory cell MC in the n+1th row in AND memory array MSC1 of block BLOCK ⁽ⁱ⁾ , and to the AND memory cell MC in the n+1th row in AND memory array MSC2 of block BLOCK ⁽ⁱ⁺¹⁾ .

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary skill in the art may make minor modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: Base

100a: Memory device area

100b: Peripheral area

102: Circuit structure layer

104: First conductive layer

106a: Insulating layer

106b: Sacrifice Layer

108: Oxide layer

AR: Memory Array Area

SC: Stairway Area

ST2: Second initial stacking structure

Claims (10)

A semiconductor structure for three-dimensional memory comprises: a substrate having a memory element region and a peripheral region surrounding the memory element region, wherein the memory element region includes a memory array region and a step region; a circuit structure layer disposed on the substrate; a first conductive layer disposed on the circuit structure layer; a stacked structure disposed on the first conductive layer in the memory element region, comprising a plurality of alternately stacked second conductive layers and a plurality of insulating layers, wherein the stacked structure in the step region has a step profile; an oxide layer disposed on the first conductive layer in the memory element region and the peripheral region, wherein the oxide layer in the peripheral region surrounds the stacked structure; A first insulating wall is disposed in the oxide layer, penetrates the first conductive layer, and surrounds the stacked structure; and a plurality of first dummy pillars are disposed in the peripheral region and the step region, wherein each of the first dummy pillars in the peripheral region penetrates the oxide layer and the first conductive layer, and each of the first dummy pillars in the step region penetrates the stacked structure and the first conductive layer. The semiconductor structure for three-dimensional memory as described in claim 1 further includes a plurality of supporting pillars disposed in the step region and penetrating the stacked structure and the first conductive layer. The semiconductor structure for three-dimensional memory as described in claim 2 further includes a plurality of second insulating walls parallel to each other, disposed in the stacked structure to divide the stacked structure into a plurality of blocks arranged parallel to each other. The semiconductor structure for three-dimensional memory as described in claim 3, wherein in each of the blocks, the first dummy pillar is located on a first side of the memory array region, and the supporting pillar is located on a second side of the memory array region opposite to the first side. The semiconductor structure for a three-dimensional memory as described in claim 4, wherein the first dummy pillar in each of the blocks is adjacent to the supporting pillar in the adjacent block, and the supporting pillar in each of the blocks is adjacent to the first dummy pillar in the adjacent block. The semiconductor structure for three-dimensional memory as described in claim 1 further includes a plurality of vertical channel structures disposed in the memory array region and penetrating the stacked structure and the first conductive layer. The semiconductor structure for three-dimensional memory as described in claim 1, wherein the first insulating wall is located in the memory element region and adjacent to the boundary between the memory element region and the peripheral region, and is spaced a distance from the bottom second conductive layer in the stacked structure. A method for fabricating a semiconductor structure for a three-dimensional memory comprises: Providing a substrate, wherein the substrate has a memory element region and a peripheral region surrounding the memory element region, wherein the memory element region includes a memory array region and a step region; Forming a circuit structure layer on the substrate; Forming a first conductive layer on the circuit structure layer; Forming a stacked structure on the first conductive layer in the memory element region, wherein the stacked structure includes a plurality of second conductive layers and a plurality of insulating layers stacked alternately, and the stacked structure in the step region has a step profile; An oxide layer is formed on the first conductive layer in the memory device region and the peripheral region, wherein the oxide layer in the peripheral region surrounds the stacked structure; a first insulating wall is formed in the oxide layer, wherein the first insulating wall penetrates the first conductive layer and surrounds the stacked structure; and a plurality of first dummy pillars are formed in the peripheral region and the step region, wherein each of the first dummy pillars in the peripheral region penetrates the oxide layer and the first conductive layer, and each of the first dummy pillars in the step region penetrates the oxide layer, the stacked structure, and the first conductive layer. The method for fabricating a semiconductor structure for a three-dimensional memory as described in claim 8, wherein the method for forming the stacked structure and the oxide layer comprises: forming a first initial stacked structure on the first conductive layer, wherein the first initial stacked structure comprises the plurality of insulating layers and the plurality of sacrificial layers stacked alternately; removing portions of the insulating layers and portions of the sacrificial layers to expose the first conductive layer in the peripheral region, and forming a second initial stacked structure in the memory device region, wherein the second initial stacked structure in the step region has the step profile; forming the oxide layer on the first conductive layer; and replacing the plurality of sacrificial layers with the plurality of second conductive layers. The method for fabricating a semiconductor structure for a three-dimensional memory as described in claim 9 further comprises: after forming the oxide layer and before replacing the plurality of sacrificial layers with the plurality of second conductive layers; forming a plurality of vertical channel structures in the memory array region, wherein each of the vertical channel structures penetrates the second initial stacking structure and the first conductive layer.