TWI853399B - Semiconductor structure and method for manufacturing the same - Google Patents

Abstract

A semiconductor structure is provided. The semiconductor structure has a device region and a periphery region adjacent to the device region. The periphery region comprises an array contact defining region and a periphery contact defining region. The semiconductor structure comprises a substrate, a staircase structure, an etch stop layer, a plurality of array contacts, and a plurality of periphery contacts. The staircase structure is disposed on the substrate in the periphery region. The staircase structure comprises conductive layers and dielectric layers disposed alternately. The etch stop layer is disposed on the staircase structure in the array contact defining region. The array contacts are disposed on the staircase structure and through the etch stop layer in the array contact defining region. The periphery contacts are through the staircase structure in the periphery contact defining region.

Description

Semiconductor structure and method for manufacturing the same

The present disclosure relates to a semiconductor structure and a method for manufacturing the same. The present disclosure particularly relates to a semiconductor structure including an array contact and a peripheral contact and a method for manufacturing the same.

Cost has always been an important issue in the manufacturing industry. For example, deep etching processes are expensive processes in semiconductor manufacturing. In the peripheral area of 3D memory devices, virtual active structures, array contacts, and peripheral contacts used to support a high stacking structure are usually formed by deep etching processes, respectively. In this case, the cost will increase as the number of layers in the stacking structure increases.

This disclosure is dedicated to using a common process to form several components that must be manufactured using a deep etching process, thereby reducing costs.

According to some embodiments, the present disclosure provides a semiconductor structure. The semiconductor structure has a device area and a peripheral area, and the peripheral area is adjacent to the device area. The peripheral area includes an array contact definition area and a peripheral contact definition area. The semiconductor structure includes a substrate, a step structure, an etch stop layer, a plurality of array contacts, and a plurality of peripheral contacts. The step structure is disposed on the substrate in the peripheral area. The step structure includes a plurality of conductive layers and a plurality of dielectric layers alternately disposed with each other. The etch stop layer is disposed on the step structure in the array contact definition area. The array contacts are disposed on the step structure in the array contact definition area and pass through the etch stop layer. The peripheral contacts pass through the step structure in the peripheral contact definition area.

According to some embodiments, the present disclosure provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure is used to manufacture a semiconductor structure. The semiconductor structure has a device area and a peripheral area, and the peripheral area is adjacent to the device area. The peripheral area includes an array contact definition area and a peripheral contact definition area. The method for manufacturing a semiconductor structure includes the following steps. First, a portion of a forming structure is provided. The portion of the forming structure includes a substrate and an initial step structure, and the initial step structure is located on the substrate in the peripheral area. The initial step structure includes a plurality of sacrificial layers and a plurality of dielectric layers alternately arranged with each other. An etch stop layer is formed on the initial step structure in the array contact definition area. Next, the sacrificial layer of the initial step structure is replaced by a plurality of conductive layers to form a step structure, wherein the conductive layers and the dielectric layers are alternately arranged. A plurality of array contacts are formed in the array contact definition region on the step structure and through the etch stop layer, and a plurality of peripheral contacts are formed in the peripheral contact definition region through the step structure.

In order to better understand the above and other aspects of this disclosure, the following is a specific example, and the attached drawings are used to explain in detail as follows:

10:Semiconductor structure

100: Substrate

102: Circuit layer

104: Bottom conductive layer

106: Connectors

200: Step structure

202: Conductive layer

204: Dielectric layer

206: Etch stop layer

208: Array contacts

208A: Part I

208B: Part 2

210: Peripheral contacts

210A: Part 1

210B: Part 2

212: Interlayer dielectric layer

214: First compartment

216: Second compartment

300: stack

302: Conductive layer

304: Dielectric layer

306: Active structure

308: Memory layer

310: Channel layer

312: Dielectric materials

314: Contacts

316: Connection structure

318: Barrier layer

320: Conductive materials

322: Plug

324: Top interlayer dielectric layer

326: Top interlayer dielectric layer

400:Layered structure

402: First bottom etch stop layer

404: first bottom dielectric layer

406: Bottom sacrificial layer

408: Second bottom dielectric layer

410: Second bottom etch stop layer

412: Initial stack

414: Sacrifice layer

416: Initial ladder structure

418: Sacrifice layer

420: Interlayer dielectric material

422: Sacrificial materials

424: Etch stop material

426: Interlayer

428: Sacrificial materials

430: Mask layer

432: Partial

D: The broken part

M: Memory cell

O1: First opening

O2: Second opening

R1: Array contact definition area

R2: Peripheral contact definition area

T: Groove

Figures 1A-1D illustrate an exemplary semiconductor structure according to an embodiment.

Figures 2A-2B to 21A-21D illustrate various stages of a method for manufacturing an exemplary semiconductor structure according to an embodiment.

A more complete description of various embodiments will be provided below with the accompanying drawings. The following description and the accompanying drawings are provided for illustrative purposes only and are not intended to be limiting. For the sake of clarity, elements may not be drawn in actual proportion. In addition, some elements and/or symbols may be omitted in some drawings. It is expected that elements and features of one embodiment can be advantageously incorporated into another embodiment without further elaboration.

The present disclosure provides a semiconductor structure. The semiconductor structure has a device area and a peripheral area, and the peripheral area is adjacent to the device area. The peripheral area includes an array contact definition area and a peripheral contact definition area. The semiconductor structure includes a substrate, a step structure, an etch stop layer, a plurality of array contacts, and a plurality of peripheral contacts. The step structure is arranged on the substrate in the peripheral area. The step structure includes a plurality of conductive layers and a plurality of dielectric layers arranged alternately with each other. The etch stop layer is arranged on the step structure in the array contact definition area. The array contacts are disposed on the step structure in the array contact definition area and pass through the etch stop layer. The peripheral contacts pass through the step structure in the peripheral contact definition area.

For more details, please refer to FIGS. 1A-1D, which illustrate an exemplary semiconductor structure 10, wherein FIG. 1A is a cross-sectional view of the device region, FIG. 1B is a cross-sectional view of the peripheral region, FIG. 1C is a top view of the peripheral region, and FIG. 1D is another cross-sectional view of the peripheral region. FIG. 1B and FIG. 1D correspond to the 1-1' line and the 2-2' line in FIG. 1C, respectively.

The semiconductor structure 10 includes a substrate 100. According to some embodiments, the semiconductor structure 10 may further include a circuit layer 102 disposed on the substrate 100 across the device region and the peripheral region. The circuit layer 102 may include various electronic devices (not shown here), such as but not limited to metal oxide semiconductor (MOS) devices, etc. According to some embodiments, the semiconductor structure 10 may further include a bottom conductive layer 104 disposed on the substrate 100. The bottom conductive layer 104 may be disposed on the circuit layer 102. According to some embodiments, the semiconductor structure 10 may further include a plurality of connectors 106 disposed on the circuit layer 102. The connectors 106 are connected to the circuit layer 102. More specifically, connector 106 is coupled to electronic devices in circuit layer 102.

The present disclosure focuses on the peripheral region of the semiconductor structure 10 shown in Figures 1B-1D. The peripheral region is adjacent to the device region. In some embodiments, the peripheral region surrounds the device region. The peripheral region includes an array contact definition region R1 and a peripheral contact definition region R2, and Figures 1B and 1D correspond to the array contact definition region R1 and the peripheral contact definition region R2, respectively. The array contact definition region R1 and the peripheral contact definition region R2 are parallel to each other and extend continuously in a first direction (i.e., the X direction in the figure) across multiple steps of the step structure 200. In some embodiments, the peripheral contact element definition region R2 is divided into two separate regions, and the array contact element definition region R1 is located between the two separate regions in a second direction (i.e., the Y direction in the figure). The first direction and the second direction are perpendicular to each other.

In the peripheral region, the semiconductor structure 10 includes a step structure 200. The step structure 200 is disposed on the substrate 100. The step structure 200 may be disposed on the circuit layer 102 and/or the bottom conductive layer 104 (if any). The step structure 200 includes a plurality of conductive layers 202 and a plurality of dielectric layers 204 alternately disposed with each other. Specifically, each step of the step structure 200 includes a conductive layer 202 and a dielectric layer 204. The conductive layer 202 may form a step of the step structure 200.

The semiconductor structure 10 includes an etch stop layer 206 disposed on the step structure 200 in the array contact definition region R1. The etch stop layer 206 may be formed of a non-conductive material that is selective to polysilicon, nitride, and oxide during an etching process, such as carbon-doped silicon nitride (sometimes referred to as SiCN). The etch stop layer 206 facilitates accurate definition of the array contacts on each step.

The semiconductor structure 10 includes a plurality of array contacts 208 and a plurality of peripheral contacts 210. The array contacts 208 are disposed on the step structure 200 in the array contact definition region R1 and pass through the etch stop layer 206. Each of the array contacts 208 may stop on the conductive layer 202 of the corresponding step and be connected to the conductive layer 202. Each of the array contacts 208 may have a first portion 208A and a second portion 208B, the second portion 208B being located below the first portion 208A, and the cross-sectional area of the second portion 208B being smaller than the cross-sectional area of the first portion 208A.

The peripheral contact 210 passes through the step structure 200 in the peripheral contact definition area R2. The peripheral contact 210 can be connected to the connector 106 and further connected to the circuit layer 102 through the connector 106. Each of the peripheral contacts 210 can have a first portion 210A and a second portion 210B, the second portion 210B is located below the first portion 210A, and the cross-sectional area of the second portion 210B is smaller than the cross-sectional area of the first portion 210A. In the present disclosure, the peripheral contact 210 also replaces the traditional virtual active structure to support a high stacking structure (i.e., the step structure 200).

In some embodiments, the upper surface of the array contact 208 can be flush with the upper surface of the peripheral contact 210. In some embodiments, each of the array contacts 208 is surrounded by four peripheral contacts 210 that are closest to the array contact 208.

According to some embodiments, the semiconductor structure 10 may further include an interlayer dielectric layer 212 located on the step structure 200 and the etch stop layer 206. The array contacts 208 and the peripheral contacts 210 also pass through the interlayer dielectric layer 212. According to some embodiments, the semiconductor structure 10 may further include a plurality of first spacers 214 and a plurality of second spacers 216. The first spacers 214 surround the array contacts 208. The second spacers 216 surround the peripheral contacts 210. More specifically, the first spacer layer 214 may completely cover the side walls and the bottom surface of the first portion 208A of the array contact 208, and further extend to a portion of the side walls of the second portion 208B. The second spacer layer 216 may completely cover the side walls and the bottom surface of the first portion 210A of the peripheral contact 210, and further extend to a portion of the side walls of the second portion 210B.

Please return to Figure 1A. The configuration of the device area depends on the type of the semiconductor structure 10. For example, in the device area, the semiconductor structure 10 may include a memory array, in particular a 3D memory array, such as a 3D NAND array, etc. Specifically, the semiconductor structure 10 may include a stack 300 disposed on the substrate 100 in the device area. The stack 300 includes a plurality of conductive layers 302 and a plurality of dielectric layers 304 arranged alternately with each other. It is understood that the step structure 200 disposed in the peripheral area may be an extension of the stack 300. In some embodiments, the conductive layer 302 may include a high dielectric constant material, a barrier material, and a metal gate material.

The semiconductor structure 10 may include a plurality of active structures 306 passing through the stack 300. Each of the active structures 306 may include a memory layer 308, a channel layer 310, a dielectric material 312, and a contact 314. The memory layer 308 is formed as the outermost layer of the active structure 306. The channel layer 310 is disposed along the memory layer 308. The dielectric material 312 is disposed in the space defined by 310. The contact 314 is disposed on the dielectric material 312. A plurality of memory cells M are defined by a plurality of intersections of the conductive layer 302 and the active structure 306 in the stack 300.

The semiconductor structure 10 may further include a connection structure 316 that passes through the stack 300 and stops in the bottom conductive layer 104. The connection structure 316 is electrically connected to the bottom conductive layer 104. In some embodiments, the memory layer 308 of the active structure 306 may have a disconnected portion in the bottom conductive layer 104 so that the channel layer 310 of the active structure 306 is connected by the bottom conductive layer 104. In this way, the connection structure 316 can be coupled to the channel layer 310 through the bottom conductive layer 104. The connection structure 316 may include a barrier layer 318, a conductive material 320, and a plug 322. The barrier layer 318 is formed as the outermost layer of the connection structure 316. The conductive material 320 is disposed in the space defined by the barrier layer 318. The plug 322 is disposed on the conductive material 320.

According to some embodiments, the semiconductor structure 10 may further include a top interlayer dielectric layer 324 located on the stack 300 and the active structure 306. According to some embodiments, the semiconductor structure 10 may further include another top interlayer dielectric layer 326 located on the top interlayer dielectric layer 324 and the connection structure 316.

The present disclosure also provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure is used to manufacture a semiconductor structure. The semiconductor structure has a device area and a peripheral area, and the peripheral area is adjacent to the device area. The peripheral area includes an array contact definition area and a peripheral contact definition area. The method for manufacturing the semiconductor structure includes the following steps. First, a partial forming structure is provided. The partial forming structure includes a substrate and an initial step structure, and the initial step structure is located on the substrate in the peripheral area. The initial step structure includes a plurality of sacrificial layers and a plurality of dielectric layers alternately arranged with each other. An etch stop layer is formed on the initial step structure in the array contact definition area. Next, the sacrificial layer of the initial step structure is replaced by a plurality of conductive layers to form a step structure, wherein the conductive layers and the dielectric layers are alternately arranged. A plurality of array contacts are formed in the array contact definition region on the step structure and through the etch stop layer, and a plurality of peripheral contacts are formed in the peripheral contact definition region through the step structure.

For more details, please refer to Figures 2A-2B to 21A-21D, which illustrate various stages of an exemplary method for manufacturing a semiconductor structure for manufacturing a semiconductor structure 10, wherein the figures indicated by the same number are at the same stage, the figure indicated by "A" is a cross-sectional view of the device area, the figure indicated by "B" is a cross-sectional view of the peripheral area, the figure indicated by "C" (if any) is a top view of the peripheral area, the figure indicated by "D" (if any) is another cross-sectional view of the peripheral area, and the figures indicated by "B" and "D" correspond to the 1-1' line and the 2-2' line in the figure indicated by "C", respectively.

As shown in FIGS. 2A-2B, a partially formed structure is provided. The partially formed structure includes a substrate 100. The partially formed structure may further include a circuit layer 102 located on the substrate 100. According to some embodiments, the partially formed structure may include a stacked structure 400 located on the circuit layer 102. The stacked structure 400 includes a first bottom etch stop layer 402, a first bottom dielectric layer 404, a bottom sacrificial layer 406, a second bottom dielectric layer 408, and a second bottom etch stop layer 410 arranged in sequence. The first bottom etch stop layer 402 may be formed of polysilicon. The first bottom dielectric layer 404 may be formed of oxide. The bottom sacrificial layer 406 may be formed of polysilicon. The second bottom dielectric layer 408 may be formed of oxide. The second bottom etch stop layer 410 may be formed of polysilicon. The partially formed structure may include a plurality of connectors 106 located on the circuit layer 102 and passing through the stacked structure 400. The connectors 106 may be formed of tungsten.

The partially formed structure may further include an initial stack 412 located on the substrate 100 in the device region. The initial stack 412 includes a plurality of sacrificial layers 414 and a plurality of dielectric layers 304 arranged alternately with each other. The partially formed structure includes an initial step structure 416 located on the substrate 100 in the peripheral region. The initial step structure 416 includes a plurality of sacrificial layers 418 and a plurality of dielectric layers 204 arranged alternately with each other. Each step of the initial step structure 416 includes a sacrificial layer 418 and a dielectric layer 204. The sacrificial layer 418 forms a step of the step structure 200. It is understood that the initial step structure 416 may be an extension of the initial stack 412. In this case, the initial step structure 416 may be formed by a trimming process of an extension portion of the initial stack 412 located in the peripheral region. The sacrificial layers 414 and 418 may be formed of silicon nitride. The dielectric layers 304 and 204 may be formed of oxide.

According to some embodiments, the partially formed structure may further include an interlayer dielectric material 420 located on the initial stack 412. The interlayer dielectric material 420 may be an oxide. According to some embodiments, the partially formed structure may include a sacrificial material 422 located on the interlayer dielectric material 420. The sacrificial material 422 may be polysilicon.

As shown in FIGS. 3A-3C , an etch stop material 424 is formed on the entire structure. The etch stop material 424 is non-conductive and is selective to polysilicon, nitride, and oxide during the etching process. For example, the etch stop material 424 can be carbon-doped silicon nitride. Next, as shown in FIGS. 4A-4C , the etch stop material 424 in the peripheral area except for the array contact defining area R1 is removed. The etch stop material 424 remaining in the array contact defining area R1 forms an etch stop layer 206.

As shown in FIGS. 5A-5B, an interlayer dielectric layer 212 is formed on the initial step structure 416 and the etch stop layer 206. The interlayer dielectric layer 212 may be formed of an oxide. In some embodiments, the interlayer dielectric layer 212 is also formed in the device region. Next, as shown in FIGS. 6A-6B, the portion of the interlayer dielectric layer 212 in the device region is removed by a planarization process such as a chemical mechanical planarization (CMP) process, using the etch stop material 424 remaining in the device region as a stop layer.

Then, as shown in FIGS. 7A-7B, the etch stop material 424 remaining in the device area is removed, for example, by an etching process. Next, the sacrificial material 422 can be removed, as shown in FIGS. 8A-8B. The top portion of the interlayer dielectric layer 212 in the peripheral area may also be removed, and the structures remaining in the device area and the peripheral area are aligned. The removal step shown in FIGS. 8A-8B can be performed by an etching process.

As shown in FIGS. 9A-9B , a plurality of active structures 306 are formed through the initial stack 412. Each of the active structures 306 may include a memory layer 308, a channel layer 310, a dielectric material 312, and a contact 314. The memory layer 308 is formed as the outermost layer of the active structure 306. The channel layer 310 is disposed along the memory layer 308. The dielectric material 312 is disposed in the space defined by 310. The contact 314 is disposed on the dielectric material 312. In some embodiments, a portion of the interlayer dielectric material 420 is removed to form the active structure 306, and then an additional interlayer dielectric material such as an oxide is provided to cover the active structure 306. In this way, a top interlayer dielectric layer 324 as shown in FIGS. 1A-1D is formed in the device region.

As shown in FIGS. 10A-10D , a plurality of first openings O1 are formed through the interlayer dielectric layer 212 and the etch stop layer 206 and land on a plurality of steps of the initial step structure 416, and a plurality of second openings O2 are formed through the interlayer dielectric layer 212 and the initial step structure 416. The second openings O2 may land on the connector 106 of the circuit layer 102. By means of the etch stop layer 206, when the second openings O2 used to form the peripheral contact 210 stop at the connector 106, the second openings O2 used to form the array contact 208 may stop precisely at the corresponding step. In this way, the formation of the array contact 208 and the peripheral contact 210 may be performed simultaneously in the subsequent process. It should be noted that, without using the etch stop layer 206, the array contact 208 cannot be formed simultaneously with the deep peripheral contact 210 because the first openings O1 with various heights used in the array contact 208 may be overetched or mislanded when the first openings O1 are formed in the same process as the second openings O2 used in the deep peripheral contact 210. The configuration of the first openings O1 and the second openings O2 depends on the predetermined configuration of the array contact 208 and the peripheral contact 210. For example, each of the first openings O1 may be surrounded by four second openings O2 that are closest to the first opening O1 among the second openings O2.

As shown in FIGS. 11A-11D , a plurality of spacer layers 426 are conformally formed in the first opening O1 and the second opening O2. More specifically, the spacer layers 426 are formed on the sidewalls and the lower surface of the first opening O1 and the second opening O2. The spacer layers 426 may be formed of oxide. The spacer layers 426 are beneficial in preventing a short circuit from occurring between the conductive layer 202 to be formed in a subsequent process and the array contact 208/peripheral contact 210.

As shown in FIGS. 12A-12D , a sacrificial material 428 is filled into the first opening O1 and the second opening O2. The sacrificial material 428 may be polysilicon.

Next, as shown in FIGS. 13A-13C, a plurality of trenches T are formed through the initial stack 412. The trenches T may extend from the device region to a portion of the peripheral region outside the array contact defining region R1 and the peripheral contact defining region R2, as shown in FIG. 13C.

As shown in FIGS. 14A-14C , a mask layer 430 is formed to cover the array contact defining region R1 and the peripheral contact defining region R2. The mask layer 430 may be formed of oxide. A disconnected portion D is formed in the memory layer 308 to expose the channel layer 310. In the process of forming the disconnected portion D, the first bottom dielectric layer 404, the bottom sacrificial layer 406, and the second bottom dielectric layer 408 are removed, and a conductive material such as polysilicon may be filled into the space created by the removal step. The filled conductive material may form the bottom conductive layer 104 as shown in FIGS. 1A-1D together with the remaining first bottom etch stop layer 402 and the second bottom etch stop layer 410. In this way, the channel layer 310 of the active structure 306 can be connected by the bottom conductive layer 104.

As shown in FIGS. 15A-15B, the sacrificial layer 414 of the initial stack 412 and the sacrificial layer 418 of the initial step structure 416 are removed through the trench T. Then, as shown in FIGS. 16A-16B, the conductive layer 202 and the conductive layer 302 can be formed in the space generated by the removal step. For example, the conductive layer 202 and the conductive layer 302 can be formed by sequentially filling a high dielectric constant material, a barrier material, and a metal gate material. In this way, the conductive layer 302 can be formed in the initial stack 412 to form a stack 300, and the stack 300 includes the conductive layer 302 and the dielectric layer 304 arranged alternately with each other. A plurality of memory cells M can be defined by a plurality of intersections of the conductive layer 302 and the active structure 306 in the stack 300. The conductive layer 302 can be used as a word line, etc. In addition, the sacrificial layer 418 of the initial ladder structure 416 can be replaced by a plurality of conductive layers 202 to form a ladder structure 200, and the ladder structure 200 includes conductive layers 202 and dielectric layers 204 arranged alternately with each other.

As shown in FIGS. 17A-17B , a plurality of connection structures 316 are formed in the trench T. Each of the connection structures 316 may include a barrier layer 318, a conductive material 320, and a plug 322. The barrier layer 318 is formed as the outermost layer of the connection structure 316. The barrier layer 318 may be formed of oxide. The conductive material 320 is disposed in the space defined by the barrier layer 318. The conductive material 320 may be polysilicon. The plug 322 is disposed on the conductive material 320. The plug 322 may be formed of metal. The connection structure 316 may serve as a connection structure for a common source line.

As shown in FIGS. 18A-18D , a top interlayer dielectric layer 326 is formed in the device region. The top interlayer dielectric layer 326 can be formed by depositing oxide over the entire structure and then removing the oxide in the peripheral region. The mask layer 430 is removed.

As shown in FIGS. 19A-19D , the sacrificial material 428 is removed. During the removal process, the spacer layer 426 can protect the components in the step structure 200.

As shown in FIGS. 20A-20D, the plurality of portions 432 of the spacer layer 426 located on the lower surface of the first opening O1 and the second opening O2 are opened, wherein in FIG. 20C, for the sake of clarity, these portions 432 are not shown. In this way, the conductive layer 202 is exposed from the first opening O1, and the connector 106 is exposed from the second opening O2. The first spacer layer 214 and the second spacer layer 216 as shown in FIGS. 1A-1D are formed. The opening step shown in FIGS. 20A-20D can be performed by an etching process. In some embodiments, the cross-sectional area of each of the opened portions 432 is smaller than the cross-sectional area of the corresponding first opening O1 or second opening O2.

As shown in FIGS. 21A-21D , a conductive material is filled into the first opening O1 and the second opening O2 to form a plurality of array contacts 208 and a plurality of peripheral contacts 210. Specifically, the array contacts 208 are formed on the step structure 200 and pass through the etch stop layer 206 in the array contact definition region R1, and the peripheral contacts 210 are formed in the peripheral contact definition region R2 and pass through the step structure 200. The conductive material may be tungsten. The excess portion of the conductive material may be removed by a planarization process such as a CMP process. In this way, the upper surface of the array contact 208 is flush with the upper surface of the peripheral contact 210.

According to the present disclosure, array contacts and peripheral contacts can be formed by a common process by using an etch stop layer. Therefore, the cost generated by the deep etching process can be reduced and the yield can be improved. In addition, the peripheral contacts in the present disclosure can provide a supporting function of the traditional virtual active structure. This will help to further reduce the manufacturing cost.

In summary, although the present disclosure has been disclosed as above by the embodiments, it is not intended to limit the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the scope defined by the attached patent application.

10:Semiconductor structure

206: Etch stop layer

208: Array contacts

210: Peripheral contacts

212: Interlayer dielectric layer

214: First compartment

216: Second compartment

316: Connection structure

R1: Array contact definition area

R2: Peripheral contact definition area

Claims (15)

A semiconductor structure has a device region and a peripheral region, the peripheral region is adjacent to the device region, the peripheral region includes an array contact definition region and a peripheral contact definition region, the semiconductor structure includes: a substrate; a step structure disposed on the substrate in the peripheral region, the step structure includes a plurality of conductive layers and a plurality of dielectric layers alternately disposed on the substrate; an etch stop layer disposed on the step structure in the array contact definition region; a plurality of array contacts disposed on the step structure in the array contact definition region and passing through the etch stop layer; and a plurality of peripheral contacts passing through the step structure in the peripheral contact definition region; wherein the array contact definition region and the peripheral The contact defining areas are parallel to each other and extend continuously across multiple steps of the step structure in a first direction; wherein the peripheral contact defining area includes two separate areas, and the array contact defining area is located between the two separate areas in a second direction; and the first direction and the second direction are perpendicular to each other; wherein each of the array contacts is surrounded by four peripheral contacts that are closest to the array contact among the peripheral contacts; and wherein each of the array contacts has a first portion and a second portion, the second portion is located below the first portion and contacts the first portion, and the cross-sectional area of the upper surface of the second portion is smaller than the cross-sectional area of the lower surface of the first portion. A semiconductor structure as described in claim 1, wherein the etch stop layer is formed of carbon-doped silicon nitride. A semiconductor structure as described in claim 1, wherein each of the peripheral contacts has a first portion and a second portion, the second portion is located below the first portion, and the cross-sectional area of the second portion is smaller than the cross-sectional area of the first portion. The semiconductor structure as described in claim 1 further includes: a plurality of first spacer layers surrounding the array contacts; and a plurality of second spacer layers surrounding the peripheral contacts. A semiconductor structure as described in claim 1, wherein the upper surfaces of the array contacts are flush with the upper surfaces of the peripheral contacts. A semiconductor structure as described in claim 1, wherein the conductive layers form the steps of the staircase structure. The semiconductor structure as described in claim 1 further includes: a stack disposed on the substrate in the device region, the stack including a plurality of conductive layers and a plurality of dielectric layers alternately disposed with each other, wherein the step structure disposed in the peripheral region is an extension of the stack; and a plurality of active structures passing through the stack, each of the active structures including: a memory layer formed as the outermost layer of the active structure; a channel layer disposed along the memory layer; a dielectric material disposed in a space defined by the channel layer; and a contact disposed on the dielectric material; wherein a plurality of memory cells are defined by a plurality of intersections of the conductive layers in the stack and the active structures. The semiconductor structure as described in claim 7 further includes: a bottom conductive layer disposed on the substrate, wherein the memory layers of the active structures have disconnected portions in the bottom conductive layer, so that the channel layers of the active structures are connected by the bottom conductive layer; and a connection structure passing through the stack and stopping in the bottom conductive layer, the connection structure being electrically connected to the bottom conductive layer. The semiconductor structure as described in claim 1 further includes: a circuit layer disposed on the substrate, wherein the step structure is disposed on the circuit layer, and the peripheral contacts are connected to a plurality of connectors and further connected to the circuit layer through the connectors. A method for manufacturing a semiconductor structure is used to manufacture a semiconductor structure, the semiconductor structure having a device area and a peripheral area, the peripheral area is adjacent to the device area, the peripheral area includes an array contact definition area and a peripheral contact definition area, the method for manufacturing the semiconductor structure includes: providing a portion of a forming structure, the portion of the forming structure includes a substrate and an initial step structure, the initial step structure is located on the substrate in the peripheral area, the initial step structure includes a plurality of sacrificial layers and a plurality of dielectric layers alternately arranged with each other; forming a plurality of sacrificial layers in the array contact definition area; An etch stop layer is formed on the initial step structure; the sacrificial layers of the initial step structure are replaced by a plurality of conductive layers to form a step structure, wherein the conductive layers and the dielectric layers are alternately arranged; and a plurality of array contacts are formed in the array contact definition region on the step structure and through the etch stop layer, and a plurality of peripheral contacts are formed in the peripheral contact definition region through the step structure; wherein the array contact definition region and the peripheral contact definition region are parallel to each other and extend continuously in a first direction across the step structure. wherein the peripheral contact defining region includes two separate regions, the array contact defining region is located between the two separate regions in a second direction; and the first direction and the second direction are perpendicular to each other; wherein each of the array contacts is surrounded by four peripheral contacts that are closest to the array contacts among the peripheral contacts; and wherein the method for manufacturing the semiconductor structure comprises: forming an interlayer dielectric layer on the initial step structure and the etch stop layer; forming a plurality of first openings through the interlayer dielectric layer and the etch stop layer and falling On a plurality of steps of the initial step structure, a plurality of second openings are formed through the interlayer dielectric layer and the initial step structure; a plurality of spacer layers are conformally formed in the first openings and the second openings; a sacrificial material is filled into the first openings and the second openings; after forming the step structure, the sacrificial material is removed; a plurality of portions of the spacer layers located at the lower surfaces of the first openings and the second openings are opened; a conductive material is filled into the first openings and the second openings to form the array contacts and the peripheral contacts. A method for manufacturing a semiconductor structure as described in claim 10, wherein the array contacts and the peripheral contacts are formed by a common process. A method for manufacturing a semiconductor structure as described in claim 10, wherein the cross-sectional area of each of the opened portions is smaller than the cross-sectional area of the corresponding first opening or the second opening. A method for manufacturing a semiconductor structure as described in claim 10, wherein the partially formed structure further includes an initial stack, the initial stack is located on the substrate in the device region, the initial stack includes a plurality of sacrificial layers and a plurality of dielectric layers arranged alternately with each other, and the method for manufacturing the semiconductor structure further includes: forming a plurality of active structures through the initial stack, each of the active structures including: a memory layer formed as the outermost layer of the active structure; a channel layer arranged along the memory layer; a dielectric material arranged in a space defined by the channel layer; and a contact arranged on the dielectric material; forming A plurality of trenches are formed through the initial stack, the trenches extending from the device region to the peripheral region outside the array contact definition region and the peripheral contact definition region; the sacrificial layers of the initial stack and the sacrificial layers of the initial staircase structure are removed through the trenches; a plurality of conductive layers are formed in the initial stack to form a stack, the stack comprising a plurality of conductive layers and a plurality of dielectric layers alternately arranged with each other, and forming the staircase structure; and a plurality of connection structures are formed in the trenches; wherein a plurality of memory cells are defined by a plurality of intersections of the conductive layers in the stack and the active structures. A method for manufacturing a semiconductor structure as described in claim 10, wherein the etch stop layer is formed of carbon-doped silicon nitride. A method for manufacturing a semiconductor structure as described in claim 10, wherein the upper surfaces of the array contacts are flush with the upper surfaces of the peripheral contacts.

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