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TWI867629B - Memory controller and control method - Google Patents

Memory controller and control method Download PDF

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Publication number
TWI867629B
TWI867629B TW112127308A TW112127308A TWI867629B TW I867629 B TWI867629 B TW I867629B TW 112127308 A TW112127308 A TW 112127308A TW 112127308 A TW112127308 A TW 112127308A TW I867629 B TWI867629 B TW I867629B
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signal
check
voltage
power
circuit
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TW112127308A
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TW202505527A (en
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丁啓恒
林渭哲
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點序科技股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller

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  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

A memory controller and control method are provided. The memory controller includes a plurality of voltage converters, an inspection circuit, and a selection circuit. The voltage converters are configured to receive an external voltage and convert the external voltage respectively as a plurality of power voltages. The plurality of voltage converters respectively detect levels of the power voltages each voltage converter generated, to generate a plurality of power confirmation signals. The inspection circuit is coupled to the voltage converters. The inspection circuit is configured to generate a first detection signal and a second detection signal according to the power confirmation signals, wherein the first detection signal corresponds to an internal power voltage of the power voltages and the second detection signal corresponds to all power voltages. The selection circuit is configured to selectively output the first detection signal or the second detection signal as the reset confirmation signal.

Description

記憶體控制器及控制方法Memory controller and control method

本發明是有關於一種控制器及方法，且特別是有關於一種記憶體控制器及控制方法。 The present invention relates to a controller and a method, and in particular to a memory controller and a control method.

在快閃記憶體控制器的應用中，因應於主機裝置的不同規格與系統需求，快閃記憶體控制器需要因應於不同規格來進行電壓轉換，以適應性地驅動快閃記憶體的操作。因此，在快閃記憶體啟動或重啟的時候，快閃記憶體控制器要如何快速且有效率地確認該些轉換後的電壓是否已就緒也就成為了相關領域所要解決的其中一項課題。 In the application of flash memory controllers, in response to different specifications and system requirements of host devices, flash memory controllers need to convert voltages according to different specifications to adaptively drive the operation of flash memory. Therefore, when the flash memory is started or restarted, how the flash memory controller can quickly and efficiently confirm whether the converted voltages are ready has become one of the issues to be solved in related fields.

本發明提供一種記憶體控制器及控制方法，其可有效地在快閃記憶體啟動或重啟的時候，快速且有效率地確認該些轉換後的電壓是否已就緒。 The present invention provides a memory controller and control method, which can effectively and efficiently confirm whether the converted voltages are ready when the flash memory is started or restarted.

本發明的記憶體控制器包括多個電壓轉換電路、檢查電 路及選擇電路。電壓轉換電路經組態以接收外部電壓，並分別轉換為多個電源電壓。電壓轉換電路分別偵測其所產生的該些電源電壓的準位，以產生多個電源確認訊號。檢查電路耦接於電壓轉換電路。檢查電路用以依據電源確認訊號來產生第一檢查訊號以及第二檢查訊號，其中第一檢查訊號對應於電源電壓中的內部電源電壓，且第二檢查訊號對應於所有的電源電壓。選擇電路用以選擇性地將第一檢查訊號或第二檢查訊號輸出為重設確認訊號。 The memory controller of the present invention includes a plurality of voltage conversion circuits, a check circuit and a selection circuit. The voltage conversion circuit is configured to receive an external voltage and convert it into a plurality of power supply voltages respectively. The voltage conversion circuit detects the levels of the power supply voltages generated by it respectively to generate a plurality of power supply confirmation signals. The check circuit is coupled to the voltage conversion circuit. The check circuit is used to generate a first check signal and a second check signal according to the power supply confirmation signal, wherein the first check signal corresponds to an internal power supply voltage in the power supply voltage, and the second check signal corresponds to all power supply voltages. The selection circuit is used to selectively output the first check signal or the second check signal as a reset confirmation signal.

本發明的控制方法，適用於驅動快閃記憶體。控制方法包括接收外部電壓，並將外部電壓轉換為多個電源電壓；偵測該些電源電壓的準位，以產生分別對應的多個電源確認訊號；依據電源確認訊號來產生第一檢查訊號以及第二檢查訊號，其中第一檢查訊號對應於電源電壓中的內部電源電壓，且第二檢查訊號對應於所有的電源電壓；以及選擇性地將第一檢查訊號或第二檢查訊號輸出為重設確認訊號。 The control method of the present invention is applicable to driving a flash memory. The control method includes receiving an external voltage and converting the external voltage into a plurality of power supply voltages; detecting the levels of the power supply voltages to generate a plurality of power supply confirmation signals corresponding to each other; generating a first check signal and a second check signal according to the power supply confirmation signal, wherein the first check signal corresponds to an internal power supply voltage in the power supply voltage, and the second check signal corresponds to all power supply voltages; and selectively outputting the first check signal or the second check signal as a reset confirmation signal.

基於上述，本發明的記憶體控制器及控制方法提供了透過軟體或硬體的方式來檢查電源電壓，提供了彈性且快速的快閃記憶體啟動或重啟流程。 Based on the above, the memory controller and control method of the present invention provide a method for checking the power supply voltage through software or hardware, providing a flexible and fast flash memory startup or restart process.

10:主機裝置 10: Host device

11、21:記憶體控制器 11, 21: Memory controller

12:快閃記憶體 12: Flash memory

110、210:檢查電路 110, 210: Check the circuit

111、211:選擇電路 111, 211: Select circuit

112:處理器 112: Processor

2100:電壓準位設定電路 2100: Voltage level setting circuit

2101:確認結果判斷電路 2101: Confirmation result judgment circuit

2110~2112:閘 2110~2112: Gate

DS1、DS2:檢查訊號 DS1, DS2: Check signal

DS2_Cont:檢查結果自定義訊號 DS2_Cont: Check result custom signal

LDO1~LDOx:電壓轉換電路 LDO1~LDOx: voltage conversion circuit

MS:模式選擇訊號 MS: Mode selection signal

RSC:重設確認訊號 RSC: Reset confirmation signal

S1、S2、S3:設定訊號 S1, S2, S3: Setting signal

S2_En:模式致能訊號 S2_En: Mode enable signal

S31~S34、S41~S46:步驟 S31~S34, S41~S46: Steps

VC1~VCx:電源確認訊號 VC1~VCx: Power confirmation signal

Vext:外部電壓 Vext: external voltage

VS:轉換設定訊號 VS: Conversion setting signal

VS1~VSx:電源電壓 VS1~VSx: power supply voltage

圖1為本發明實施例一記憶體控制器的電路方塊圖。 Figure 1 is a circuit block diagram of a memory controller in Embodiment 1 of the present invention.

圖2為本發明實施例一記憶體控制器的電路方塊圖。 Figure 2 is a circuit block diagram of a memory controller in Embodiment 1 of the present invention.

圖3為本發明實施例一控制方法的流程圖。 Figure 3 is a flow chart of the control method of embodiment 1 of the present invention.

圖4為本發明實施例一控制方法的流程圖。 Figure 4 is a flow chart of the control method of embodiment 1 of the present invention.

圖1為本發明實施例一記憶體控制器11的電路方塊圖。一般來說，記憶體控制器11耦接於快閃記憶體12及主機裝置10之間。記憶體控制器11可接受主機裝置10所提供的外部電壓Vext以及外部輸入的設定訊號S1、S2，來對應地將外部電壓Vext轉換為適合的電壓準位，進而驅動快閃記憶體12以及記憶體控制器11的內部電路的操作。在實際應用上，不同規格的主機裝置10所提供的外部電壓Vext有所不同，因此連接於主機裝置10以及快閃記憶體12之間的記憶體控制器10就扮演了重要的腳色，負責在不同規格及電壓需求的主機裝置10以及快閃記憶體12之間，適應性地進行電壓轉換，以較佳地區動快閃記憶體12，進而增加快閃記憶體12的系統相容性。 FIG1 is a circuit block diagram of a memory controller 11 according to an embodiment of the present invention. Generally speaking, the memory controller 11 is coupled between a flash memory 12 and a host device 10. The memory controller 11 can receive an external voltage Vext provided by the host device 10 and external input setting signals S1 and S2 to convert the external voltage Vext into a suitable voltage level accordingly, thereby driving the operation of the flash memory 12 and the internal circuit of the memory controller 11. In actual applications, the external voltage Vext provided by host devices 10 of different specifications is different, so the memory controller 10 connected between the host device 10 and the flash memory 12 plays an important role. It is responsible for adaptively converting the voltage between the host device 10 and the flash memory 12 of different specifications and voltage requirements to better activate the flash memory 12, thereby increasing the system compatibility of the flash memory 12.

詳細來說，主機裝置10可能是符合Secure Digital(SD)記憶卡、嵌入式多媒體卡(embedded MultiMedia Card,eMMC)、通用序列匯流排(Universal Serial Bus,USB)、通用快閃記憶體儲存(Universal Flash Storage,UFS)、非揮發性記憶體通訊協定(Non-Volatile Memory Express,NVMe)、或其他適合規格的主機裝置10。進一步，主機裝置10可提供外部電壓Vext至記憶體控制器11。同時，藉由外部輸入第一設定訊號S1及第二設定訊號S2至記憶 體控制器11，來指示使用者設定或系統需求的電壓組合。 Specifically, the host device 10 may be a host device 10 that complies with Secure Digital (SD) memory card, embedded MultiMedia Card (eMMC), Universal Serial Bus (USB), Universal Flash Storage (UFS), Non-Volatile Memory Express (NVMe), or other suitable specifications. Furthermore, the host device 10 can provide an external voltage Vext to the memory controller 11. At the same time, the first setting signal S1 and the second setting signal S2 are input externally to the memory controller 11 to indicate the voltage combination set by the user or the system requirement.

在一些實施例中，記憶體控制器11可接收外部電壓Vext、並依據第一設定訊號S1來產生出適當的第一電源電壓VS1及第二電源電壓VS2，分別用以驅動快閃記憶體12中的核心電路區塊。另一方面，在每次進行啟動或重啟時，記憶體控制器11都會需要重新檢查外部電壓Vext的電壓，來確認轉換出的多個電源電壓的準位已達系統需求。在此實施例中，記憶體控制器11還可依據第二設定訊號S2來操作在不同的模式之下，依據設定來以不同的方式檢查經轉換的多個電源電壓VS1~VSx(包括第一電源電壓VS1及第二電源電壓VS2)的準位。當操作在第一模式時，記憶體控制器11可透過其內部處理器112以軟體操作的方式來一一檢查轉換出的所有電源電壓VS1~VSx。當操作在第二模式時，記憶體控制器11可透過其內部電路以硬體的方式，來針對轉換出的電源電壓VS1~VSx進行檢查。 In some embodiments, the memory controller 11 can receive the external voltage Vext and generate the appropriate first power voltage VS1 and the second power voltage VS2 according to the first setting signal S1, which are respectively used to drive the core circuit blocks in the flash memory 12. On the other hand, each time the memory controller 11 is started or restarted, it is necessary to recheck the voltage of the external voltage Vext to confirm that the levels of the converted multiple power voltages have reached the system requirements. In this embodiment, the memory controller 11 can also operate in different modes according to the second setting signal S2, and check the levels of the converted multiple power voltages VS1~VSx (including the first power voltage VS1 and the second power voltage VS2) in different ways according to the setting. When operating in the first mode, the memory controller 11 can check all the converted power voltages VS1~VSx one by one through its internal processor 112 in a software operation manner. When operating in the second mode, the memory controller 11 can check the converted power voltages VS1~VSx through its internal circuit in a hardware manner.

在一些實施例中，記憶體控制器11包括多個電壓轉換電路LDO1~LDOx、檢查電路110、選擇電路111及處理器112。電壓轉換電路LDO1~LDOx可用以接收外部電壓Vext以產生多個電源電壓VS1~VSx，其中包括第一電源電壓VS1、第二電源電壓VS2及第三電源電壓VS3。第一電源電壓VS1及第二電源電壓VS2可被提供至快閃記憶體12進行驅動，並例如是分別用來驅動快閃記憶體核心電路區塊以及輸入輸出電路區塊。第三電源電壓VS3(即內部電源電壓)可被提供至記憶體控制器11內部進行驅動， 並例如是驅動記憶體控制器11運作的基本電源電壓。在一些實施例中，每個電壓轉換電路LDO1~LDOx可例如是低壓差轉換電路(low dropout circuit)、降壓轉換器(buck converter)或其他適合的電路，其用以將外部電壓Vext降壓到適當的電壓準位。在此實施例中，電壓轉換電路LDO1~LDOx的數量x可依據系統所需的電源電壓數量或分割的電壓域(voltage domain)的數量而調整。 In some embodiments, the memory controller 11 includes a plurality of voltage conversion circuits LDO1-LDOx, a check circuit 110, a selection circuit 111, and a processor 112. The voltage conversion circuits LDO1-LDOx can be used to receive an external voltage Vext to generate a plurality of power voltages VS1-VSx, including a first power voltage VS1, a second power voltage VS2, and a third power voltage VS3. The first power voltage VS1 and the second power voltage VS2 can be provided to the flash memory 12 for driving, and are used to drive the flash memory core circuit block and the input/output circuit block, for example, respectively. The third power voltage VS3 (i.e., the internal power voltage) can be provided to the memory controller 11 for driving, and is, for example, the basic power voltage for driving the memory controller 11 to operate. In some embodiments, each voltage conversion circuit LDO1~LDOx can be, for example, a low dropout circuit, a buck converter, or other suitable circuits, which are used to step down the external voltage Vext to an appropriate voltage level. In this embodiment, the number x of the voltage conversion circuits LDO1~LDOx can be adjusted according to the number of power voltages required by the system or the number of divided voltage domains.

進一步，檢查電路110耦接於電壓轉換電路LDO1~LDOx，檢查電路110可依據第一設定訊號S1來產生多個轉換設定訊號VS，用以控制並設定電壓轉換電路LDO1~LDOx的操作，使電壓轉換電路LDO1~LDOx可依據主機裝置10及快閃記憶體12規格來轉換產生出適當且符合快閃記憶體12規格的電源電壓。詳細來說，每個電壓轉換電路LDO1~LDOx可獨立運作並產生出個別的電源電壓，其可具有相同或互異的電壓準位。而在電壓轉換電路LDO1~LDOx中的第一電壓轉換電路LDO1及第二電壓轉換電路LDO2(未明確標示於圖1中)，可分別產生電源電壓VS1、VS2，用以分別驅動快閃記憶體12中核心電路區塊以及輸入輸出電路區塊。另外第三電壓轉換電路LDO3(未明確標示於圖1中)可以產生記憶體控制器11所需要的第三電源電壓VS3。另外，在每次進行啟動或重啟時，受到外部電壓Vext斷電的影響，記憶體控制器11還需要確認每個電源電壓VS1~VSx是否已達到或超越各自所對應的電壓閥值。更具體來說，電壓轉換電路LDO1~LDOx可分別針對自身所產生的電源電壓VS1~VSx來進行感測，以判斷每 個電源電壓VS1~VSx是否超越其所對應的電壓閥值，並據此產生相對應的電源確認訊號VC1~VCx。 Furthermore, the check circuit 110 is coupled to the voltage conversion circuits LDO1-LDOx, and the check circuit 110 can generate a plurality of conversion setting signals VS according to the first setting signal S1 to control and set the operation of the voltage conversion circuits LDO1-LDOx, so that the voltage conversion circuits LDO1-LDOx can convert and generate appropriate power voltages that meet the specifications of the flash memory 12 according to the specifications of the host device 10 and the flash memory 12. In detail, each voltage conversion circuit LDO1-LDOx can operate independently and generate individual power voltages, which can have the same or different voltage levels. The first voltage conversion circuit LDO1 and the second voltage conversion circuit LDO2 (not clearly marked in FIG. 1 ) in the voltage conversion circuits LDO1 to LDOx can generate power voltages VS1 and VS2 respectively to drive the core circuit block and the input/output circuit block in the flash memory 12 respectively. In addition, the third voltage conversion circuit LDO3 (not clearly marked in FIG. 1 ) can generate the third power voltage VS3 required by the memory controller 11. In addition, each time the startup or restart is performed, the memory controller 11 is affected by the power failure of the external voltage Vext, and it is also necessary to confirm whether each power voltage VS1 to VSx has reached or exceeded the corresponding voltage threshold. More specifically, the voltage conversion circuits LDO1~LDOx can sense the power voltages VS1~VSx generated by themselves to determine whether each power voltage VS1~VSx exceeds its corresponding voltage threshold, and generate corresponding power confirmation signals VC1~VCx accordingly.

在一些實施例中，第一設定訊號S1及第二設定訊號S2可由外部即時提供或預先寫入至記憶體控制器11，藉以控制記憶體控制器11的操作。舉例來說，第一設定訊號S1及第二設定訊號S2可例如是對預先被寫入的電子熔斷器(efuse)進行讀取所獲得的。又或者是，第一設定訊號S1及第二設定訊號S2可例如是讀取相對應焊墊(pad)上，打線(bonding wire)所連接的電壓準位來獲得的。再或者是，第一設定訊號S1及第二設定訊號S2可例如是由與主機裝置10相同或不同的外部裝置所即時提供的。 In some embodiments, the first setting signal S1 and the second setting signal S2 may be provided in real time by an external device or pre-written to the memory controller 11 to control the operation of the memory controller 11. For example, the first setting signal S1 and the second setting signal S2 may be obtained by reading a pre-written electronic fuse. Alternatively, the first setting signal S1 and the second setting signal S2 may be obtained by reading the voltage level connected to the bonding wire on the corresponding pad. Alternatively, the first setting signal S1 and the second setting signal S2 may be provided in real time by an external device that is the same as or different from the host device 10.

進一步，檢查電路110耦接於電壓轉換電路LDO1~LDOx，檢查電路110可依據電源確認訊號VC1~VCx來產生第一檢查訊號DS1以及第二檢查訊號DS2，其中第一檢查訊號DS1對應於第三電源確認訊號VC3，其包含有可用來驅動處理器112的第三電源電壓VS3的檢查資訊。而第二檢查訊號DS2對應於所有的電源電壓VS1~VSx的電源確認訊號VC1~VCx，其包含所有的電源電壓VS1~VSx的檢查資訊。進一步，檢查電路110還可依據第二設定訊號S2來產生模式選擇訊號MS，並將模式選擇訊號MS、第一檢查訊號DS1及第二檢查訊號DS2提供至選擇電路111。 Furthermore, the check circuit 110 is coupled to the voltage conversion circuit LDO1~LDOx, and the check circuit 110 can generate a first check signal DS1 and a second check signal DS2 according to the power confirmation signals VC1~VCx, wherein the first check signal DS1 corresponds to the third power confirmation signal VC3, which includes the check information of the third power voltage VS3 that can be used to drive the processor 112. The second check signal DS2 corresponds to the power confirmation signals VC1~VCx of all power voltages VS1~VSx, which includes the check information of all power voltages VS1~VSx. Furthermore, the check circuit 110 can also generate a mode selection signal MS according to the second setting signal S2, and provide the mode selection signal MS, the first check signal DS1 and the second check signal DS2 to the selection circuit 111.

選擇電路111耦接於檢查電路110。選擇電路111可依據模式選擇訊號MS來選擇第一檢查訊號DS1或第二檢查訊號DS作為重設確認訊號RSC，並輸出至處理器112。更具體來說，當記 憶體控制器11是操作在第一模式時，處理器112會被用以檢查電源確認訊號VC1~VCx。在此情況下，為了確保處理器112可以先獲得到穩定的電源電壓來進行檢查，檢查電路110可先僅針對處理器112所接收的電源電壓來進行檢查。在此實施例中，處理器112運行需要第三電源電壓VS3。因此，檢查電路110會將電壓轉換電路LDO3針對第三電源電壓VS3進行檢查所產生的電源確認訊號VC3輸出為第一檢查訊號DS1，並提供至選擇電路111。另外，當記憶體控制器11是操作在第二模式時，則是透過檢查電路110以硬體電路的方式來檢查所有的電源確認訊號VC1~VCx，並依據所有的電源確認訊號VC1~VCx產生第二檢查訊號DS2。 The selection circuit 111 is coupled to the check circuit 110. The selection circuit 111 can select the first check signal DS1 or the second check signal DS as the reset confirmation signal RSC according to the mode selection signal MS, and output it to the processor 112. More specifically, when the memory controller 11 is operated in the first mode, the processor 112 is used to check the power confirmation signals VC1~VCx. In this case, in order to ensure that the processor 112 can first obtain a stable power voltage for inspection, the check circuit 110 can first only check the power voltage received by the processor 112. In this embodiment, the processor 112 requires a third power voltage VS3 to operate. Therefore, the check circuit 110 outputs the power confirmation signal VC3 generated by the voltage conversion circuit LDO3 checking the third power voltage VS3 as the first check signal DS1, and provides it to the selection circuit 111. In addition, when the memory controller 11 is operating in the second mode, the check circuit 110 checks all the power confirmation signals VC1~VCx in a hardware circuit manner, and generates the second check signal DS2 according to all the power confirmation signals VC1~VCx.

另一方面，第二設定訊號S2則指示了關於記憶體控制器11是要以軟體方式還是硬體的方式來檢查電源電壓VS1~VSx。在此情況下，檢查電路110可依據第二設定訊號S2來產生模式選擇訊號MS，以告知選擇電路111究竟主機裝置10是要指示軟體或硬體的方式來檢查電源電壓VS1~VSx。當第二設定訊號S2指示以軟體方式來檢查電源電壓VS1~VSx時，記憶體控制器11會被控制以操作在第一模式，選擇電路111則會依據模式選擇訊號MS來將第一檢查訊號DS1輸出為重設確認訊號RSC，使處理器112在重設確認訊號RSC指示第三電源電壓VS3已就緒之後，再檢查所有的電源確認訊號VC1~VCx。另外，當第二設定訊號S2指示以硬體方式來檢查電源電壓VS1~VSx時，記憶體控制器11會被控制以操作在第二模式，由檢查電路110來同時檢查所有的 電源確認訊號VC1~VCx，並據此產生出對應的第二檢查訊號DS2。選擇電路111則會依據模式選擇訊號MS在第二模式下將第二檢查訊號DS2輸出為重設確認訊號RSC，藉此指示處理器112關於檢查電路110的檢查結果。 On the other hand, the second setting signal S2 indicates whether the memory controller 11 is to check the power voltages VS1-VSx by software or hardware. In this case, the checking circuit 110 can generate a mode selection signal MS according to the second setting signal S2 to inform the selection circuit 111 whether the host device 10 is to instruct the software or hardware to check the power voltages VS1-VSx. When the second setting signal S2 indicates that the power supply voltages VS1~VSx are checked in software mode, the memory controller 11 is controlled to operate in the first mode, and the selection circuit 111 outputs the first check signal DS1 as the reset confirmation signal RSC according to the mode selection signal MS, so that the processor 112 checks all the power confirmation signals VC1~VCx after the reset confirmation signal RSC indicates that the third power supply voltage VS3 is ready. In addition, when the second setting signal S2 indicates that the power supply voltages VS1~VSx are checked in hardware mode, the memory controller 11 is controlled to operate in the second mode, and the check circuit 110 checks all the power confirmation signals VC1~VCx at the same time, and generates the corresponding second check signal DS2 accordingly. The selection circuit 111 will output the second check signal DS2 as a reset confirmation signal RSC in the second mode according to the mode selection signal MS, thereby indicating the processor 112 about the check result of the check circuit 110.

受到重設確認訊號RSC的控制，處理器112會執行對應於第一模式及第二模式的操作。具體來說，當記憶體控制器11操作在第一模式且重設確認訊號RSC指示基本工作電壓VS3已就緒時，處理器112會執行軟體程序，來對電源確認訊號VC1~VCx依序進行檢查，以確保在各個電源電壓VS1~VSx大於等於其各自所對應的電壓閥值之後，再進行驅動以及進行快閃記憶體12的讀寫操作。另外，當記憶體控制器11操作在第二模式且重設確認訊號RSC指示所有的電源電壓VS1~VSx皆已就緒時，處理器112便可即刻開始驅動並進行快閃記憶體12的讀寫操作。 Under the control of the reset confirmation signal RSC, the processor 112 performs operations corresponding to the first mode and the second mode. Specifically, when the memory controller 11 operates in the first mode and the reset confirmation signal RSC indicates that the basic working voltage VS3 is ready, the processor 112 executes a software program to sequentially check the power confirmation signals VC1~VCx to ensure that each power voltage VS1~VSx is greater than or equal to its corresponding voltage threshold before driving and performing read and write operations on the flash memory 12. In addition, when the memory controller 11 operates in the second mode and the reset confirmation signal RSC indicates that all power voltages VS1~VSx are ready, the processor 112 can immediately start driving and performing read and write operations on the flash memory 12.

圖2為本發明實施例一記憶體控制器21的電路方塊圖。圖2的記憶體控制器21相似於圖1的記憶體控制器11，是用以說明記憶體控制器21中檢查電路210與選擇電路211的內部電路結構，故相同的元件以相同的符號標示，且於此不另外贅述。 FIG2 is a circuit block diagram of a memory controller 21 of an embodiment of the present invention. The memory controller 21 of FIG2 is similar to the memory controller 11 of FIG1 and is used to illustrate the internal circuit structure of the check circuit 210 and the selection circuit 211 in the memory controller 21. Therefore, the same components are marked with the same symbols and will not be further described here.

在此實施例中，記憶體控制器21中包括檢查電路210、選擇電路211、處理器112及電壓轉換電路LDO1~LDOx。進一步，檢查電路210包含了電壓準位設定電路2100及確認結果判斷電路2101。詳細來說，電壓準位設定電路2100接收了第一設定訊號S1及第二設定訊號S2。電壓準位設定電路2100可依據第一設 定訊號產生出轉換設定訊號VS，據以適應性地調整電壓轉換電路LDO1~LDOx來產生出系統所需的電源電壓VS1~VSx。進一步，電壓準位設定電路2100可依據第二設定訊號S2來提供模式資訊MI至確認結果判斷電路2101。 In this embodiment, the memory controller 21 includes a check circuit 210, a selection circuit 211, a processor 112, and voltage conversion circuits LDO1~LDOx. Furthermore, the check circuit 210 includes a voltage level setting circuit 2100 and a confirmation result judgment circuit 2101. Specifically, the voltage level setting circuit 2100 receives a first setting signal S1 and a second setting signal S2. The voltage level setting circuit 2100 can generate a conversion setting signal VS according to the first setting signal, and adaptively adjust the voltage conversion circuits LDO1~LDOx to generate the power voltages VS1~VSx required by the system. Furthermore, the voltage level setting circuit 2100 can provide mode information MI to the confirmation result determination circuit 2101 according to the second setting signal S2.

在此實施例中，確認結果判斷電路2101除了接收電源確認訊號VC1~VCx以及由電壓準位設定電路2100接收相關於第二設定訊號S2的模式資訊MI之外，確認結果判斷電路2101還會由主機裝置10接收第三設定訊號S3，並且由處理器112接收模式致能訊號S2_En及檢查結果自定義訊號DS2_Cont。詳細來說，第三設定訊號S3包含了重設確認訊號RSC的輸出時間，也就是在啟動或重啟後需要等待多久的運算時間再將運算後的重設確認訊號RSC輸出，一般來說重設確認訊號RSC的輸出時間會相關於電源確認訊號VC1~VCx所需要的爬升斜率與確認時間。模式致能訊號S2_En則包含了關於記憶體控制器21是否允許被操作在第二模式下的資訊，也就是記憶體控制器21是否開放以硬體方式來進行電源電壓的確認判斷。最後，檢查結果自定義訊號DS2_Cont則是開放了由系統或使用者定義記憶體控制器21在第二模式下所要檢查的電源確認訊號。舉例來說，在一些實施例中，確認結果判斷電路2101可透過及閘來接收所有的電源確認訊號VC1~VCx，以判斷是否所有的電源確認訊號VC1~VCx皆已就緒，並據此產生第二檢查訊號DS2。但是，在一些其他實施例中，確認結果判斷電路2101當然僅可依據檢查結果自定義訊號DS2_Cont來由電源 確認訊號VC1~VCx中選出一部分選中電源確認訊號，進而判斷該些選中電源確認訊號是否已就緒，並據此產生第二檢查訊號DS2。 In this embodiment, in addition to receiving the power confirmation signals VC1~VCx and the mode information MI related to the second setting signal S2 from the voltage level setting circuit 2100, the confirmation result determination circuit 2101 also receives the third setting signal S3 from the host device 10, and receives the mode enable signal S2_En and the check result custom signal DS2_Cont from the processor 112. In detail, the third setting signal S3 includes the output time of the reset confirmation signal RSC, that is, how long the calculation time needs to wait after starting or restarting before outputting the calculated reset confirmation signal RSC. Generally speaking, the output time of the reset confirmation signal RSC is related to the climbing slope and confirmation time required by the power confirmation signals VC1~VCx. The mode enable signal S2_En includes information about whether the memory controller 21 is allowed to be operated in the second mode, that is, whether the memory controller 21 is open to confirm the power voltage in hardware. Finally, the check result custom signal DS2_Cont opens the power confirmation signal to be checked by the memory controller 21 in the second mode defined by the system or the user. For example, in some embodiments, the confirmation result judgment circuit 2101 can receive all the power confirmation signals VC1~VCx through an AND gate to determine whether all the power confirmation signals VC1~VCx are ready, and generate the second check signal DS2 accordingly. However, in some other embodiments, the confirmation result judgment circuit 2101 can only select a part of the selected power confirmation signals from the power confirmation signals VC1~VCx according to the check result custom signal DS2_Cont, and then judge whether the selected power confirmation signals are ready, and generate the second check signal DS2 accordingly.

選擇電路211包括及閘2110、互斥或閘2111及或閘2112。及閘2110的第一輸入端接收模式資訊MI且第二輸入端接收第一檢查訊號DS1。互斥或閘2111的第一輸入端接收模式資訊MI且第二輸入端接收第二檢查訊號DS2。並且，及閘2110及互斥或閘2111的輸出端分別接到或閘2112的第一輸入端及第二輸入端，以於或閘2112的輸出端產生重設確認訊號RSC。詳細來說，當模式致能訊號S2_En指示了記憶體控制器21開放第二模式時，選擇電路211將會依據第二設定訊號S2的控制來選擇性地選擇第一檢查訊號DS1或第二檢查訊號DS2作為重設確認訊號RSC。相反地，當模式致能訊號S2_En指示了記憶體控制器21不開放第二模式時，確認結果判斷電路2101可依據模式致能訊號S2_En僅操作在第一模式下的模式選擇訊號MS，使選擇電路211據此將第一檢查訊號DS1輸出為重設確認訊號RSC。雖然在圖2中繪示了以及閘2110、互斥或閘2111及或閘2112來實現選擇電路211的實現方式。但應當理解的是，圖3中的電路結構僅是本發明的多種變化實施例的其中一種實施方式而已，本領域具通常知識者當然可自行變化電路結構，透過相異的電路結構亦可達到相同結果的操作。舉例來說，選擇電路211亦可由多工器所實現，只要其可實現選擇性地將第一檢查訊號DS1或第二檢查訊號DS2輸出為重設確認 訊號RSC即可。 The selection circuit 211 includes an AND gate 2110, an XOR gate 2111, and an OR gate 2112. The first input terminal of the AND gate 2110 receives the mode information MI and the second input terminal receives the first check signal DS1. The first input terminal of the XOR gate 2111 receives the mode information MI and the second input terminal receives the second check signal DS2. In addition, the output terminals of the AND gate 2110 and the XOR gate 2111 are respectively connected to the first input terminal and the second input terminal of the OR gate 2112 to generate a reset confirmation signal RSC at the output terminal of the OR gate 2112. Specifically, when the mode enable signal S2_En indicates that the memory controller 21 opens the second mode, the selection circuit 211 will selectively select the first check signal DS1 or the second check signal DS2 as the reset confirmation signal RSC according to the control of the second setting signal S2. On the contrary, when the mode enable signal S2_En indicates that the memory controller 21 does not open the second mode, the confirmation result judgment circuit 2101 can operate only the mode selection signal MS in the first mode according to the mode enable signal S2_En, so that the selection circuit 211 outputs the first check signal DS1 as the reset confirmation signal RSC. Although FIG. 2 shows the implementation method of the selection circuit 211 by the AND gate 2110, the exclusive OR gate 2111 and the OR gate 2112. However, it should be understood that the circuit structure in FIG. 3 is only one of the various variations of the present invention. A person skilled in the art can change the circuit structure by himself, and can achieve the same operation result through a different circuit structure. For example, the selection circuit 211 can also be implemented by a multiplexer, as long as it can selectively output the first check signal DS1 or the second check signal DS2 as the reset confirmation signal RSC.

圖3為本發明實施例一控制方法的流程圖。圖3所示的流程圖可應用於圖1、2中所繪示的記憶體控制器11、21，且關於記憶體控制器11、21的操作內容可被歸納為圖3所示的流程圖。圖3所示的流程圖包括步驟S31~S34。在步驟S31中，記憶體控制器11/21可接收外部電壓Vext，並將外部電壓Vext轉換為多個電源電壓VS1~VSx。在步驟S32中，記憶體控制器11/21可偵測轉換出的電源電壓VS1~VSx的準位，以產生分別對應的電源確認訊號VC1~VCx。在步驟S33中，記憶體控制器11/21可依據電源確認訊號VC1~VCx來產生第一檢查訊號DS1以及第二檢查訊號DS2，其中第一檢查訊號DS1對應於電源電壓中的第三電源電壓VS3，且第二檢查訊號DS2對應於所有的電源電壓。最後，記憶體控制器11/21可選擇性地將第一檢查訊號DS1或第二檢查訊號DS2輸出為重設確認訊號RSC。關於圖3所示的控制方法的詳細內容，請進一步參考上述段落中關於記憶體控制器11、21的說明，於此不另贅述。 FIG3 is a flow chart of the control method of the first embodiment of the present invention. The flow chart shown in FIG3 can be applied to the memory controllers 11 and 21 shown in FIGS. 1 and 2, and the operation contents of the memory controllers 11 and 21 can be summarized as the flow chart shown in FIG3. The flow chart shown in FIG3 includes steps S31 to S34. In step S31, the memory controller 11/21 can receive an external voltage Vext and convert the external voltage Vext into a plurality of power voltages VS1 to VSx. In step S32, the memory controller 11/21 can detect the levels of the converted power voltages VS1 to VSx to generate corresponding power confirmation signals VC1 to VCx. In step S33, the memory controller 11/21 can generate a first check signal DS1 and a second check signal DS2 according to the power confirmation signals VC1~VCx, wherein the first check signal DS1 corresponds to the third power voltage VS3 in the power voltage, and the second check signal DS2 corresponds to all power voltages. Finally, the memory controller 11/21 can selectively output the first check signal DS1 or the second check signal DS2 as a reset confirmation signal RSC. For details of the control method shown in FIG. 3, please refer to the description of the memory controllers 11 and 21 in the above paragraphs, which will not be elaborated here.

圖4為本發明實施例一控制方法的流程圖。圖4所示的流程圖可應用於圖1、2中所繪示的記憶體控制器11、21，且關於記憶體控制器11、21的操作內容亦可被歸納為圖4所示的流程圖。圖4所示的流程圖包括步驟S41~S46。在步驟S41中，記憶體控制器11/21可依據第一設定訊號S1來設定電壓轉換電路LDO1~LDOx中，用來驅動快閃記憶體12的第一電壓轉換電路LDO1及 第二電壓轉換電路LDO2。在步驟S42中，記憶體控制器11/21可接收外部電壓Vext，並將外部電壓Vext轉換為多個電源電壓VS1~VSx。在步驟S43中，記憶體控制器11/21可偵測電源電壓VS1~VSx的準位，以產生分別對應的電源確認訊號VC1~VCx。在步驟S44中，記憶體控制器11/21可依據第二設定訊號判斷記憶體控制器11/21是被控制在哪一個操作模式下。當記憶體控制器11/21判斷記憶體控制器11/21是被控制在第一模式下時，則進入步驟S45中，記憶體控制器11/21可以藉由處理器112來以軟體的方式檢查電源電壓VS1~VSx。相反地，當記憶體控制器11/21判斷記憶體控制器11/21是被控制在第二模式下時，則進入步驟S46中，記憶體控制器11/21可以藉由檢查電路110來以硬體的方式檢查電源電壓VS1~VSx。 FIG4 is a flow chart of the control method of the first embodiment of the present invention. The flow chart shown in FIG4 can be applied to the memory controllers 11 and 21 shown in FIG1 and FIG2, and the operation contents of the memory controllers 11 and 21 can also be summarized as the flow chart shown in FIG4. The flow chart shown in FIG4 includes steps S41 to S46. In step S41, the memory controller 11/21 can set the first voltage conversion circuit LDO1 and the second voltage conversion circuit LDO2 of the voltage conversion circuit LDO1 to drive the flash memory 12 according to the first setting signal S1. In step S42, the memory controller 11/21 can receive an external voltage Vext and convert the external voltage Vext into a plurality of power supply voltages VS1 to VSx. In step S43, the memory controller 11/21 can detect the level of the power supply voltage VS1~VSx to generate the corresponding power supply confirmation signals VC1~VCx. In step S44, the memory controller 11/21 can determine which operation mode the memory controller 11/21 is controlled in according to the second setting signal. When the memory controller 11/21 determines that the memory controller 11/21 is controlled in the first mode, it enters step S45, and the memory controller 11/21 can check the power supply voltage VS1~VSx in software through the processor 112. On the contrary, when the memory controller 11/21 determines that the memory controller 11/21 is controlled in the second mode, it enters step S46, and the memory controller 11/21 can check the power supply voltage VS1~VSx in a hardware manner by checking the circuit 110.

綜上所述，本發明的記憶體控制器及控制方法提供了透過軟體或硬體的方式來檢查電源電壓。相較於透過處理器以軟體方式一一對所有電源電壓依序進行檢查的流程，透過硬體的方式來檢查電源電壓，可省卻對所有電源電壓一一進行檢查的流程，有效改善記憶體控制器啟動或重啟後的檢查速度。 In summary, the memory controller and control method of the present invention provide a method for checking the power voltage through software or hardware. Compared with the process of checking all power voltages one by one in software through a processor, checking the power voltage through hardware can save the process of checking all power voltages one by one, effectively improving the checking speed after the memory controller is started or restarted.

10:主機裝置 10: Host device

11:記憶體控制器 11:Memory controller

12:快閃記憶體 12: Flash memory

110:檢查電路 110: Check the circuit

111:選擇電路 111: Select circuit

112:處理器 112: Processor

DS1、DS2:檢查訊號 DS1, DS2: Check signal

LDO1~LDOx:電壓轉換電路 LDO1~LDOx: voltage conversion circuit

MS:模式選擇訊號 MS: Mode selection signal

RSC:重設確認訊號 RSC: Reset confirmation signal

S1、S2:設定訊號 S1, S2: Setting signal

VC1~VCx:電源確認訊號 VC1~VCx: Power confirmation signal

Vext:外部電壓 Vext: external voltage

VS:轉換設定訊號 VS: Conversion setting signal

VS1~VSx:電源電壓 VS1~VSx: power supply voltage

Claims (17)

一種記憶體控制器，包括：多個電壓轉換電路，經組態以接收一外部電壓，並分別轉換為多個電源電壓，該些電壓轉換電路並分別偵測其所產生的該些電源電壓的準位，以產生多個電源確認訊號；一檢查電路，耦接於該些電壓轉換電路，該檢查電路用以依據該些電源確認訊號來產生一第一檢查訊號以及一第二檢查訊號，其中該第一檢查訊號對應於該些電源電壓中的一內部電源電壓，且該第二檢查訊號對應於所有的該些電源電壓；以及一選擇電路，用以選擇性地將該第一檢查訊號或該第二檢查訊號輸出為一重設確認訊號。 A memory controller includes: a plurality of voltage conversion circuits configured to receive an external voltage and convert it into a plurality of power voltages respectively, and the voltage conversion circuits respectively detect the levels of the power voltages generated to generate a plurality of power confirmation signals; a check circuit coupled to the voltage conversion circuits, the check circuit is used to generate a first check signal and a second check signal according to the power confirmation signals, wherein the first check signal corresponds to an internal power voltage among the power voltages, and the second check signal corresponds to all the power voltages; and a selection circuit is used to selectively output the first check signal or the second check signal as a reset confirmation signal. 如請求項1所述的記憶體控制器，其中該檢查電路用以接收一第一設定訊號，用以設定該些電壓轉換電路中的一第一電壓轉換電路及一第二電壓轉換電路，該第一電壓轉換電路及該第二電壓轉換電路用以產生該第一電源電壓及一第二電壓來驅動一快閃記憶體，使該第一電源電壓及該第二電源電壓的準位符合該快閃記憶體的規格。 A memory controller as described in claim 1, wherein the check circuit is used to receive a first setting signal to set a first voltage conversion circuit and a second voltage conversion circuit among the voltage conversion circuits, and the first voltage conversion circuit and the second voltage conversion circuit are used to generate the first power voltage and a second voltage to drive a flash memory, so that the levels of the first power voltage and the second power voltage meet the specifications of the flash memory. 如請求項1所述的記憶體控制器，還包括一處理器，其中該檢查電路還用以接收一第二設定訊號，用以指示該記憶體控制器是操作一第一模式或一第二模式下，其中當該記憶體控制器是操作在該第一模式時，該處理器被用以檢查該些電源確認訊號，以及 當該記憶體控制器是操作在該第二模式時，該檢查電路被用以檢查該些電源確認訊號。 The memory controller as described in claim 1 further includes a processor, wherein the check circuit is also used to receive a second setting signal to indicate whether the memory controller is operating in a first mode or a second mode, wherein when the memory controller is operating in the first mode, the processor is used to check the power confirmation signals, and When the memory controller is operating in the second mode, the check circuit is used to check the power confirmation signals. 如請求項3所述的記憶體控制器，其中該內部電源電被用來驅動該處理器。 A memory controller as described in claim 3, wherein the internal power supply is used to drive the processor. 如請求項3所述的記憶體控制器，其中該檢查電路還用以依據該第二設定訊號產生一模式選擇訊號至該選擇電路，其中當該記憶體控制器是操作在該第一模式時，該選擇電路依據該模式選擇訊號，來選擇該第一檢查訊號作為該重設確認訊號，並將該重設確認訊號提供至該處理器，以及當該記憶體控制器是操作在該第二模式時，該選擇電路依據該模式選擇訊號，來選擇該第二檢查訊號作為該重設確認訊號，並將該重設確認訊號提供至該處理器。 A memory controller as described in claim 3, wherein the check circuit is further used to generate a mode selection signal to the selection circuit according to the second setting signal, wherein when the memory controller is operating in the first mode, the selection circuit selects the first check signal as the reset confirmation signal according to the mode selection signal, and provides the reset confirmation signal to the processor, and when the memory controller is operating in the second mode, the selection circuit selects the second check signal as the reset confirmation signal according to the mode selection signal, and provides the reset confirmation signal to the processor. 如請求項5所述的記憶體控制器，其中當該記憶體控制器是操作在該第一模式時，該處理器會在該第一檢查訊號指示該內部電源電壓已大於一第一電壓閥值之後，再依序確認該些電源確認訊號，來確定該些電源電壓是否已分別大於多個電壓閥值。 A memory controller as described in claim 5, wherein when the memory controller is operating in the first mode, the processor will sequentially confirm the power confirmation signals after the first check signal indicates that the internal power voltage is greater than a first voltage threshold value to determine whether the power voltages are respectively greater than a plurality of voltage threshold values. 如請求項5所述的記憶體控制器，其中當該記憶體控制器是操作在該第二模式時，該檢查電路會先同時檢查該些電源確認訊號是否已分別大於多個電壓閥值之後，再據此產生指示該些電源電壓已分別大於該些電壓閥值的該第二檢查訊號。 A memory controller as described in claim 5, wherein when the memory controller is operating in the second mode, the check circuit will first simultaneously check whether the power supply confirmation signals are respectively greater than a plurality of voltage thresholds, and then generate the second check signal indicating that the power supply voltages are respectively greater than the voltage thresholds. 如請求項1所述的記憶體控制器，其中該選擇電路包括：一及閘，具有接收一模式選擇訊號的第一輸入端、接收該第一檢查訊號的第二輸入端，以及產生一第一運算訊號的輸出端；一互斥或閘(exclusive or gate)，具有接收該模式選擇訊號的第一輸入端、接收該第二檢查訊號的第二輸入端，以及產生一第二運算訊號的輸出端；一或閘，具有接收該第一運算訊號的第一輸入端、接收該第二運算訊號的第二輸入端，以及產生該重設確認訊號的輸出端。 A memory controller as described in claim 1, wherein the selection circuit includes: an AND gate having a first input terminal receiving a mode selection signal, a second input terminal receiving the first check signal, and an output terminal generating a first operation signal; an exclusive OR gate having a first input terminal receiving the mode selection signal, a second input terminal receiving the second check signal, and an output terminal generating a second operation signal; an OR gate having a first input terminal receiving the first operation signal, a second input terminal receiving the second operation signal, and an output terminal generating the reset confirmation signal. 如請求項2所述的記憶體控制器，其中該檢查電路還接收一第三設定訊號，用以設定該檢查電路產生該重設確認訊號的輸出時間。 A memory controller as described in claim 2, wherein the check circuit also receives a third setting signal for setting the output time of the check circuit generating the reset confirmation signal. 如請求項9所述的記憶體控制器，其中該檢查電路包括：一電壓準位設定電路，該電壓準位設定電路依據該第一設定訊號產生一轉換設定訊號，以設定該些電壓轉換電路；以及一確認結果判斷電路，接收該些電源確認訊號，以依據該些電源確認訊號中對應該內部電源電壓的一電源確認訊號以產生該第一檢查訊號，以及依據所有的該些電源確認訊號以產生該第二檢查訊號。 A memory controller as described in claim 9, wherein the check circuit comprises: a voltage level setting circuit, the voltage level setting circuit generates a conversion setting signal according to the first setting signal to set the voltage conversion circuits; and a confirmation result judgment circuit, receiving the power confirmation signals, to generate the first check signal according to a power confirmation signal corresponding to the internal power voltage among the power confirmation signals, and to generate the second check signal according to all the power confirmation signals. 一種控制方法，適用於驅動一快閃記憶體，該控制方法包括： 接收一外部電壓，並將該外部電壓轉換為多個電源電壓；偵測該些電源電壓的準位，以產生分別對應的多個電源確認訊號；依據該些電源確認訊號來產生一第一檢查訊號以及一第二檢查訊號，其中該第一檢查訊號對應於該些電源電壓中的一內部電源電壓，且該第二檢查訊號對應於所有的該些電源電壓；以及選擇性地將該第一檢查訊號或該第二檢查訊號輸出為一重設確認訊號。 A control method is used for driving a flash memory, the control method comprising: receiving an external voltage and converting the external voltage into a plurality of power supply voltages; detecting the levels of the power supply voltages to generate a plurality of power supply confirmation signals respectively corresponding to the power supply voltages; generating a first check signal and a second check signal according to the power supply confirmation signals, wherein the first check signal corresponds to an internal power supply voltage among the power supply voltages, and the second check signal corresponds to all the power supply voltages; and selectively outputting the first check signal or the second check signal as a reset confirmation signal. 如請求項11所述的控制方法，還包括接收一第一設定訊號，用以設定一第一電壓轉換電路及一第二電壓轉換電路，該第一電壓轉換電路及該第二電壓轉換電路產生該第一電源電壓及一第二電壓來驅動該快閃記憶體，使該第一電源電壓及該第二電源電壓的準位符合該快閃記憶體的規格。 The control method as described in claim 11 further includes receiving a first setting signal to set a first voltage conversion circuit and a second voltage conversion circuit, wherein the first voltage conversion circuit and the second voltage conversion circuit generate the first power voltage and a second voltage to drive the flash memory, so that the levels of the first power voltage and the second power voltage meet the specifications of the flash memory. 如請求項11所述的控制方法，還包括接收一第二設定訊號，以指示操作在一第一模式或一第二模式，其中當操作在該第一模式時，一處理器被用以檢查該些電源確認訊號，以及當操作在該第二模式時，一檢查電路被用以檢查該些電源確認訊號。 The control method as claimed in claim 11 further includes receiving a second setting signal to indicate operation in a first mode or a second mode, wherein when operating in the first mode, a processor is used to check the power confirmation signals, and when operating in the second mode, a check circuit is used to check the power confirmation signals. 如請求項13所述的控制方法，還包括依據該第二設定訊號產生一模式選擇訊號，其中當操作在該第一模式時，依據該模式選擇訊號來選擇該 第一檢查訊號作為該重設確認訊號，並將該重設確認訊號提供至該處理器，以及當操作在該第二模式時，依據該模式選擇訊號來選擇該第二檢查訊號作為該重設確認訊號，並將該重設確認訊號提供至該處理器。 The control method as claimed in claim 13 further includes generating a mode selection signal according to the second setting signal, wherein when operating in the first mode, the first check signal is selected according to the mode selection signal as the reset confirmation signal, and the reset confirmation signal is provided to the processor, and when operating in the second mode, the second check signal is selected according to the mode selection signal as the reset confirmation signal, and the reset confirmation signal is provided to the processor. 如請求項14所述的控制方法，其中當操作在該第一模式時，在該第一檢查訊號指示該內部電源電壓已大於一第一電壓閥值之後，藉由該處理器再依序確認該些電源確認訊號，來確定該些電源電壓是否已分別大於多個電壓閥值。 A control method as described in claim 14, wherein when operating in the first mode, after the first check signal indicates that the internal power supply voltage is greater than a first voltage threshold, the processor sequentially confirms the power supply confirmation signals to determine whether the power supply voltages are respectively greater than a plurality of voltage thresholds. 如請求項14所述的控制方法，其中當操作在該第二模式時，藉由該檢查電路先同時檢查該些電源確認訊號是否已分別大於多個電壓閥之後，再據此產生指示該些電源電壓已分別大於該些電壓閥值的該第二檢查訊號。 The control method as described in claim 14, wherein when operating in the second mode, the check circuit first checks whether the power supply confirmation signals are respectively greater than a plurality of voltage valves, and then generates the second check signal indicating that the power supply voltages are respectively greater than the voltage valve values. 如請求項12所述的控制方法，還包括接收一第三設定訊號，用以設定產生該重設確認訊號的輸出時間。 The control method as described in claim 12 further includes receiving a third setting signal for setting the output time of generating the reset confirmation signal.
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