CN211906032U - Initialization control circuit and electronic equipment - Google Patents

Abstract

This utility model discloses an initialization control circuit and electronic device. The initialization control circuit includes a power switch, a first controller, a switch module, and a second controller. The power switch is electrically connected to the first controller. The first controller is electrically connected to the second controller through the switch module. The first controller controls the switch module to turn on. In this utility model embodiment, the power switch, the first controller, the switch module, and the second controller are connected in series. When the power switch is closed, the first controller first completes initialization and then controls the switch module to turn on, so that the second controller completes initialization, thereby achieving the purpose of the first controller and the second controller completing initialization sequentially.

Description

A kind of initialization control circuit and electronic equipment

technical field

The embodiments of the present utility model relate to the technical field of computers, and in particular, to an initialization control circuit and an electronic device.

Background technique

A notebook computer or a desktop computer system includes many chips, and the sequence of initialization of each chip during startup has a great influence on the startup process.

Taking Embedded Controller (EC) and Power Management Integrated Circuit (PMIC) as examples, both play an important role in the system, and EC controls most of the important components during system startup. The timing of the signals, for example, the keyboard controller, the control of the charging indicator and the fan and other devices, in addition, also controls the standby, hibernation and other states of the system. PMIC is used to manage the power supply equipment in the host system, and also plays a crucial role in the system. Fig. 1 is a schematic structural diagram of an existing initialization control circuit. As shown in Fig. 1, at present, most initialization schemes are that after closing the power switch 10, the low-level power-on signal is simultaneously transmitted to the EC through the zero-ohm resistor 2 3 and PMIC 4, so that the EC 3 and PMIC 4 are connected in parallel to achieve simultaneous initialization.

However, the scheme of initializing the EC and PMIC in parallel during the boot process often encounters the problem that the EC and the PMIC preempt the bus resources at the same time, and the system cannot arbitrate the priority of the two and the chip code crashes.

Utility model content

The purpose of the embodiments of the present invention is to provide an initialization control circuit and an electronic device, so that each chip in the system can be initialized in a certain order when the computer is turned on.

In a first aspect, an embodiment of the present invention provides an initialization control circuit, including a power switch, a first controller, a switch module, and a second controller;

The power switch is electrically connected with the first controller; the first controller is electrically connected with the second controller through the switch module; the first controller controls the switch module to conduct.

Further, the switch module includes a diode; the cathode of the diode is electrically connected to the output terminal of the first controller, and the anode of the diode is electrically connected to the input terminal of the second controller.

Further, the switch module includes a switch chip; the control terminal of the switch chip is electrically connected to the control terminal of the first controller, the input terminal of the switch chip is electrically connected to the output terminal of the first controller, and the output terminal of the switch chip is electrically connected to the second controller The input terminal of the device is electrically connected.

Further, the switch chip includes a metal oxidesemiconductor Field-Effect Transistor (MOSFET, hereinafter referred to as a MOS tube); the control end of the MOS tube is the control end of the switch chip; the input end of the MOS tube is the switch The input end of the chip; the output end of the MOS tube is the output end of the switch chip.

Further, the switch chip further includes: a first resistor, a second resistor and a comparator;

The first end of the first resistor is electrically connected to the output end of the switch chip, the second end of the first resistor is electrically connected to the first end of the second resistor, and the second end of the second resistor is grounded; the positive input end of the comparator It is electrically connected to the second end of the first resistor, the reverse input end of the comparator is electrically connected to the input end of the switch chip, and the output end of the comparator is electrically connected to the control end of the MOS tube.

Further, the switch chip also includes a first capacitor;

The first end of the first capacitor is electrically connected to the first end of the first resistor, and the second end of the first capacitor is electrically connected to the second end of the first resistor.

Further, the circuit also includes a third resistor and a second capacitor;

The first end of the third resistor and the first end of the second capacitor are both electrically connected to the output end of the switch chip, and the second end of the third resistor and the second end of the second capacitor are both electrically connected to the input end of the second controller connect.

Further, the circuit also includes a first reserved connection end of the zero-ohm resistance and a second reserved connection end of the zero-ohm resistance;

The first reserved connection end of the zero-ohm resistor is electrically connected with the power switch;

The second reserved connection ends of the zero-ohm resistor are respectively electrically connected with the second controller and the switch module.

Further, the first controller includes an EC; the second controller includes a PMIC.

In a second aspect, an embodiment of the present invention further provides an electronic device, where the electronic device includes the initialization control circuit provided in any one of the foregoing aspects.

According to the technical solution of the embodiment of the present invention, by connecting the power switch, the first controller, the switch module and the second controller in series in sequence, when the power switch is closed, the first controller first completes initialization and is controlled by the first controller. The switch module is turned on, so that the second controller completes the initialization, so that the first controller and the second controller complete the initialization in sequence.

Description of drawings

In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description The drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative work.

1 is a schematic structural diagram of an existing initialization control circuit;

2 is a schematic structural diagram of an initialization control circuit provided by an embodiment of the present invention;

3 is a schematic structural diagram of another initialization control circuit provided by an embodiment of the present invention;

4 is a schematic structural diagram of yet another initialization control circuit provided by an embodiment of the present invention;

5 is a schematic structural diagram of another initialization control circuit provided by an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a compatible initialization control circuit provided by an embodiment of the present invention.

Detailed ways

The present utility model will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, the drawings only show some but not all structures related to the present invention.

FIG. 2 is a schematic structural diagram of an initialization control circuit provided by an embodiment of the present invention. As shown in FIG. 2, the circuit includes a power switch 10, a first controller 20, a switch module 30 and a second controller 40. The power switch 10 is electrically connected to the first controller 20, the first controller 20 is electrically connected to the second controller 40 through the switch module 30, and the first controller 20 controls the switch module 30 to conduct.

Among them, the power switch 10 refers to a switch controlled by the power button of the computer. The computer can be started by pressing the power button. During the startup process of the computer, many controllers (chips) are initialized. Here, the first controller 20 and The second controller 40 is taken as an example to illustrate the working mechanism of the initialization control circuit provided by the embodiment of the present invention.

Wherein, the importance or priority of the first controller 20 is higher than that of the second controller 40, and the priority of the controller can be defined according to manufacturer requirements or chip functions, which is not limited in this embodiment of the present invention . Taking EC and PMIC as an example, if the priority of EC is higher than that of PMIC, then EC is the first controller 20, and PMIC is the second controller 40. On the contrary, if the priority of PMIC is higher than that of EC, then PMIC is the first controller. The controller 20, EC is the second controller 40.

It should be noted that the importance of EC and PMIC in many chips in the system is relatively high. Therefore, EC and PMIC are used as the first controller 20 and the second controller 40 here. For other chips in the system, the The same applies to the initialization control circuit.

The on and off of the switch module 30 is controlled by the first controller 20. After the first controller 20 receives the power-on signal of the power switch 10, it first completes its own initialization, and then controls the switch module 30 to turn on, so that The power-on signal is transmitted to the second controller 40 to complete the initialization of the second controller 40 . It should be noted that the switch module 30 may be any device known to those skilled in the art, and the turn-on and turn-off of the device may be determined by the output signal of the first controller 20 , which is not limited in this embodiment of the present invention.

According to the technical solution of the embodiment of the present invention, by connecting the power switch, the first controller, the switch module and the second controller in series in sequence, when the power switch is closed, the first controller first completes initialization and is controlled by the first controller. The switch module is turned on, so that the second controller completes the initialization, so that the first controller and the second controller complete the initialization in sequence.

Below, based on different selections of the switch module 30, two specific implementations of the initialization control circuit provided by the embodiments of the present invention are introduced.

FIG. 3 is a schematic structural diagram of another initialization control circuit provided by an embodiment of the present invention, and the circuit structure shown in FIG. 3 is a first implementation manner. 3 , optionally, the switch module 30 includes a diode 310 , the cathode of the diode 310 is electrically connected to the output terminal 22 of the first controller 20 , and the anode of the diode 310 is electrically connected to the input terminal 41 of the second controller 40 .

It can be understood that since the cathode of the diode 310 is electrically connected to the output end 22 of the first controller 20, only when the output end 22 of the first controller 20 outputs a low-level signal, the input end 41 of the second controller 40 Only then can a low-level power-on signal be received, so as to achieve the purpose of initializing the first controller 20 and then initializing the second controller 40 . This solution only needs to add one diode 310 to meet the requirement of starting the first controller 20 and the second controller 40 in sequence, and the cost is extremely low, the load of the system is basically not increased, and the practicability is high.

FIG. 4 is a schematic structural diagram of still another initialization control circuit provided by an embodiment of the present invention, and the circuit structure shown in FIG. 4 is a second implementation manner. Referring to FIG. 4 , optionally, the switch module 30 includes a switch chip 320 , the control terminal 31 of the switch chip 320 is electrically connected to the control terminal 21 of the first controller 20 , and the input terminal 32 of the switch chip 320 is electrically connected to the control terminal 21 of the first controller 20 . The output terminal 22 is electrically connected, and the output terminal 33 of the switch chip 320 is electrically connected to the input terminal 41 of the second controller 40 .

Specifically, by controlling the switch chip 320 by the first controller 20, after the first controller 20 completes the initialization, the input terminal 32 and the output terminal 33 of the switch chip 320 can be controlled to conduct, so that the second controller 40 completes the initialization, so as to realize the purpose of initializing the first controller 20 and the second controller 40 in sequence.

Continue to refer to FIG. 4 , optionally, the switch chip 320 includes a MOS tube; the control end of the MOS tube is the control end of the switch chip; the input end of the MOS tube is the input end of the switch chip; the output end of the MOS tube is the output end of the switch chip end. Exemplarily, FIG. 4 shows the case where the MOS transistor is a PMOS transistor 321 . Specifically, the gate of the PMOS transistor 321 is electrically connected to the control terminal 31 of the switch chip 320 , and the source of the PMOS transistor 321 is connected to the input of the switch chip 320 . The terminal 32 is electrically connected, and the drain of the PMOS transistor 321 is electrically connected to the output terminal 33 of the switch chip 320 . After the first controller 20 completes the initialization, it can output a low level signal to the gate of the PMOS transistor 321 to make the source and drain of the PMOS transistor 321 conduct, so that the first controller 20 completes the initialization and then initializes the second The purpose of the controller 40.

It should be noted that, in other embodiments, the MOS transistor may also be an NMOS transistor, which is not limited in the embodiments of the present invention.

It should be noted that, in other embodiments, the switch chip 320 can also be replaced by a MOS transistor, so that each functional pin of the MOS transistor is connected to the control terminal 21 and the output terminal 22 of the first controller 20 and the second controller 40 respectively. The input terminal 41 is electrically connected to realize the corresponding function. The specific connection method can be referred to FIG. 4 , which will not be repeated here.

It should also be noted that the signals output by the switch chip 320 or the MOS tube are all high-level signals, and the initialization start signal (ie, the power-on signal) of the controller needs to be a low-level signal. 40 performs related logic circuit design, such as designing a NOT gate circuit to convert the high-level signal transmitted to the input terminal 41 of the second controller 40 into a low-level signal, thereby completing the initialization of the second controller 40 .

Continuing to refer to FIG. 4 , optionally, the switch chip 320 further includes: a first resistor R1 , a second resistor R2 and a comparator 322 . The first end of the first resistor R1 is electrically connected to the output end 33 of the switch chip 320, the second end of the first resistor R1 is electrically connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded; compare The forward input terminal of the comparator 322 is electrically connected to the second terminal of the first resistor R1, the reverse input terminal of the comparator 322 is electrically connected to the input terminal 32 of the switch chip 320, and the output terminal of the comparator 322 is electrically connected to the control terminal of the MOS transistor. electrical connection.

It should be noted that a short circuit or other faults inside the second controller 40 may cause the level value of the input terminal 41 to be too high, and the input terminal 41 of the second controller 40 is electrically connected to the output terminal 33 of the switch chip 320 , when the level value of the input terminal 41 of the second controller 40 is too high and higher than the level value of the input terminal 32 of the switch chip 320 , there will be a transition from the second controller 40 through the switch chip 320 to the first controller the current of the controller 20, the reverse current will seriously affect the first controller 20, making it unable to work normally. Therefore, the level value of the output terminal 33 of the switch chip 320 can be collected through the forward input terminal of the comparator 322, and the level value of the input terminal 32 of the switch chip 320 can be collected through the reverse input terminal of the comparator 322, and the The level of the output terminal 33 of the switch chip 320 is compared with that of the input terminal 32 . If the level of the output terminal 33 is high, it indicates that the second controller 40 is faulty. At this time, the comparator 322 can be used to output a high-level signal to control the gate voltage of the PMOS transistor 321 to turn it off, thereby functioning as a The function of the first controller 20 is protected. In this embodiment, the switch chip 320 can not only realize that the first controller 20 and the second controller 40 are initialized in sequence, but also can effectively prevent the abnormal voltage and current of the second controller 40 from being reversed into the first controller 20. When the overvoltage and overcurrent of the second controller 40 are detected, the input end 32 and the output end 33 of the switch chip 320 are disconnected to cut off the connection between the second controller 40 and the first controller 20 for protection The role of the first controller 20 .

Optionally, the switch chip 320 further includes a first capacitor C1, the first end of the first capacitor C1 is electrically connected to the first end of the first resistor R1, and the second end of the first capacitor C1 is electrically connected to the second end of the first resistor R1. terminal electrical connection.

The setting of the first capacitor C1 makes the current flowing through the first resistor R1 more stable, thereby ensuring that the level signal collected by the positive input terminal of the comparator 322 is more accurate.

FIG. 5 is a schematic structural diagram of another initialization control circuit provided by an embodiment of the present invention. FIG. 5 further optimizes the initialization control circuit on the basis of FIG. 4 . As shown in FIG. 5, optionally, the control circuit further includes a third resistor R3 and a second capacitor C2. The first terminal of the third resistor R3 and the first terminal of the second capacitor C2 are both electrically connected to the output terminal 33 of the switch chip 320 , and the second terminal of the third resistor R3 and the second terminal of the second capacitor C2 are both electrically connected to the output terminal 33 of the switch chip 320 . The input terminal 41 of the controller 40 is electrically connected.

The third resistor R3 and the second capacitor C2 form a delay circuit, and the length of the delay time can be changed by adjusting the sizes of the third resistor R3 and the second capacitor C2. Those skilled in the art can set the sizes of the third resistor R3 and the second capacitor C2 by themselves, which are not limited in the embodiment of the present invention.

FIG. 6 is a schematic structural diagram of a compatible initialization control circuit provided by an embodiment of the present invention. As shown in FIG. 6 , optionally, the circuit further includes a first reserved connection end 51 of the zero-ohm resistance and a second reserved connection end of the zero-ohm resistance 52 , the first reserved connection end 51 of the zero-ohm resistance and the power switch 10 For electrical connection, the second reserved connection terminals 52 of the zero-ohm resistance are electrically connected to the second controller 40 and the switch module 30 respectively.

In order to adapt to different initialization sequence requirements, connection terminals of zero-ohm resistors can be reserved. When the first controller 20 and the second controller 40 need to be initialized at the same time, a zero-ohm resistor can be installed on the reserved position of the circuit board, so that the power-on signal is transmitted to the first controller according to the direction of the bold dotted line in FIG. 6 . The controller 20 and the second controller 40 can be initialized at the same time; when the first controller 20 and the second controller 40 need to be initialized in sequence, the position of the zero-ohm resistor is left idle, and the power-on signal is bolded as shown in FIG. 6 . The direction of the solid line is transmitted to the first controller 20 and the second controller 40 in turn, so that the two complete the initialization in sequence.

On the basis of the above embodiment, optionally, the first controller 20 includes an EC; the second controller 40 includes a PMIC.

It can be understood that the EC is used as the first controller 20 and the PMIC is used as the second controller 40, and the initialization of the PMIC can be performed after the initialization of the EC is completed by adopting any of the above specific implementation manners.

In addition, an embodiment of the present invention also provides an electronic device, the electronic device includes the initialization control circuit provided by any of the above embodiments, so that when the electronic device is powered on, each controller follows the initialization control circuit provided by the embodiment of the present invention. Complete the initialization process. Exemplarily, the electronic device may be a notebook computer, a desktop computer, a tablet computer, or a mobile phone, etc., which is not limited in this embodiment of the present invention.

Note that the above are only preferred embodiments of the present invention and applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments and substitutions can be made to those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present utility model has been described in detail through the above embodiments, the present utility model is not limited to the above embodiments, and can also include more other equivalent embodiments without departing from the concept of the present utility model. Rather, the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. An initialization control circuit is characterized by comprising a power switch, a first controller, a switch module and a second controller;

the power switch is electrically connected with the first controller; the first controller is electrically connected with the second controller through the switch module; the first controller controls the switch module to be conducted.

2. The initialization control circuit of claim 1, wherein the switching module comprises a diode; the cathode of the diode is electrically connected with the output end of the first controller, and the anode of the diode is electrically connected with the input end of the second controller.

3. The initialization control circuit of claim 1, wherein the switch module comprises a switch chip; the control end of the switch chip is electrically connected with the control end of the first controller, the input end of the switch chip is electrically connected with the output end of the first controller, and the output end of the switch chip is electrically connected with the input end of the second controller.

4. The initialization control circuit of claim 3, wherein the switch chip comprises a metal-oxide-semiconductor field effect transistor;

the control end of the metal-oxide-semiconductor field effect transistor is the control end of the switch chip; the input end of the metal-oxide-semiconductor field effect transistor is the input end of the switch chip; and the output end of the metal-oxide-semiconductor field effect transistor is the output end of the switch chip.

5. The initialization control circuit of claim 4, wherein the switch chip further comprises: a first resistor, a second resistor and a comparator;

the first end of the first resistor is electrically connected with the output end of the switch chip, the second end of the first resistor is electrically connected with the first end of the second resistor, and the second end of the second resistor is grounded; the positive input end of the comparator is electrically connected with the second end of the first resistor, the reverse input end of the comparator is electrically connected with the input end of the switch chip, and the output end of the comparator is electrically connected with the control end of the metal-oxide-semiconductor field effect transistor.

6. The initialization control circuit of claim 5, wherein the switch chip further comprises a first capacitor;

the first end of the first capacitor is electrically connected with the first end of the first resistor, and the second end of the first capacitor is electrically connected with the second end of the first resistor.

7. The initialization control circuit of claim 3, further comprising a third resistor and a second capacitor;

the first end of the third resistor and the first end of the second capacitor are both electrically connected with the output end of the switch chip, and the second end of the third resistor and the second end of the second capacitor are both electrically connected with the input end of the second controller.

8. The initialization control circuit of claim 1, further comprising a zero ohm resistor first reserved connection terminal and a zero ohm resistor second reserved connection terminal;

the first reserved connecting end of the zero-ohm resistor is electrically connected with the power switch;

and the second reserved connecting end of the zero-ohm resistor is electrically connected with the second controller and the switch module respectively.

9. The initialization control circuit of any one of claims 1 to 8, wherein the first controller comprises an embedded controller; the second controller includes a power management integrated circuit.

10. An electronic device, characterized in that it comprises an initialization control circuit according to any one of claims 1 to 9.

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