TWI862045B - Semiconductor device and method for operating the same - Google Patents

Abstract

The present disclosure provides a semiconductor device and a method for operating the same. The semiconductor device includes a first device and a second device on a substrate. The first device includes a deep well region extending from a surface of the substrate into the substrate, a body region and a drift region respectively in the deep well region, a source region and a drain region respectively in the body region and the drift region, a gate structure disposed on the surface of the substrate and located on the body region and the drift region, and a field plate disposed on the drift region and extending from the gate structure into the drain region. The second device includes a bottom metal layer, a first and a second gate dielectric layers respectively on the bottom metal layer, a first and a second channel patterns respectively on the first and the second gate dielectric layers, and a first and a second top metal layers respectively on the first and the second channel patterns. The field plate of the first device connects to an output voltage of the second device.

Description

Semiconductor device and method of operating the same

The present invention relates to a semiconductor device and an operating method thereof.

With the development of the semiconductor industry, high-voltage semiconductor devices are widely used in various fields. For example, high-voltage lateral diffused metal oxide semiconductor (LDMOS) is often used in high-voltage integrated circuits because of its high breakdown voltage and low on-state resistance (also known as Ron) during operation.

In order to avoid punch through or severe hot carrier injection (HCI), high voltage semiconductor devices usually need to have a longer channel length and/or drift length. For a longer drift length, in some embodiments, the controllability of the longer drift length can be improved, for example, by placing a field plate above the drift region and applying a fixed voltage thereto.

Generally speaking, high-voltage semiconductor devices including field plates can be roughly divided into two categories, one of which is the gate-side connection type in which the field plate is connected to the gate, and the other is the source-side connection type in which the field plate is connected to the source. In the gate-side connection type, when the high-voltage semiconductor device is in the on-state, Ron decreases and the linear region drain current (Idlin) increases, but a serious HCI effect will occur during the switching process. In the source-side connection type, although Ron can be increased during the switching process to alleviate the HCI effect, it will cause a decrease in Idlin when in the on-state. Therefore, how to integrate the advantages of the above two types is one of the goals that technical personnel in this field are eager to work hard on.

The present invention provides a semiconductor device and an operating method thereof, wherein a field plate included in a first element is connected to a first channel pattern and a second channel pattern included in a second element, so that the field plate can have different potentials (i.e., apply a non-fixed voltage) through the second element in various states/stages (e.g., an on state/switching stage/off state) of the first element. In this way, the semiconductor device can have good electrical performance and reliability.

An embodiment of the present invention provides a semiconductor device, which includes a first element and a second element. The first element is arranged on a substrate and includes a deep well region, a main region and a drift region, a source region and a drain region, a gate structure and a field plate. The deep well region extends from the surface of the substrate into the substrate. The main region and the drift region are respectively in the deep well region. The source region and the drain region are respectively in the main region and the drift region. The gate structure is arranged on the surface of the substrate and is located on the main region and the drift region. The field plate is arranged above the drift region and extends from the gate structure to the drain region. The second element is disposed above the substrate and includes a bottom metal layer, a first gate dielectric layer and a second gate dielectric layer, a first channel pattern and a second channel pattern, and a first top metal layer and a second top metal layer. The first gate dielectric layer and the second gate dielectric layer are disposed on the bottom metal layer, respectively. The first channel pattern and the second channel pattern are disposed on the first gate dielectric layer and the second gate dielectric layer, respectively. The first top metal layer and the second top metal layer are disposed on the first channel pattern and the second channel pattern, respectively. The field plate of the first element is connected to the output voltage of the second element.

In one embodiment of the present invention, the semiconductor device further includes a dielectric layer disposed between the field plate and the drift region to separate the field plate from the drift region.

In one embodiment of the present invention, the dielectric layer covers the sidewalls of the gate structure above the drift region and extends to the top surface of the gate structure.

In one embodiment of the present invention, the first channel pattern and the second channel pattern include semiconductor oxides of different conductivity types.

In one embodiment of the present invention, the first element is a lateral diffused metal oxide semiconductor (LDMOS) element, and the second element is an inverter.

In one embodiment of the present invention, the second element is disposed above the first element, and in a direction perpendicular to the surface of the substrate, the second element includes a portion overlapping with the first element.

In one embodiment of the present invention, a semiconductor device includes a front end of line (FEOL) layer formed in a FEOL process and a back end of line (BEOL) layer formed in a BEOL process, a first element is in the FEOL layer, and a second element is in the BEOL layer.

An embodiment of the present invention provides a method for operating a semiconductor device, comprising: providing a semiconductor device as described above; and switching a first element between an on-state and an off-state. The drain region of the first element is connected to a first operating voltage, and the source region of the first element is connected to a first ground voltage. The first channel pattern of the second element is connected to a second operating voltage, and the second channel pattern of the second element is connected to a second ground voltage.

In one embodiment of the present invention, switching the first element from a closed state to an open state includes: applying a threshold voltage to a gate structure of the first element; and applying a third ground voltage to a bottom metal layer of a second element, so that the second element provides an output voltage derived from a second operating voltage to a field plate of the first element.

In one embodiment of the present invention, switching the first element from an on state to a off state includes: applying a third ground voltage to the gate structure of the first element; and applying a threshold voltage to the bottom metal layer of the second element so that the second element provides an output voltage derived from the second ground voltage to the field plate of the first element.

Based on the above, in the semiconductor device and the operating method thereof of the above embodiment, by connecting the field plate included in the first element to the first channel pattern and the second channel pattern included in the second element, the field plate can have different potentials (i.e., apply non-fixed voltage) through the second element in each state/stage (e.g., open state/switching stage/closed state) of the first element. In this way, the semiconductor device can have good electrical performance and reliability.

The present invention is more fully described with reference to the drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

It should be understood that when an element is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or there may be an intermediate element. If an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connection" may refer to physical and/or electrical connection, and "electrical connection" or "coupling" may be the presence of other elements between two elements. As used herein, "electrical connection" may include physical connection (e.g., wired connection) and physical disconnection (e.g., wireless connection).

As used herein, "about", "approximately" or "substantially" includes the referenced value and the average value within an acceptable deviation range of a specific value that can be determined by a person of ordinary skill in the art, taking into account the measurement in question and the specific amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately" or "substantially" can select a more acceptable deviation range or standard deviation depending on the optical properties, etching properties or other properties, and can apply to all properties without a single standard deviation.

The terms used herein are used to describe exemplary embodiments only, rather than to limit the present disclosure. In this case, unless otherwise explained in the context, the singular form includes the plural form.

Fig. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention. Fig. 2 is a schematic diagram of an operation method of turning on a semiconductor device according to an embodiment of the present invention. Fig. 3 is a schematic diagram of an operation method of turning off a semiconductor device according to an embodiment of the present invention.

1 , the semiconductor device includes a first element 10 and a second element 20. The first element 10 is disposed on a substrate 100 and includes a deep well region HVPW, a drift region 101 and a body region 102, a drain region 103 and a source region (e.g., including a first doped region 104 and a second doped region 105), a gate structure GS, and a field plate FP.

The substrate 100 may include a semiconductor substrate or a semiconductor on insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or SOI substrate may include an elemental semiconductor, an alloy semiconductor, or a compound semiconductor. For example, the elemental semiconductor may include Si or Ge. The alloy semiconductor may include SiGe, SiGeC, etc. The compound semiconductor may include SiC, a III-V semiconductor material, or a II-VI semiconductor material. The III-V semiconductor material may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. Group II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnS e. CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe or HgZnSTe. The semiconductor material may be doped with a first conductivity type dopant or a second conductivity type dopant complementary to the first conductivity type. For example, the first conductivity type may be P type, and the second conductivity type may be N type. In some embodiments, the substrate 100 may be doped with the first conductivity type dopant and have the first conductivity type (eg, P type).

The deep well region HVPW extends from the surface of the substrate 100 into the substrate 100. The deep well region HVPW may have the same conductivity type as the substrate 100, for example, the first conductivity type (for example, P type).

The drift region 101 and the main region 102 are respectively in the deep well region HVPW. The drift region 101 may have a conductivity type different from that of the deep well region HVPW, such as a second conductivity type (e.g., N-type). The main region 102 may have the same conductivity type as that of the deep well region HVPW, such as a first conductivity type (e.g., P-type). The drift region 101 and the main region 102 may extend from the surface of the substrate 100 into the deep well region HVPW. In some embodiments, the drift region 101 and the main region 102 may be spaced apart from each other in a direction horizontal to the surface of the substrate 100.

The drain region 103 is disposed in the drift region 101. The drain region 103 may have the same conductivity type as the drift region 101, such as the second conductivity type (such as N type). The drain region 103 may extend from the surface of the substrate 100 into the drift region 101. The drain region 103 may be connected to the first operating voltage VD.

The source region is disposed in the main region 102 and may include a first doped region 104 and a second doped region 105. The first doped region 104 may have the same conductivity type as the main region 102, for example, a first conductivity type (for example, a P type). The second doped region 105 may have a conductivity type different from the main region 102 and the first doped region 104, for example, a second conductivity type (for example, an N type). The first doped region 104 and the second doped region 105 may extend from the surface of the substrate 100 into the main region 102, respectively. The second doped region 105 may be closer to the gate structure GS than the first doped region 104. The first doped region 104 and the second doped region 105 contact each other in a direction horizontal to the surface of the substrate 100. The source region may be connected to a first ground voltage GND1.

The gate structure GS is disposed on the surface of the substrate 100 and is located on the drift region 101 and the main region 102. The gate structure GS may include a gate electrode GE and a gate dielectric layer GD formed on the substrate 100 and located between the gate electrode GE and the substrate 100. The material of the gate electrode GE may include polysilicon or a metal gate material. The material of the gate dielectric layer GD may include silicon dioxide or a gate dielectric material having a high dielectric constant (high-k).

The field plate FP is disposed above the drift region 101 and extends from the gate structure GS to the drain region 103. The field plate FP may include a conductive material such as a metal. In some embodiments, the field plate FP may be separated from the drift region 101 by a dielectric layer 110 disposed between the field plate FP and the drift region 101. In some embodiments, the dielectric layer 110 may cover the sidewall of the gate structure GS located above the drift region 101 and extend to the top surface of the gate structure GS. For example, the gate structure GS may include a first portion overlapping with the drift region 101 and a second portion overlapping with the main region 102 in a direction perpendicular to the substrate 100. The dielectric layer 110 may cover the sidewall of the gate structure GS above the drift region 101 and extend to the top surface of the first portion of the gate structure GS. In some embodiments, the dielectric layer 110 does not cover the top surface of the second portion of the gate structure GS. In some embodiments, the dielectric layer 110 may be a resistive protective oxide (RPO), and its material may include an oxide suitable for being an RPO, such as silicon oxide.

The second element 20 is disposed above the substrate 100 and includes a bottom metal layer BM, a first gate dielectric layer GD1 and a second gate dielectric layer GD2, a first channel pattern CH1 and a second channel pattern CH2, and a first top metal layer TM1 and a second top metal layer TM2. In some embodiments, the second element 20 may be disposed above the first element 10, and in a direction perpendicular to the surface of the substrate 100, the second element 20 may include a portion overlapping with the first element 10.

The first gate dielectric layer GD1 and the second gate dielectric layer GD2 are respectively disposed on the bottom metal layer BM. In some embodiments, the bottom metal layer BM may be a film layer formed in the back-end process (BEOL). The bottom metal layer BM may include a conductive material. For example, the conductive material may include metals such as Cu, Al, Ti, Ta, W, Pt, Cr, Mo, Sn, or a combination of these metals or an alloy thereof. The first gate dielectric layer GD1 and the second gate dielectric layer GD2 may be separated from each other in a direction horizontal to the substrate 100. The first gate dielectric layer GD1 and the second gate dielectric layer GD2 may include materials such as nitrides (e.g., Si ₃ N ₄ ).

The first channel pattern CH1 and the second channel pattern CH2 are disposed on the first gate dielectric layer GD1 and the second gate dielectric layer GD2, respectively. In some embodiments, the first channel pattern CH1 and the second channel pattern CH2 may have different conductivity types, for example, the first channel pattern CH1 may have a first conductivity type (e.g., P-type), and the second channel pattern CH2 may have a second conductivity type (e.g., N-type). For example, the first channel pattern CH1 and the second channel pattern CH2 may include semiconductor oxides of different conductivity types. The first channel pattern CH1 may include a material as a P-type channel (e.g., SnO), and the second channel pattern CH2 may include a material as an N-type channel (e.g., IGZO).

The first channel pattern CH1 may be connected to the second operating voltage VDD, and the second channel pattern CH2 may be connected to the second ground voltage GND2. In some embodiments, the second ground voltage GND2 and the first ground voltage GND1 may be connected to each other and to a common ground voltage.

The first top metal layer TM1 and the second top metal layer TM2 are disposed on the first channel pattern CH1 and the second channel pattern CH2, respectively. The first top metal layer TM1 and the second top metal layer TM2 may include a conductive material. For example, the conductive material may include metals such as Cu, Al, Ti, Ta, W, Pt, Cr, Mo, Sn, or a combination of these metals or an alloy thereof.

In this embodiment, the field plate FP of the first element 10 is connected to the output voltage Vout of the second element 20 (the output voltage Vout is connected to the first channel pattern CH1 and the second channel pattern CH2). In this way, the field plate FP can have different potentials (i.e., apply a non-fixed voltage) through the second element 20 in various states/stages of the first element 10 (e.g., open state/switching stage/closed state), so that the semiconductor device can have good electrical performance and reliability.

The following will illustrate the operation method of the semiconductor device with reference to Figures 1 to 3. The operation method includes: providing the semiconductor device described above; and switching the first element 10 between an on-state and an off-state.

1 and 2 , the drain region 103 of the first element 10 is connected to the first operating voltage VD, the source region (e.g., including the first doping region 104 and the second doping region 105) of the first element 10 is connected to the first ground voltage GND1, and the first channel pattern CH1 of the second element 20 is connected to the second operating voltage VDD, and the second channel pattern CH2 of the second element 20 is connected to the second ground voltage GND2. Switching the first element 10 from the closed state to the open state includes: applying a threshold voltage Vin1 (i.e., Vin1=“1”) to the gate structure GS of the first element 10; and applying a third ground voltage Vin2 (i.e., Vin2=“0”) to the bottom metal layer BM of the second element 20, so that the second element 20 provides an output voltage Vout (i.e., Vout=“1”) derived from the second working voltage VDD to the field plate FP of the first element 10. In this way, the electron concentration of the drift region 101 of the first element 10 is increased, the turn-on resistance (Ron) is reduced, and the linear region drain current (Idlin) is increased, so as to increase the speed of the first element 10 and reduce its power consumption.

1 and 3 , the drain region 103 of the first element 10 is connected to the first operating voltage VD, the source region (e.g., including the first doping region 104 and the second doping region 105) of the first element 10 is connected to the first ground voltage GND1, and the first channel pattern CH1 of the second element 20 is connected to the second operating voltage VDD, and the second channel pattern CH2 of the second element 20 is connected to the second ground voltage GND2. Switching the first element 10 from the on state to the off state includes: applying a third ground voltage Vin1 (i.e., Vin1=“0”) to the gate structure GS of the first element 10; and applying a threshold voltage (i.e., Vin2=“1”) to the bottom metal layer BM of the second element 20, so that the second element 20 provides the output voltage Vout (i.e., Vout=“0”) derived from the second ground voltage GND2 to the field plate FP of the first element 10. In this way, the electron concentration of the drift region 101 of the first element 10 is reduced, so that the resistance of the drift region 101 is increased, so that the resistance to the hot carrier injection (HCI) effect in the switching stage can be improved and the first element 10 can be helped to reach the off state faster. After reaching the off state, since the field plate FP is provided with the output voltage Vout (ie, Vout=“0”) derived from the second ground voltage GND2 which can serve as a floating potential, the breakdown voltage (eg, BVdss) of the first element 10 can be increased.

In some embodiments, the first device 10 may be, for example, a lateral diffused metal oxide semiconductor (LDMOS) device, and the second device 20 may be, for example, an inverter.

In some embodiments, the semiconductor device may include a FEOL layer FEOL formed in a front-end-of-line (FEOL) process and a BEOL layer BEOL formed in a back-end-of-line (BEOL) process, wherein the first element 10 is in the FEOL layer FEOL and the second element 20 is in the BEOL layer BEOL. In this way, the semiconductor device may have a lower thermal budget and lower process complexity in the process, and may be easily integrated into a silicon-based complementary metal oxide semiconductor (Si-based CMOS) process.

In summary, in the semiconductor device and the operating method thereof of the above-mentioned embodiment, by connecting the field plate included in the first element to the first channel pattern and the second channel pattern included in the second element, the field plate can have different potentials (i.e., apply non-fixed voltage) through the second element in various states/stages (e.g., open state/switching stage/closed state) of the first element. In this way, the semiconductor device can have good electrical performance and reliability.

10: First element 20: Second element 100: Substrate 101: Drift region 102: Body region 103: Drain region 104: First doped region 105: Second doped region 110: Dielectric layer BM: Bottom metal layer BEOL: BEOL layer CH1: First channel pattern CH2: Second channel pattern FP: Field plate FEOL: FEOL layer GS: Gate structure GE: Gate electrode GD: Gate dielectric layer GND1: First ground voltage GND2: Second ground voltage HVPW: Deep well region GD1: First gate dielectric layer GD2: Second gate dielectric layer TM1: First top metal layer TM2: Second top metal layer VD: First operating voltage VDD: Second operating voltage Vin1, Vin2: Threshold voltage/third ground voltage Vout: Output voltage

FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of an operating method for turning on a semiconductor device according to an embodiment of the present invention. FIG. 3 is a schematic diagram of an operating method for turning off a semiconductor device according to an embodiment of the present invention.

10: First element

20: Second element

100: Base

101: Drift Zone

102: Main area

103: Drain area

104: First mixed area

105: Second mixed area

110: Dielectric layer

BM: Bottom metal layer

BEOL:BEOL layer

CH1: First channel pattern

CH2: Second channel pattern

FP: Field board

FEOL:FEOL layer

GS: Gate structure

GE: Gate electrode

GD: Gate dielectric layer

GND1: First ground voltage

GND2: Second ground voltage

HVPW: Deep well area

GD1: First gate dielectric layer

GD2: Second gate dielectric layer

TM1: First top metal layer

TM2: Second top metal layer

VD: First working voltage

VDD: Second operating voltage

Vin1, Vin2: Threshold voltage/third ground voltage

Vout: output voltage

Claims (10)

A semiconductor device comprises: a first element disposed on a substrate and comprising: a deep well region extending from the surface of the substrate into the substrate; a main region and a drift region respectively in the deep well region; a source region and a drain region respectively in the main region and the drift region; a gate structure disposed on the surface of the substrate and located on the main region and the drift region; and a field plate disposed above the drift region and extending from the gate structure to the drain region; and a second element disposed above the substrate and comprising: a bottom metal layer; a first gate dielectric layer and a second gate dielectric layer, respectively disposed on the bottom metal layer; a first channel pattern and a second channel pattern, respectively disposed on the first gate dielectric layer and the second gate dielectric layer; and a first top metal layer and a second top metal layer, respectively disposed on the first channel pattern and the second channel pattern, wherein the output voltage of the second element is transmitted through the first channel pattern or the second channel pattern, and the output voltage of the second element is connected to the field plate of the first element. The semiconductor device as described in claim 1 further includes: A dielectric layer disposed between the field plate and the drift region to separate the field plate from the drift region. A semiconductor device as described in claim 2, wherein the dielectric layer covers the sidewall of the gate structure above the drift region and extends to the top surface of the gate structure. A semiconductor device as described in claim 1, wherein the first channel pattern and the second channel pattern include semiconductor oxides of different conductivity types. A semiconductor device as described in claim 1, wherein the first element is a lateral diffused metal oxide semiconductor (LDMOS) element, and the second element is an inverter. A semiconductor device as described in claim 1, wherein the second element is disposed above the first element, and in a direction perpendicular to the surface of the substrate, the second element includes a portion overlapping with the first element. A semiconductor device as described in claim 1, wherein the semiconductor device includes a front-end-of-line (FEOL) layer formed in a FEOL process and a back-end-of-line (BEOL) layer formed in a BEOL process, the first element is in the FEOL layer, and the second element is in the BEOL layer. A method for operating a semiconductor device, comprising: providing a semiconductor device as described in claim 1; and switching the first element between an on-state and an off-state, wherein the drain region of the first element is connected to a first operating voltage, the source region of the first element is connected to a first ground voltage, and the first channel pattern of the second element is connected to a second operating voltage, and the second channel pattern of the second element is connected to a second ground voltage. The operating method as described in claim 8, wherein switching the first element from the closed state to the open state comprises: applying a threshold voltage to the gate structure of the first element; and applying a third ground voltage to the bottom metal layer of the second element, so that the second element provides an output voltage derived from the second operating voltage to the field plate of the first element. The operating method as described in claim 8, wherein switching the first element from the on state to the off state comprises: applying a third ground voltage to the gate structure of the first element; and applying a threshold voltage to the bottom metal layer of the second element, so that the second element provides an output voltage derived from the second ground voltage to the field plate of the first element.

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