CN115939201A - High Electron Mobility Transistor Devices - Google Patents

Abstract

The invention provides a high electron mobility transistor device which comprises a substrate, a semiconductor stacked layer, a grid electrode, a source electrode, a drain electrode and a first Schottky electrode. The semiconductor stack layer is disposed on the substrate. The grid is arranged on the semiconductor stacking layer. The source and the drain are respectively electrically connected with the semiconductor stacked layer. The source, the gate and the drain are arranged in sequence along a first direction. The first Schottky electrode has a Schottky contact with the semiconductor stacked layer, and the first Schottky electrode is electrically connected to the source. The grid and the first Schottky electrode are arranged along a second direction, and the second direction is vertical to the first direction. By integrating the hemt with the schottky diode, the overall performance of the hemt device may be improved.

Description

High Electron Mobility Transistor Devices

technical field

The present invention relates to a high electron mobility transistor device, and more particularly to a high electron mobility transistor device comprising a Schottky electrode.

Background technique

A high electron mobility transistor (HEMT) is a type of transistor. A HEMT includes a heterojunction formed by two semiconductor materials with different energy gaps. The heterojunction can generate two-dimensional electron gas or two-dimensional hole gas, which can be used as the conductive channel of HEMT. Due to the advantages of low resistance, high breakdown voltage, and fast switching frequency, HEMTs are widely used in the field of high-power electronic components.

HEMTs can be classified as depletion mode or enhancement mode HEMTs according to whether the channel is normally open or normally closed. Enhancement mode transistor devices have gained considerable attention in the industry because of the added safety they provide and because they are easier to control with simple, low-cost driver circuits.

Contents of the invention

The present invention provides a high electron mobility transistor device. By integrating a HEMT and a Schottky Barrier Diode (SBD), the overall performance of the high electron mobility transistor device can be improved.

At least one embodiment of the present invention provides a high electron mobility transistor device including a substrate, a semiconductor stack, a gate, a source, a drain, and a first Schottky electrode. The semiconductor stack layer is disposed on the substrate, and the semiconductor stack layer includes a first isolation structure. The gate is disposed on the semiconductor stack. The source and the drain are electrically connected to the semiconductor stack layer respectively. The source, the gate and the drain are arranged in sequence along the first direction. There is a Schottky contact between the first Schottky electrode and the semiconductor stack layer, and the first Schottky electrode is electrically connected to the source. The gate and the first Schottky electrode are arranged along a second direction, wherein the first direction and the second direction are parallel to the surface of the substrate, and the second direction is perpendicular to the first direction. The first Schottky electrode and the semiconductor stack constitute a first Schottky diode, the first Schottky diode is electrically connected to the source and the drain, and the first isolation structure is laterally located between the first Schottky electrode and the gate. between and between the first Schottky electrode and the source.

In some embodiments, the first isolation structure electrically isolates the semiconductor stack layer below the first Schottky electrode from the semiconductor stack layer below the gate, and the first isolation structure electrically isolates the semiconductor stack layer below the first Schottky electrode. Electrically isolated from the semiconductor stack layer below the source.

In some embodiments, the high electron mobility transistor device further includes field effect electrodes. The field effect electric plate is electrically connected to the grid and is located above the grid and the first Schottky electrode.

In some embodiments, in the first direction, the distance between the gate and the drain is equal to the distance between the first Schottky electrode and the drain.

In some embodiments, the high electron mobility transistor device further includes a first ohmic electrode and a second Schottky electrode. The first ohmic electrode has an ohmic contact with the semiconductor stack layer and is electrically connected to the gate, wherein the gate, the first Schottky electrode and the first ohmic electrode are arranged along the second direction. There is a Schottky contact between the second Schottky electrode and the semiconductor stack layer. The source electrode and the second Schottky electrode are arranged along the second direction. A second Schottky diode composed of a second Schottky electrode and a semiconductor stack layer is included between the source and the gate.

In some embodiments, a second isolation structure is included in the semiconductor stack layer. The second isolation structure is laterally located between the first ohmic electrode and the gate and between the first ohmic electrode and the drain, and the second isolation structure is laterally located between the second Schottky electrode and the source, wherein the second The isolation structure electrically isolates the semiconductor stack layer below the first ohmic electrode from the semiconductor stack layer below the gate, and the second isolation structure electrically isolates the semiconductor stack layer below the first ohmic electrode from the semiconductor stack layer below the drain, and Wherein the second isolation structure electrically isolates the semiconductor stack layer under the second Schottky electrode from the semiconductor stack layer under the source electrode.

In some embodiments, the second Schottky diode is electrically connected to the source and the gate.

In some embodiments, the source has an ohmic contact with the semiconductor stack, and the drain has an ohmic contact with the semiconductor stack.

At least one embodiment of the present invention provides a high electron mobility transistor device including a substrate, a semiconductor stack, a gate, a source, a drain, a first ohmic electrode, and a first Schottky electrode. The semiconductor stack layer is disposed on the substrate, wherein the semiconductor stack layer includes a first isolation structure. The gate is disposed on the semiconductor stack. The source and the drain are electrically connected to the semiconductor stack layer respectively. The source, the gate and the drain are arranged in sequence along the first direction. There is an ohmic contact between the first ohmic electrode and the semiconductor stack layer. The first ohmic electrode is electrically connected to the gate. The first ohmic electrode and the grid are arranged along a second direction, wherein the first direction and the second direction are parallel to the surface of the substrate, and the second direction is perpendicular to the first direction. The first isolation structure is laterally located between the first ohmic electrode and the gate and between the first ohmic electrode and the drain. There is a Schottky contact between the first Schottky electrode and the semiconductor stack layer. The source electrode and the first Schottky electrode are arranged along the second direction. A first Schottky diode composed of a first Schottky electrode and a semiconductor stack layer is included between the source and the gate. The first isolation structure is laterally located between the first Schottky electrode and the source.

In some embodiments, the first isolation structure electrically isolates the semiconductor stack layer below the first ohmic electrode from the semiconductor stack layer below the gate, and the first isolation structure electrically isolates the semiconductor stack layer below the first ohmic electrode from the semiconductor stack layer below the drain. The semiconductor stack is electrically isolated, and the first isolation structure electrically isolates the semiconductor stack under the first Schottky electrode from the semiconductor stack under the source.

In some embodiments, the first Schottky diode is electrically connected to the source and the gate.

In some embodiments, the source has an ohmic contact with the semiconductor stack, and the drain has an ohmic contact with the semiconductor stack.

In some embodiments, the high electron mobility transistor device further includes field effect electrodes. The field effect electric plate is electrically connected to the grid and located above the grid and the first ohmic electrode.

In some embodiments, the high electron mobility transistor device further includes a second ohmic electrode and a second Schottky electrode. There is an ohmic contact between the second ohmic electrode and the semiconductor stack layer, and is electrically connected to the first Schottky electrode. There is a Schottky contact between the second Schottky electrode and the semiconductor stack layer. The second Schottky electrode and the semiconductor stack constitute a second Schottky diode. The first Schottky diode and the second Schottky diode are connected in series between the source and the gate.

In some embodiments, the second ohmic electrode is located between the first ohmic electrode and the gate.

In some embodiments, the source, the first Schottky electrode and the second Schottky electrode are arranged along the second direction, and the first ohmic electrode, the second ohmic electrode and the gate are arranged along the second direction.

Based on the above, by integrating the HEMT and the SBD, the efficiency loss of the reverse conduction (Reverseconduction) mode and/or the component failure caused by the electrostatic discharge (Electrostatic Discharge, ESD) can be reduced.

Description of drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain principles of the invention.

FIG. 1A is a schematic top view of a high electron mobility transistor device according to an embodiment of the present invention.

Fig. 1B is a schematic cross-sectional view along line a-a' of Fig. 1A.

Fig. 1C is a schematic cross-sectional view along line b-b' of Fig. 1A.

Fig. 1D is a schematic cross-sectional view along line c-c' of Fig. 1A.

FIG. 1E is a schematic circuit diagram of the high electron mobility transistor device of FIG. 1A .

FIG. 2A is a schematic top view of a high electron mobility transistor device according to an embodiment of the present invention.

Fig. 2B is a schematic cross-sectional view along line a-a' of Fig. 2A.

Fig. 2C is a schematic cross-sectional view along line b-b' of Fig. 2A.

Fig. 2D is a schematic cross-sectional view along line c-c' of Fig. 2A.

2E is a schematic circuit diagram of the high electron mobility transistor device of FIG. 2A.

FIG. 3A is a schematic top view of a high electron mobility transistor device according to an embodiment of the present invention.

Fig. 3B is a schematic cross-sectional view along line d-d' and e-e' in Fig. 3A.

3C is a schematic circuit diagram of the high electron mobility transistor device of FIG. 3A.

FIG. 4A is a schematic top view of a high electron mobility transistor device according to an embodiment of the present invention.

FIG. 4B is a schematic circuit diagram of the high electron mobility transistor device of FIG. 4A .

FIG. 5A is a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present invention.

FIG. 5B is a schematic cross-sectional view of a Schottky diode according to an embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of a Schottky diode according to an embodiment of the present invention.

Explanation of reference numbers

10,20,30: high electron mobility transistor devices;

100: substrate;

102: nucleation layer;

104: buffer layer;

106: channel layer;

108: barrier layer;

110: semiconductor stacked layer;

120: dielectric structure;

210: gate;

220: source;

220B, 230B, 320B: bottom surface;

230: drain;

240: P-type gallium nitride layer;

310,350: conductive structures;

320a, 320b, 320ba, 320bb, 320bc: Schottky electrodes;

330a, 330b, 330c: isolation structures;

340, 340a, 340b, 340c: ohmic electrodes;

360a, 360b: conductive structure;

a-a',b-b',c-c',d-d',e-e': line;

D1: first direction;

D2: second direction;

Id, Ir: direction;

FP: field effect panel;

HEMT: High Electron Mobility Transistor;

SBD1, SBD2, SBD2a, SBD2b, SBD2c: Schottky diodes;

V1, V2, V2a, V3, V4, V4a: distance.

Detailed ways

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and descriptions to refer to the same or like parts.

FIG. 1A is a schematic top view of a high electron mobility transistor device according to an embodiment of the present invention.

Fig. 1B is a schematic cross-sectional view along line a-a' of Fig. 1A. Fig. 1C is a schematic cross-sectional view along line b-b' of Fig. 1A.

Fig. 1D is a schematic cross-sectional view along line c-c' of Fig. 1A.

Referring to FIG. 1A to FIG. 1E , the high electron mobility transistor device 10 includes a substrate 100 , a semiconductor stack 110 , a gate 210 , a source 220 , a drain 230 and a Schottky electrode 320 a.

In some embodiments, the substrate 100 includes a semiconductor substrate or a semiconductor on insulator (SOI) substrate, wherein the semiconductor material in the semiconductor substrate or the SOI substrate may include elemental semiconductors, alloy semiconductors or compound semiconductors. Elemental semiconductors may include Si or Ge, for example. Alloy semiconductors may include SiGe, SiGeC, and the like. The compound semiconductor may include SiC, a group III-V semiconductor material, or a group II-VI semiconductor material. Group III-V semiconductor materials may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNPs, GaInNAs, GaInPAs, InAlNPs, InAlNAs or InAlPAs. Group II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, or HgZnSTe. Additionally, the semiconductor material may be doped to a first conductivity type or a second conductivity type that is complementary to the first conductivity type. For example, the first conductivity type can be N type, and the second conductivity type can be P type.

The semiconductor stack layer 110 is disposed on the substrate 100 and includes a nucleation layer 102 , a buffer layer 104 , a channel layer 106 and a barrier layer 108 .

The channel layer 106 is disposed above the substrate 100 . In one embodiment, the material of the channel layer 106 includes III-nitrides, such as III-V compound semiconductor materials. In some embodiments, the material of the channel layer 106 includes GaN. Channel layer 106 may be a doped or undoped layer. In some embodiments, the channel layer 106 has a two-dimensional electron gas (2DEG) therein below the interface between the channel layer 106 and the overlying barrier layer 108 .

The nucleation layer 102 and the buffer layer 104 can be disposed between the substrate 100 and the channel layer 106 to reduce the stress caused by the difference in lattice constant and/or the difference in thermal expansion coefficient between the substrate 100 and the channel layer 106 . More specifically, the nucleation layer 102 is in contact with the upper surface of the substrate 100 , and the buffer layer 104 is disposed between the nucleation layer 102 and the channel layer 106 . In one embodiment, the material of the nucleation layer 102 includes III-nitrides, such as III-V compound semiconductor materials. In one embodiment, the material of the nucleation layer 102 includes AlN, GaN, AlGaN or a combination thereof. In one embodiment, the material of the buffer layer 104 includes group III nitrides, such as group III-V compound semiconductor materials, and may have a single-layer or multi-layer structure. In one embodiment, the material of the buffer layer 104 includes AlN, GaN, AlGaN, InGaN, AlInN, AlGaInN or a combination thereof.

The barrier layer 108 is disposed on the channel layer 106 . In an embodiment, the material of the barrier layer 108 includes group III nitrides, such as group III-V compound semiconductor materials, and may have a single-layer or multi-layer structure. In one embodiment, the barrier layer 108 includes AlGaN, AlInN, AlN or AlGaInN or a combination thereof. Barrier layer 108 may be a doped or undoped layer.

The gate 210 is disposed on the semiconductor stack 110 . In one embodiment, the material of the gate 210 includes metal or metal nitride (such as Ta, TaN, Ti, TiN, W, Pd, Ni, Au, Al or a combination thereof), metal silicide (such as WSix) or other Materials that can form Schottky contacts with III-V compound semiconductors.

In this embodiment, the P-type gallium nitride (GaN) layer 240 is disposed between the gate 210 and the barrier layer 108 . The p-type gallium nitride layer 240 is used to form a disconnected region of two-dimensional electron gas or a region with a relatively low electron density, so the material of the p-type gallium nitride layer 240 is doped with a dopant (such as magnesium). gallium nitride. In some embodiments, in order to suppress the redistribution of dopants in the p-type gallium nitride layer 240, a low-temperature aluminum nitride layer (not shown) is disposed under the p-type gallium nitride layer 240, the "low temperature" herein "The aluminum nitride layer refers to the aluminum nitride layer formed at an epitaxial temperature lower than that usually used in the epitaxial process of HEMT elements (such as more than 1,000 degrees Celsius), for example, the epitaxial temperature is formed between 700 ° C and 800 ° C aluminum nitride layer.

The source 220 and the drain 230 are respectively electrically connected to the semiconductor stack 110 . The source 220 and the drain 230 are disposed on the barrier layer 108 . However, the present invention is not limited thereto. In one embodiment, at least one of the source electrode 220 and/or the drain electrode 230 may extend into the channel layer 106 and be electrically connected to the two-dimensional electron gas. In one embodiment, the material of the source electrode 220 and the drain electrode 230 includes metal (such as Al, Ti, Ni, Au or alloys thereof), or other materials that can form Ohmic contact with III-V compound semiconductors. . In other words, there is an ohmic contact between the source 220 and the semiconductor stack 110 , and there is an ohmic contact between the drain 230 and the semiconductor stack 110 , but the invention is not limited thereto. In other embodiments, the source 220 and the drain 230 may also be selected from materials that can form Schottky contacts with III-V compound semiconductors.

The Schottky electrode 320 a is disposed on the barrier layer 108 , and there is a Schottky contact between the Schottky electrode 320 a and the semiconductor stack layer 110 . In some embodiments, the material of the Schottky electrode 320a includes metal or metal nitride (such as Ta, TaN, Ti, TiN, W, Pd, Ni, Au, Al or combinations thereof), metal silicide (such as WSix) Or other materials that can form Schottky contacts with III-V compound semiconductors. In some embodiments, the Schottky electrode 320 a and the gate 210 include the same material, but the invention is not limited thereto.

The Schottky electrode 320 a is electrically connected to the source 220 . In this embodiment, the source electrode 220 is electrically connected to the Schottky electrode 320a through the conductive structure 310 . In some embodiments, the material of the conductive structure 310 includes metal, metal nitride, metal oxide or other suitable materials.

In this embodiment, the Schottky electrode 320a and the semiconductor stacked layer 110 constitute a Schottky diode SBD1. There is a Schottky diode SBD1 between the source 220 and the drain 230, and the Schottky diode SBD1 is electrically connected to the source 220 and the drain 230, wherein the HEMT includes the source 220, the gate 210 and the drain 230, as shown in FIG. 1E is shown in the schematic circuit diagram.

The field effect panel FP is electrically connected to the grid 210 . In some embodiments, the field effect plate FP includes conductive materials, such as metals, metal nitrides, metal oxides or other suitable materials. In some embodiments, the field effect plate FP, the source 220 and the drain 230 extend along the second direction D2 and are separated from each other. The field effect plate FP is located above the gate 210 and the Schottky electrode 320a, and extends from above the gate 210 and the Schottky electrode 320a toward the drain 230 to cover the part between the gate 210 and the drain 230 The semiconductor stack 110 and a part of the semiconductor stack 110 between the Schottky electrode 320 a and the drain 230 .

The dielectric structure 120 is located on the semiconductor stack 110 . It should be noted that, for the convenience of illustration, the dielectric structure 120 is omitted to be shown as a single-layer structure in FIG. 1B to FIG. 1C , but actually, the dielectric structure 120 may include a single-layer or multi-layer insulating layer. For example, the dielectric structure 120 includes silicon nitride, silicon oxide, aluminum oxide, hafnium oxide or other insulating materials or stacked layers of the above materials. In some embodiments, the gate 210, the source 220, the drain 230, the conductive structure 310, the Schottky electrode 320a, and the field effect plate FP each comprise a single-layer or multi-layer structure, and are distributed in the dielectric structure 120 or on the dielectric structure 120 .

In this embodiment, the semiconductor stack layer 110 includes an isolation structure 330 a. The isolation structure 330 a extends downward from the top surface of the semiconductor stack 110 beyond the 2D electron gas.

The isolation structure 330a is laterally located between the Schottky electrode 320a and the gate 210, thereby preventing current from directly passing through the semiconductor stack between the semiconductor stack 110 below the Schottky electrode 320a and the semiconductor stack 110 below the gate 210. Layer 110 delivery. In other words, the isolation structure 330 a electrically isolates the semiconductor stack 110 below the Schottky electrode 320 a from the semiconductor stack 110 below the gate 210 . In addition, the isolation structure 330a is laterally located between the Schottky electrode 320a and the source 220, so that the current can flow into the semiconductor stack layer 110 below the Schottky electrode 320a through the Schottky electrode 320a without being transferred from the Schottky electrode 320a. The semiconductor stacked layer 110 below the source electrode 220 flows directly through the semiconductor stacked layer 110 into the semiconductor stacked layer 110 below the Schottky electrode 320a. In other words, the isolation structure 330 a electrically isolates the semiconductor stack 110 below the Schottky electrode 320 a from the semiconductor stack 110 below the source 220 .

In this embodiment, the isolation structure 330a is located between the vertical projection of the Schottky electrode 320a on the semiconductor stack layer 110 and the vertical projection of the gate 210 on the semiconductor stack layer 110, and the isolation structure 330a is located between the Schottky electrode 320a on the semiconductor stack layer 110. Between the vertical projection of the stacked layer 110 and the vertical projection of the source 220 on the semiconductor stacked layer 110 , and in the first direction D1 . The isolation structure 330 a is not located between the vertical projection of the Schottky electrode 320 a on the semiconductor stack 110 and the vertical projection of the drain 230 on the semiconductor stack 110 .

In some embodiments, the isolation structure 330a includes an insulating material. For example, a groove is formed in the semiconductor stack layer 110, and an insulating material is filled in the aforementioned concave layer to form the isolation structure 330a. For example, when forming the dielectric structure 120 , part of the insulating material fills the groove in the semiconductor stack 110 to form the isolation structure 330 a. In other embodiments, a doping process (for example, ion implantation process) is performed on the semiconductor stack layer 110 to form an isolation structure 330 a in the semiconductor stack layer 110 through which carriers cannot easily pass.

In this embodiment, the source 220, the gate 210, and the drain 230 are arranged in sequence along the first direction D1, and in this embodiment, the source 220, the Schottky electrode 320a, and the drain 230 are arranged along the first direction D1. One direction D1 is arranged.

In the forward conduction mode of the high electron mobility transistor device 10 , a positive voltage is applied to the drain 230 , and the current flows from the drain 230 through the semiconductor stack 110 below the gate 210 along the direction Id, and reaches the source 220 . At this time, the Schottky diode SBD1 is in reverse bias, and it is difficult for current to pass through the Schottky diode SBD1 , while the HEMT including the source 220 , the gate 210 and the drain 230 (such as the transistor in FIG. 1E ) operates normally.

In the reverse conduction mode of the high electron mobility transistor device 10, a negative voltage is applied to the drain 230 or a positive voltage is applied to the source 220. At this time, the Schottky diode SBD1 is in a forward bias, and the current can pass through the Schottky diode SBD1. Terbase diode SBD1. The current flows from the Schottky electrode 320 a through the semiconductor stack 110 below the Schottky electrode 320 a along the direction Ir, and reaches the drain 230 . Therefore, no matter the HEMT is in an on-state or an off-state, current can flow from the source 220 to the drain 230 through the Schottky electrode 320a.

Based on the above, the current in the reverse conduction mode can be channeled through the Schottky diode SBD1 , thereby increasing the efficiency of the high electron mobility transistor device 10 in the reverse conduction mode.

In this embodiment, the gate 210 and the Schottky electrode 320a are arranged along the second direction D2, and the second direction D2 is perpendicular to the first direction D1. Since the gate 210 and the Schottky electrode 320a are arranged along the second direction D2, the breakdown voltage of the HEMT including the source 220, the gate 210 and the drain 230 (such as a transistor in FIG. 1E ) is similar to that of the Schottky diode SBD1 The breakdown voltages are close to or equal to each other. In some embodiments, the distance V1 between the gate 210 and the drain 230 in the first direction D1 is equal to the distance V2 between the Schottky electrode 320a and the drain 230 in the first direction D1, thereby making it easier to control high electron mobility. rate the breakdown voltage of the transistor device 10.

In addition, since the gate 210 and the Schottky electrode 320a are arranged along the second direction D2, the field effect electric plate FP can not only shield the electric field of the HEMT, but also shield the electric field of the Schottky diode SBD1, thereby enabling the Schottky Diode SBD1 achieves reliability similar to HEMT. In some embodiments, the distance V3 between the side of the field effect electric plate FP close to the drain 230 and the gate 210 in the first direction D1 is equal to the distance V3 between the side of the field effect electric plate FP close to the drain 230 and the Schottky The distance V4 between the electrodes 320a in the first direction D1.

In addition, since the gate 210 and the Schottky electrode 320 a are in the second direction D2 , the width of the high electron mobility transistor device 10 in the first direction D1 can be reduced.

FIG. 2A is a schematic top view of a high electron mobility transistor device according to an embodiment of the present invention.

Fig. 2B is a schematic cross-sectional view along line a-a' of Fig. 2A. Fig. 2C is a schematic cross-sectional view along line b-b' of Fig. 2A.

Fig. 2D is a schematic cross-sectional view along line c-c' of Fig. 2A. 2E is a schematic circuit diagram of the high electron mobility transistor device of FIG. 2A.

It must be noted here that the embodiments in Figures 2A to 2E continue to use the element numbers and parts of the embodiments in Figures 1A to 1E, wherein the same or similar symbols are used to indicate the same or similar elements, and the same elements are omitted. A description of the technical content. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

Please refer to FIG. 2A to FIG. 2E. In this embodiment, there is a Schottky diode SBD2 between the source 220 and the gate 210 of the high electron mobility transistor device 20, and the Schottky diode SBD2 is electrically connected to the source 220. with gate 210.

The high electron mobility transistor device 20 includes a substrate 100 , a semiconductor stack 110 , a gate 210 , a source 220 , a drain 230 , an ohmic electrode 340 and a Schottky electrode 320 b.

The semiconductor stack 110 is disposed on the substrate 100 . The gate 210 is disposed on the semiconductor stack 110 . The source 220 and the drain 230 are respectively electrically connected to the semiconductor stack 110 .

The source 220 , the gate 210 and the drain 230 are disposed on the semiconductor stack 110 and arranged in sequence along the first direction D1 , and the HEMT includes the source 220 , the gate 210 and the drain 230 . In some embodiments, the source 220 has an ohmic contact with the semiconductor stack 110 , and the drain 230 has an ohmic contact with the semiconductor stack 110 , but the invention is not limited thereto. In other embodiments, the source 220 and the drain 230 may also be selected from materials that can form Schottky contacts with III-V compound semiconductors.

The ohmic electrode 340 is disposed on the semiconductor stack 110 and has an ohmic contact with the semiconductor stack 110 . The ohmic electrode 340 is electrically connected to the gate 210 through the conductive structure 350 . In some embodiments, the material of the conductive structure 350 includes metal. In some embodiments, the ohmic electrode 340, the source electrode 220 and the drain electrode 230 are selected from materials that can form an ohmic contact with the semiconductor stack layer 110, therefore, the ohmic electrode 340, the source electrode 220 and the drain electrode 230 can be formed together, This saves production costs.

In some embodiments, the distance V1 between the gate 210 and the drain 230 in the first direction D1 is equal to the distance V2a between the ohmic electrode 340 and the drain 230 in the first direction D1, but the invention is not limited thereto.

The Schottky electrode 320 b is disposed on the semiconductor stack 110 and has a Schottky contact with the semiconductor stack 110 . The Schottky electrode 320 b is electrically connected to the source 220 through the conductive structure 310 . In this embodiment, the conductive structure 310 extends along the second direction D2. The Schottky electrode 320b, the ohmic electrode 340 and the drain electrode 230 are sequentially arranged along the first direction D1.

In this embodiment, the ohmic electrode 340 and the gate electrode 210 are arranged along the second direction D2, and the source electrode 220 and the Schottky electrode 320b are arranged along the second direction D2. Accordingly, the width of the high electron mobility transistor device 20 in the first direction D1 is reduced.

In this embodiment, the Schottky electrode 320b and the semiconductor stacked layer 110 constitute a Schottky diode SBD2. One end of the Schottky diode SBD2 is electrically connected to the source 220 , and the other end of the Schottky diode SBD2 is electrically connected to the gate 210 through the ohmic electrode 340 and the conductive structure 350 , as shown in the schematic circuit diagram of FIG. 2E .

The field effect panel FP is electrically connected to the gate 210 . In some embodiments, the field effect plate FP includes conductive materials, such as metals, metal nitrides, metal oxides or other suitable materials. In some embodiments, the field effect plate FP, the conductive structure 310 and the drain 230 extend along the second direction D2 and are separated from each other. The field effect plate FP is located above the gate 210 and the ohmic electrode 340, and extends from above the gate 210 and the ohmic electrode 340 toward the drain 230 to cover part of the semiconductor stack 110 between the gate 210 and the drain 230 and a part of the semiconductor stack 110 between the ohmic electrode 340 and the drain 230 . In this embodiment, the field effect plate FP also covers part of the semiconductor stack layer 110 between the ohmic electrode 340 and the Schottky electrode 320b, thereby improving the reliability of the Schottky diode SBD2.

In some embodiments, the gate 210, the source 220, the drain 230, the conductive structure 310, the Schottky electrode 320b, the ohmic electrode 340, the conductive structure 350, and the field effect plate FP each include a single-layer or multi-layer structure, And distributed in the dielectric structure 120 or on the dielectric structure 120 . In this embodiment, a part of the dielectric structure 120 is selectively disposed between the field effect plate FP and the ohmic electrode 340 . For example, the dielectric structure 120 is sandwiched between the conductive structure 350 above the ohmic electrode 340 and the field effect plate FP.

In some embodiments, the distance V3 between the side of the field effect electric plate FP close to the drain 230 and the gate 210 in the first direction D1 is equal to the distance between the side of the field effect electric plate FP close to the drain and the ohmic electrode 340 The distance V4a between them in the first direction D1.

In this embodiment, the semiconductor stack layer 110 includes an isolation structure 330 b. The isolation structure 330 b extends downward from the top surface of the semiconductor stack 110 beyond the 2D electron gas.

The isolation structure 330 b is laterally located between the ohmic electrode 340 and the gate 210 , thereby preventing current from directly passing through the semiconductor stack 110 between the semiconductor stack 110 below the ohmic electrode 340 and the semiconductor stack 110 below the gate 210 . In other words, the isolation structure 330 b electrically isolates the semiconductor stack 110 under the ohmic electrode 340 from the semiconductor stack 110 under the gate 210 . In addition, the isolation structure 330 b is laterally located between the ohmic electrode 340 and the drain 230 , thereby preventing the Schottky diode SBD2 from being directly connected to the drain 230 . In other words, the isolation structure 330 b electrically isolates the semiconductor stack 110 under the ohmic electrode 340 from the semiconductor stack 110 under the drain 230 . In addition, the isolation structure 330b is laterally located between the Schottky electrode 320b and the source 220, thereby preventing current from directly passing between the semiconductor stack 110 below the Schottky electrode 320b and the semiconductor stack 110 below the source 220. The semiconductor stack layer 110 is transferred. In other words, the isolation structure 330 b electrically isolates the semiconductor stack 110 below the Schottky electrode 320 b from the semiconductor stack 110 below the source 220 .

In this embodiment, the isolation structure 330b is located between the vertical projection of the ohmic electrode 340 on the semiconductor stack layer 110 and the vertical projection of the gate 210 on the semiconductor stack layer 110, and the isolation structure 330b is located between the ohmic electrode 340 on the semiconductor stack layer 110 Between the vertical projection and the vertical projection of the drain 230 on the semiconductor stack 110 . In addition, in the second direction D2 , the isolation structure 330 b is located between the vertical projection of the Schottky electrode 320 b on the semiconductor stack 110 and the vertical projection of the source 220 on the semiconductor stack 110 . In some embodiments, the isolation structure 330 a is not located between the vertical projection of the Schottky electrode 320 b on the semiconductor stack 110 and the vertical projection of the ohmic electrode 340 on the semiconductor stack 110 .

In some embodiments, the isolation structure 330b includes an insulating material. For example, a groove is formed in the semiconductor stack layer 110, and an insulating material is filled in the aforementioned concave layer to form the isolation structure 330b. For example, when forming the dielectric structure 120 , part of the insulating material fills the groove in the semiconductor stack 110 to form the isolation structure 330 a. In other embodiments, a doping process (for example, ion implantation process) is performed on the semiconductor stack layer 110 to form an isolation structure 330 b in the semiconductor stack layer 110 through which carriers cannot easily pass.

In this embodiment, the anode of the Schottky diode SBD2 is electrically connected to the source 220, and the cathode is electrically connected to the gate 210, so that the effective discharge of static electricity can be realized, the electrostatic protection ability of the gate of the HEMT can be improved, and the electrostatic discharge can be reduced. result in component failure.

FIG. 3A is a schematic top view of a high electron mobility transistor device according to an embodiment of the present invention. Fig. 3B is a schematic cross-sectional view along line d-d' and e-e' in Fig. 3A. FIG. 3C is a schematic circuit diagram of the high electron mobility transistor device of FIG. 3A .

It must be noted here that the embodiment of FIG. 3A to FIG. 3C follows the component numbers and part of the content of the embodiment of FIG. 2A to FIG. A description of the technical content. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

Please refer to FIG. 3A to FIG. 3C , in this embodiment, a plurality of Schottky diodes SBD2 a , SBD2 b , and SBD2 c connected in series are included between the source 220 and the gate 210 of the high electron mobility transistor device 30 .

The ohmic electrodes 340 a , 340 b , and 340 c are disposed on the semiconductor stack 110 , and have ohmic contacts with the semiconductor stack 110 respectively. In this embodiment, the ohmic electrodes 340 b and 340 c are located between the first ohmic electrode 340 a and the gate 210 .

The Schottky electrodes 320ba , 320bb , and 320bc are disposed on the semiconductor stack 110 , and have Schottky contacts with the semiconductor stack 110 respectively.

In this embodiment, the source electrode 220, the Schottky electrodes 320ba, 320bb, and 320bc are arranged along the second direction D2, and the ohmic electrodes 340a, 340b, 340c and the gate 210 are arranged along the second direction D2, thereby reducing the high electron density. The width of the mobility transistor device 30 in the first direction D1.

In this embodiment, the gate 210 is electrically connected to the ohmic electrode 340 a through the conductive structure 350 (and other signal lines not shown in the figure). In some embodiments, the gate 210 is electrically connected to other gates (not shown) through the conductive structure 350 , and the plurality of gates are electrically connected to the ohmic electrode 340a. In other words, the ohmic electrode 340a can be electrically connected to the gates of multiple HEMTs, and the number of HEMTs can be adjusted according to requirements, which means that the present invention does not limit only one HEMT gate to be electrically connected to the ohmic electrode 340a.

The ohmic electrode 340a is electrically connected to the Schottky electrode 320ba and the semiconductor stack 110 to form a Schottky diode SBD2a. The Schottky electrode 320ba is electrically connected to the ohmic electrode 340b through the conductive structure 360a. The ohmic electrode 340b is electrically connected to the Schottky electrode 320bb and the semiconductor stack 110 to form a Schottky diode SBD2b. Schottky electrode 320bb is electrically connected to ohmic electrode 340c through conductive structure 360b. The ohmic electrode 340c is electrically connected to the Schottky electrode 320bc and the semiconductor stack 110 to form a Schottky diode SBD2c. The Schottky electrode 320bc is electrically connected to the source 220 through the conductive structure 310 .

In this embodiment, Schottky diodes SBD2a, SBD2b, SBD2c are connected in series. In this embodiment, three Schottky diodes SBD2 a , SBD2 b , and SBD2 c connected in series are included between the gate 210 and the source 220 , but the present invention is not limited thereto. Two or more Schottky diodes connected in series are included between the gate 210 and the source 220 . In other words, the number of Schottky diodes connected in series can be adjusted according to requirements. By connecting the Schottky diodes in series, the electrostatic discharge of the high electron mobility transistor device 30 can be better adjusted.

In this embodiment, the field effect plate FP overlaps the gate 210 and the ohmic electrodes 340a, 340b, 340c. The field effect plate FP overlaps the semiconductor stack 110 between the gate 210 and the drain 230 and the semiconductor stack 110 between the ohmic electrodes 340 a , 340 b , 340 c and the Schottky electrodes 320 ba , 320 bb , 320 bc. The field effect plate FP is electrically connected to the conductive structure 350 through the conductive hole C, but the invention is not limited thereto.

In this embodiment, the semiconductor stack layer 110 includes an isolation structure 330c. The isolation structure 330c extends downward from the top surface of the semiconductor stack 110 beyond the 2D electron gas.

The isolation structure 330c is laterally located between the ohmic electrodes 340a, 340b, 340c, thereby preventing current flow in the semiconductor stack 110 below the ohmic electrode 340a, the semiconductor stack 110 below the ohmic electrode 340b, and the semiconductor stack 110 below the ohmic electrode 340c. directly pass through the semiconductor stack layer 110 . In addition, the isolation structure 330c is laterally located between the Schottky electrodes 320ba, 320bb, 320bc, thereby preventing the current flow between the semiconductor stack layer 110 below the Schottky electrode 320ba, the semiconductor stack layer 110 below the Schottky electrode 320bb, and the Schottky electrode 320bb. The semiconductor stacked layers 110 below the tertiary electrodes 320bc are directly transmitted through the semiconductor stacked layers 110 . In other words, the isolation structure 330c electrically isolates the semiconductor stack layers 110 below the ohmic electrodes 340a, 340b, 340c from each other. In addition, the isolation structure 330c is laterally located between the Schottky electrode 320bc and the source 220, thereby preventing current from directly passing between the semiconductor stack 110 below the Schottky electrode 320bc and the semiconductor stack 110 below the source 220. The semiconductor stack layer 110 is transferred. In other words, the isolation structure 330 c electrically isolates the semiconductor stack 110 below the Schottky electrode 320 bc from the semiconductor stack 110 below the source 220 .

FIG. 4A is a schematic top view of a high electron mobility transistor device according to an embodiment of the present invention. FIG. 4B is a schematic circuit diagram of the high electron mobility transistor device of FIG. 4A .

It must be noted here that the embodiment of FIG. 4A and FIG. 4B follows the component numbers and parts of the embodiment of FIG. 1A to FIG. 1E and the embodiment of FIG. 2A to FIG. or similar elements, and descriptions of the same technical content are omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

4A and 4B, the high electron mobility transistor device 40 includes a substrate 100, a semiconductor stack 110, a gate 210, a source 220, a drain 230, a Schottky electrode 320a, a Schottky electrode 320b, and an ohmic electrode 340 .

The ohmic electrode 340 is disposed on the semiconductor stack 110 and has an ohmic contact with the semiconductor stack 110 . The ohmic electrode 340 is electrically connected to the gate 210 through the conductive structure 350 .

The Schottky electrodes 320 a , 320 b are disposed on the semiconductor stack 110 , and have Schottky contacts with the semiconductor stack 110 respectively. The Schottky electrodes 320 a , 320 b are electrically connected to the source 220 through the conductive structure 310 .

The Schottky electrode 320a and the semiconductor stacked layer 110 constitute a Schottky diode SBD1. The Schottky diode SBD1 is electrically connected to the source 220 and the drain 230 . The Schottky electrode 320b and the semiconductor stacked layer 110 constitute a Schottky diode SBD2. The Schottky diode SBD2 is electrically connected to the source 220 , and is electrically connected to the gate 210 through the ohmic electrode 340 and the conductive structure 350 , as shown in the schematic circuit diagram of FIG. 4B .

In this embodiment, the ohmic electrode 340 , the gate 210 and the Schottky electrode 320 a are arranged along the second direction D2 , and the source 220 and the Schottky electrode 320 b are arranged along the second direction D2 . Accordingly, the width of the high electron mobility transistor device 40 in the first direction D1 is reduced.

In this embodiment, the number of gates 210 between the ohmic electrode 340 and the Schottky electrode 320a can be adjusted according to actual needs. In other words, multiple HEMTs can share the Schottky diode SBD1 and the Schottky diode SBD2, but the present invention is not limited thereto.

In some embodiments, the distance V1 between the gate 210 and the drain 230 in the first direction D1 is equal to the distance V2 between the Schottky electrode 320a and the drain 230 in the first direction D1, thereby making it easier to control the strike of the device. wear voltage. In some embodiments, the distance V2a between the ohmic electrode 340 and the drain 230 in the first direction D1 is also equal to the distance V1 between the gate 210 and the drain 230 in the first direction D1, but the invention is not limited thereto.

In this embodiment, since the gate 210 and the Schottky electrode 320a are arranged along the second direction D2, the field effect electric plate FP can not only shield the electric field of the HEMT, but also shield the electric field of the Schottky diode SBD1, thereby Make Schottky diode SBD1 obtain reliability similar to HEMT. In addition, in this embodiment, the field effect plate FP is also overlapped on the semiconductor stack layer 110 between the ohmic electrode 340 and the Schottky electrode 320b, therefore, the reliability of the Schottky diode SBD2 can also be increased.

In some embodiments, the distance V3 between the side of the field effect electric plate FP close to the drain 230 and the gate 210 in the first direction D1 is equal to the distance V3 between the side of the field effect electric plate FP close to the drain 230 and the Schottky The distance V4 between the electrodes 320a in the first direction D1. In some embodiments, the distance V4a between the side of the field effect electric plate FP close to the drain and the ohmic electrode 340 in the first direction D1 is also equal to the distance V4a between the side of the field effect electric plate FP close to the drain 230 and the gate 210 The distance V3 between them in the first direction D1, but the present invention is not limited thereto.

In this embodiment, the semiconductor stack layer 110 includes an isolation structure 330 a. The isolation structure 330a is laterally located between the Schottky electrode 320a and the gate 210, thereby preventing current from directly passing through the semiconductor stack between the semiconductor stack 110 below the Schottky electrode 320a and the semiconductor stack 110 below the gate 210. Layer 110 delivery. In addition, the isolation structure 330a is laterally located between the Schottky electrode 320a and the source 220, so that the current can flow into the semiconductor stack layer 110 below the Schottky electrode 320a through the Schottky electrode 320a without being transferred from the Schottky electrode 320a. The semiconductor stacked layer 110 below the source electrode 220 flows directly through the semiconductor stacked layer 110 into the semiconductor stacked layer 110 below the Schottky electrode 320a.

In this embodiment, the semiconductor stack layer 110 further includes an isolation structure 330b. The isolation structure 330 b is laterally located between the ohmic electrode 340 and the gate 210 , thereby preventing current from directly passing through the semiconductor stack 110 between the semiconductor stack 110 below the ohmic electrode 340 and the semiconductor stack 110 below the gate 210 . In addition, the isolation structure 330 b is laterally located between the ohmic electrode 340 and the drain 230 , thereby preventing the Schottky diode SBD2 from being directly connected to the drain 230 . In addition, the isolation structure 330b is laterally located between the Schottky electrode 320b and the source 220, thereby preventing the current from flowing directly between the semiconductor stack 110 below the Schottky electrode 320b and the semiconductor stack 110 below the source 220. passed through the semiconductor stack layer 110 .

FIG. 5A is a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present invention. FIG. 5B is a schematic cross-sectional view of a Schottky diode according to an embodiment of the present invention.

It must be noted here that the embodiment in FIG. 5A and FIG. 5B continues to use the component numbers and parts of the embodiment in FIG. 1A to FIG. A description of the technical content. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

Please refer to FIG. 5A , in this embodiment, the source 220 and the drain 230 are respectively electrically connected to the semiconductor stack 110 . The source 220 and the drain 230 extend into the channel layer 106 and are electrically connected to the 2D electron gas. In one embodiment, the material of the source electrode 220 and the drain electrode 230 includes metal (such as Al, Ti, Ni, Au or alloys thereof), or other materials that can form Ohmic contact with III-V compound semiconductors. . In other words, the source 220 has an ohmic contact with the semiconductor stack 110 , and the drain 230 has an ohmic contact with the semiconductor stack 110 .

In some embodiments, at least one of the source 220 and the drain 230 includes a multi-layer structure. For example, the source electrode 220 includes a multi-layer structure, wherein the lowest layer in contact with the semiconductor stack layer 110 has an ohmic contact with the semiconductor stack layer 110, while other layers not in contact with the semiconductor stack layer 110 may include the aforementioned The bottom layer is a different material. Similarly, the drain 230 includes, for example, a multi-layer structure, wherein the lowermost layer in contact with the semiconductor stack layer 110 has an ohmic contact with the semiconductor stack layer 110, while other layers not in contact with the semiconductor stack layer 110 may include the aforementioned The bottom layer is a different material.

In this embodiment, the bottom surface 220B of the source electrode 220 and/or the bottom surface 230B of the drain electrode 230 are located at different levels from the bottom surface 320B of the Schottky electrode 320a, but the invention is not limited thereto.

FIG. 6 is a schematic cross-sectional view of a high electron mobility transistor device according to an embodiment of the present invention.

It must be noted here that the embodiment of FIG. 6 follows the component numbers and part of the content of the embodiment of FIG. 5A and FIG. illustrate. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

Please refer to FIG. 6 , in this embodiment, the Schottky electrode 320 a is directly connected to the source 220 . In other words, in this embodiment, the arrangement of the conductive structure 310 (please refer to FIG. 5B ) can be saved, thereby reducing the manufacturing cost.

To sum up, the present invention can reduce the efficiency loss of the reverse conduction mode and/or the element failure caused by electrostatic discharge by integrating the HEMT and the SBD.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (16)

1. A high electron mobility transistor device, characterized in that, comprising: Substrate; a semiconductor stack layer disposed on the substrate, wherein the semiconductor stack layer includes a first isolation structure; a gate disposed on the semiconductor stack; a source and a drain are respectively electrically connected to the semiconductor stack layer, and the source, the gate and the drain are arranged in sequence along a first direction; and a first Schottky electrode having a Schottky contact with the semiconductor stack layer and electrically connected to the source, wherein the gate and the first Schottky electrode are arranged along a second direction, Wherein the first direction and the second direction are parallel to the surface of the substrate, and the second direction is perpendicular to the first direction, wherein the first Schottky electrode and the semiconductor stack layer A first Schottky diode is formed, the first Schottky diode is electrically connected to the source and the drain, and the first isolation structure is laterally located between the first Schottky electrode and the gate between the electrodes and between the first Schottky electrode and the source. 2. The high electron mobility transistor device according to claim 1, wherein the first isolation structure connects the semiconductor stack layer under the first Schottky electrode and the semiconductor stack layer under the gate The semiconductor stack layer is electrically isolated, and the first isolation structure electrically isolates the semiconductor stack layer below the first Schottky electrode from the semiconductor stack layer below the source. 3. The high electron mobility transistor device according to claim 1, further comprising: The field effect electric plate is electrically connected to the gate and located above the gate and the first Schottky electrode. 4. The high electron mobility transistor device according to claim 1, wherein the distance between the gate and the drain in the first direction is equal to the distance between the first Schottky electrode and the drain. The distance between the drains in the first direction. 5. The high electron mobility transistor device according to claim 1, further comprising: A first ohmic electrode having an ohmic contact with the semiconductor stack layer and electrically connected to the gate, wherein the gate, the first Schottky electrode and the first ohmic electrode are along the aligned in a second direction; and A second Schottky electrode having a Schottky contact with the semiconductor stack layer, wherein the source and the second Schottky electrode are arranged along the second direction, and wherein the source and the second Schottky electrode are arranged along the second direction, and wherein the source and the second Schottky electrode are arranged in the second direction, A second Schottky diode formed by the second Schottky electrode and the semiconductor stack layer is included between the gates. 6. The high electron mobility transistor device according to claim 5, wherein the semiconductor stack layer further comprises a second isolation structure, and the second isolation structure is laterally located between the first ohmic electrode and Between the gate and between the first ohmic electrode and the drain, and wherein the second isolation structure is laterally located between the second Schottky electrode and the source, wherein the The second isolation structure electrically isolates the semiconductor stack layer below the first ohmic electrode from the semiconductor stack layer below the gate, and the second isolation structure electrically isolates the semiconductor stack layer below the first ohmic electrode. The semiconductor stack is electrically isolated from the semiconductor stack below the drain, and wherein the second isolation structure separates the semiconductor stack below the second Schottky electrode from the semiconductor stack below the source The semiconductor stack layers are electrically isolated. 7. The high electron mobility transistor device according to claim 5, characterized in that: The second Schottky diode is electrically connected to the source and the gate. 8. The high electron mobility transistor device according to claim 1, wherein an ohmic contact is provided between the source and the semiconductor stack, and an ohmic contact is provided between the drain and the semiconductor stack. ohmic contact. 9. A high electron mobility transistor device, comprising: Substrate; a semiconductor stack layer disposed on the substrate, wherein the semiconductor stack layer includes a first isolation structure; a gate disposed on the semiconductor stack; a source and a drain are respectively electrically connected to the semiconductor stack layer, and the source, the gate and the drain are arranged in sequence along a first direction; A first ohmic electrode, having an ohmic contact with the semiconductor stack layer, and electrically connected to the gate, wherein the first ohmic electrode and the gate are arranged along a second direction, wherein the first direction The second direction is parallel to the surface of the substrate, and the second direction is perpendicular to the first direction, wherein the first isolation structure is laterally located between the first ohmic electrode and the gate between and between the first ohmic electrode and the drain; and The first Schottky electrode has a Schottky contact with the semiconductor stack layer, wherein the source and the first Schottky electrode are arranged along a second direction, and wherein the source and the A first Schottky diode formed by the first Schottky electrode and the semiconductor stack layer is included between the gates, and the first isolation structure is laterally located between the first Schottky electrode and the between the sources. 10. The high electron mobility transistor device according to claim 9, wherein the first isolation structure separates the semiconductor stack layer under the first ohmic electrode from the semiconductor stack layer under the gate. The stacked layers are electrically isolated, the first isolation structure electrically isolates the semiconductor stacked layer below the first ohmic electrode from the semiconductor stacked layer below the drain, and the first isolation structure electrically isolates the semiconductor stacked layer below the drain. The semiconductor stack layer below the first Schottky electrode is electrically isolated from the semiconductor stack layer below the source. 11. The high electron mobility transistor device of claim 9, wherein the first Schottky diode is electrically connected to the source and the gate. 12. The high electron mobility transistor device according to claim 9, wherein there is an ohmic contact between the source and the semiconductor stack, and an ohmic contact between the drain and the semiconductor stack. ohmic contact. 13. The high electron mobility transistor device according to claim 9, further comprising: The field effect electric plate is electrically connected to the grid and located above the grid and the first ohmic electrode. 14. The high electron mobility transistor device according to claim 9, further comprising: a second ohmic electrode having an ohmic contact with the semiconductor stack layer and electrically connected to the first Schottky electrode; and The second Schottky electrode has a Schottky contact with the semiconductor stack layer, wherein the second Schottky electrode and the semiconductor stack layer form a second Schottky diode, and the first Schottky The base diode and the second Schottky diode are connected in series between the source and the gate. 15. The high electron mobility transistor device of claim 14, wherein the second ohmic electrode is located between the first ohmic electrode and the gate. 16. The high electron mobility transistor device according to claim 14, wherein the source, the first Schottky electrode, and the second Schottky electrode are arranged along the second direction, And the first ohmic electrode, the second ohmic electrode and the grid are arranged along the second direction.

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