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TWI732921B - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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TWI732921B
TWI732921B TW106127072A TW106127072A TWI732921B TW I732921 B TWI732921 B TW I732921B TW 106127072 A TW106127072 A TW 106127072A TW 106127072 A TW106127072 A TW 106127072A TW I732921 B TWI732921 B TW I732921B
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sealing body
protective film
semiconductor
manufacturing
layer
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TW201826405A (en
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篠田智則
根本拓
中西勇人
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日商琳得科股份有限公司
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Abstract

一種半導體裝置的製造方法，其特徵為包含： 　　將元件背面(W2)朝向黏著劑層，使具有電路面(W1)及前述元件背面(W2)之複數的半導體元件貼著於具有前述黏著劑層的支撐基板(10)的前述黏著劑層之工程； 　　將被貼著於支撐基板(10)的前述半導體元件密封，而形成密封體(3)之工程； 　　將外部端子電極形成於密封體(3)，而使被貼著於支撐基板(10)的前述半導體元件與前述外部端子電極電性連接之工程； 　　在使前述半導體元件與前述外部端子電極電性連接之後，從密封體(3)剝離支撐基板(10)，而使前述半導體元件的元件背面(W2)露出之工程； 　　在露出的前述半導體元件的元件背面(W2)形成硬化性的保護膜形成層之工程；及 　　使前述保護膜形成層硬化而形成保護膜之工程。A method for manufacturing a semiconductor device, which is characterized by comprising: 　 　 turn the back surface of the device (W2) toward an adhesive layer, and stick a plurality of semiconductor devices having the circuit surface (W1) and the back surface of the device (W2) on the adhesive layer The process of forming the aforementioned adhesive layer of the supporting substrate (10); 　　 sealing the aforementioned semiconductor element attached to the supporting substrate (10) to form a sealing body (3); 　　 forming external terminal electrodes on the sealing body (3) ) To electrically connect the semiconductor element attached to the support substrate (10) with the external terminal electrode; 　　 after electrically connecting the semiconductor element with the external terminal electrode, peel off from the sealing body (3) The process of supporting the substrate (10) to expose the device back surface (W2) of the semiconductor element; 　　 forming a curable protective film forming layer on the exposed device back surface (W2) of the semiconductor element; and forming the protective film The process of hardening the layer to form a protective film.

Description

半導體裝置的製造方法Manufacturing method of semiconductor device

本發明是有關半導體裝置的製造方法。The present invention relates to a method of manufacturing a semiconductor device.

近年來，電子機器的小型化、輕量化、及高機能化進展。被搭載於電子機器的半導體裝置也被要求小型化、薄型化、及高密度化。半導體晶片(有時只稱晶片)是有被安裝於接近其大小的封裝的情形。如此的封裝亦有被稱為晶片規模封裝(Chip Scale Package；CSP)的情形。作為製造CSP的製程之一，可舉晶圓水準封裝(Wafer Level Package；WLP)。在WLP中是在藉由切割來使封裝小片化之前，在晶片電路形成面形成外部電極等，最後切割包含晶片的封裝晶圓，而使小片化。作為WLP是可舉扇入(Fan-In)型及扇出(Fan-Out)型。在扇出型的WLP(以下有時簡稱為FO-WLP)中，以能成為比晶片大小更大的領域之方式，使用密封構件來覆蓋半導體晶片，而形成半導體晶片密封體，不僅半導體晶片的電路面，在密封構件的表面領域中也形成再配線層或外部電極。 　　例如，在文獻1(日本特開2012-62372號公報)中記載有使用晶片暫時固定用的黏著膠帶的WLP等的製造方法。在文獻1的方法中，藉由將晶片的電路面朝向基板上的黏著膠帶的黏著劑層貼著的方式(有時稱為面朝下方式)來貼著晶片。 　　在文獻1的方法中，在樹脂密封晶片之後，從藉由樹脂來密封晶片而成的層(有時稱為晶片密封層)剝離黏著膠帶及基板，在露出的電路面形成電極。如此，在文獻1的方法中，由於在晶片電路面形成電極時，晶片密封層是未藉由基板來支撐，因此藉由伴隨密封樹脂的硬化之應力，恐有發生晶片密封層的彎曲之虞。一旦發生晶片密封層的彎曲，則難以在晶片電路面形成再配線層及電極。In recent years, the miniaturization, weight reduction, and high performance of electronic equipment have progressed. Semiconductor devices mounted on electronic devices are also required to be downsized, thinner, and high-density. A semiconductor chip (sometimes just called a chip) is sometimes mounted in a package close to its size. Such a package is also called a chip scale package (CSP). As one of the manufacturing processes of CSP, wafer level packaging (Wafer Level Package; WLP) can be cited. In WLP, before the package is diced by dicing, external electrodes and the like are formed on the circuit formation surface of the chip, and finally the packaged wafer including the chip is diced to make the package into small pieces. The WLP can be a fan-in (Fan-In) type and a fan-out (Fan-Out) type. In fan-out WLP (hereinafter sometimes abbreviated as FO-WLP), a sealing member is used to cover the semiconductor wafer in a way that can become a larger area than the wafer size, and the semiconductor wafer sealing body is formed, not only the semiconductor wafer On the circuit surface, a rewiring layer or external electrode is also formed in the surface area of the sealing member. "For example, Document 1 (Japanese Patent Application Laid-Open No. 2012-62372) describes a manufacturing method such as WLP using an adhesive tape for temporary fixation of a wafer. In the method of Document 1, the chip is attached by a method in which the circuit surface of the chip faces the adhesive layer of the adhesive tape on the substrate (sometimes referred to as the face-down method). "In the method of Document 1, after resin sealing a wafer, the adhesive tape and a board|substrate are peeled from the layer (sometimes called a wafer sealing layer) which seals a wafer with resin, and an electrode is formed on the exposed circuit surface. In this way, in the method of Document 1, since the chip sealing layer is not supported by the substrate when electrodes are formed on the circuit surface of the chip, there is a risk that the chip sealing layer may be bent due to the stress accompanying the curing of the sealing resin. . Once the wafer sealing layer is bent, it is difficult to form a rewiring layer and electrodes on the circuit surface of the wafer.

本發明的目的是在於提供一種可抑制密封體的彎曲之半導體裝置的製造方法。 　　本發明之一形態的半導體裝置的製造方法的特徵是包含： 　　將元件背面朝向黏著劑層，使具有電路面及與前述電路面相反側的前述元件背面之複數的半導體元件貼著於具有前述黏著劑層的支撐基板的前述黏著劑層之工程； 　　將被貼著於前述支撐基板的前述半導體元件密封，而形成密封體之工程； 　　將外部端子電極形成於前述密封體，而使被貼著於前述支撐基板的前述半導體元件與前述外部端子電極電性連接之工程； 　　在使前述半導體元件與前述外部端子電極電性連接之後，從前述密封體剝離前述支撐基板，而使前述半導體元件的前述元件背面露出之工程； 　　在露出的前述半導體元件的前述元件背面形成硬化性的保護膜形成層之工程； 　　使前述保護膜形成層硬化而形成保護膜之工程。 　　在本發明之一形態的半導體裝置的製造方法中，較理想是更包含： 　　在形成前述保護膜之後，將前述密封體貼著於第一支撐薄板之工程；及 　　使被貼著於前述第一支撐薄板的前述密封體小片化之工程。 　　在本發明之一形態的半導體裝置的製造方法中，較理想是更包含： 　　使前述半導體元件與前述外部端子電極電性連接之後，從前述密封體剝離前述支撐基板之前，將前述密封體貼著於第二支撐薄板之工程， 　　將前述密封體的前述外部端子電極朝前述第二支撐薄板貼著。 　　在本發明之一形態的半導體裝置的製造方法中，較理想是將前述密封體貼著於前述第二支撐薄板，從前述密封體剝離前述支撐基板之後，在露出的前述半導體元件的前述元件背面形成前述保護膜形成層。 　　在本發明之一形態的半導體裝置的製造方法中，較理想是更包含： 　　在形成前述保護膜之後，使被貼著於前述第二支撐薄板的前述密封體小片化之工程。 　　在本發明之一形態的半導體裝置的製造方法中，較理想是更包含： 　　在形成前述保護膜之後，從前述第二支撐薄板剝離前述密封體，而貼著於第三支撐薄板之工程； 　　使被貼著於前述第三支撐薄板的前述密封體小片化之工程。 　　若根據本發明之一形態，則可提供一種能夠抑制密封體的彎曲之半導體裝置的製造方法。The object of the present invention is to provide a method of manufacturing a semiconductor device that can suppress the bending of the sealing body. The method of manufacturing a semiconductor device according to one aspect of the present invention is characterized by: 　 　 turn the back surface of the element toward the adhesive layer, and stick a plurality of semiconductor elements having a circuit surface and the back surface of the element opposite to the circuit surface on the adhesive The process of forming a sealing body by sealing the semiconductor element attached to the supporting substrate; 　　 forming the external terminal electrode on the sealing body so as to be attached to The process of electrically connecting the semiconductor element of the supporting substrate to the external terminal electrode; 　　 after electrically connecting the semiconductor element to the external terminal electrode, peeling the supporting substrate from the sealing body to make the element of the semiconductor element The process of exposing the back surface; 　　 the process of forming a curable protective film forming layer on the back surface of the exposed semiconductor element; 　　 the process of curing the protective film forming layer to form a protective film. In the method of manufacturing a semiconductor device according to one aspect of the present invention, it is desirable to further include: 　　 after forming the protective film, attaching the sealing body to the first support sheet; and attaching to the first support The process of making the aforementioned sealing body of the thin plate into small pieces. In the method of manufacturing a semiconductor device according to one aspect of the present invention, it is desirable to further include: 　　 after electrically connecting the semiconductor element to the external terminal electrode, and before peeling off the supporting substrate from the sealing body, attaching the sealing body to In the process of the second supporting sheet, the external terminal electrode of the sealing body is attached to the second supporting sheet. In the method of manufacturing a semiconductor device according to one aspect of the present invention, it is preferable that the sealing body is attached to the second supporting sheet, and the supporting substrate is peeled from the sealing body, and then formed on the exposed back surface of the semiconductor device. The aforementioned protective film forms a layer.　　The method of manufacturing a semiconductor device according to one aspect of the present invention preferably further includes: 　　, after forming the protective film, a process of slicing the sealing body attached to the second supporting sheet. In the method of manufacturing a semiconductor device according to one aspect of the present invention, it is desirable to further include: 　　 after forming the protective film, peeling off the sealing body from the second supporting sheet and attaching it to the third supporting sheet; 　　using The process of making the sealing body attached to the third supporting sheet into small pieces. "According to one aspect of the present invention, it is possible to provide a method of manufacturing a semiconductor device capable of suppressing bending of the sealing body.

[第一實施形態] 　　以下，說明有關本實施形態的半導體裝置的製造方法。 　　本實施形態的半導體裝置的製造方法是包含： 　　將元件背面朝向黏著劑層，使具有電路面及與前述電路面相反側的前述元件背面之複數的半導體元件貼著於具有前述黏著劑層的支撐基板的前述黏著劑層之工程； 　　將被貼著於前述支撐基板的前述半導體元件密封，而形成密封體之工程； 　　將外部端子電極形成於前述密封體，而使被貼著於前述支撐基板的前述半導體元件與前述外部端子電極電性連接之工程； 　　在使前述半導體元件與前述外部端子電極電性連接之後，從前述密封體剝離前述支撐基板，而使前述半導體元件的前述元件背面露出之工程； 　　在露出的前述半導體元件的前述元件背面形成硬化性的保護膜形成層之工程； 　　使前述保護膜形成層硬化而形成保護膜之工程； 　　在形成前述保護膜之後，將前述密封體貼著於第一支撐薄板之工程；及 　　使被貼著於前述第一支撐薄板的前述密封體小片化之工程。 　　圖1(圖1A、圖1B及圖1C)、圖2(圖2A、圖2B、圖2C及圖2D)及圖3(圖3A及圖3B)是表示本實施形態的半導體裝置的製造方法之一例的圖。 (半導體晶片貼著工程) 　　在圖1A及圖1B是表示說明使作為半導體元件的半導體晶片CP貼著於具有黏著劑層的支撐基板10的工程(有時稱為半導體晶片貼著工程)的剖面概略圖。另外，在圖1A是顯示有1個半導體晶片CP，但在本實施形態是如圖1B所示般使複數的半導體晶片CP貼著於黏著劑層。使半導體晶片CP貼著時，亦可使1個1個貼著，或使複數的半導體晶片CP同時貼著。 　　在本實施形態中，半導體晶片CP會被貼著於兩面黏著薄板20所具備的黏著劑層，該兩面黏著薄板20是被貼著於支撐基板10。 ･兩面黏著薄板 　　在圖4是表示兩面黏著薄板20的剖面概略圖。 　　兩面黏著薄板20是具有基材21、第一黏著劑層22及第二黏著劑層23。基材21是具有第一基材面211及與第一基材面211相反側的第二基材面212。 　　第一黏著劑層22是形成於第一基材面211。 　　第二黏著劑層23是形成於第二基材面212。 　　在本實施形態中，半導體晶片CP會被貼著於第一黏著劑層22，第二黏著劑層23會被貼著於支撐基板10。 　　如圖1所示般，在本實施形態所使用的半導體晶片CP是具有：設有連接端子W3的電路面W1，及與電路面W1相反側的元件背面W2。在本實施形態中，使元件背面W2貼著於第一黏著劑層22。如此，將電路面W1朝上來使貼著於第一黏著劑層22的方式，有時稱為面朝上方式。 　　第一黏著劑層22是含有黏著劑。在第一黏著劑層22中所含的黏著劑並未特別加以限定，可將各種種類的黏著劑適用於第一黏著劑層22。作為在第一黏著劑層22中所含的黏著劑，例如可舉由橡膠系、丙烯酸系、矽酮系、聚酯系、及聚氨酯系等所成的群來選擇的黏著劑。另外，黏著劑的種類是考慮用途及所被貼著的被著體的種類等來選擇。在第一黏著劑層22調配有能量線重合性化合物時，從支撐基板10側照射能量線至第一黏著劑層22，使能量線重合性化合物硬化。一旦使能量線重合性化合物硬化，則第一黏著劑層22的凝集力變高，可使第一黏著劑層22與半導體晶片CP之間的黏著力，及第一黏著劑層22與密封構件之間的黏著力降低或消失。例如可舉紫外線(UV)及電子線(EB)等作為能量線，較理想是紫外線。 　　第一黏著劑層22是亦可含有藉由加熱來發泡的發泡劑。此情況，藉由加熱來使發泡劑發泡，可使第一黏著劑層22與半導體晶片CP之間的黏著力，及第一黏著劑層22與密封構件之間的黏著力降低或消失。 　　第二黏著劑層23也含有黏著劑。在第二黏著劑層23中所含的黏著劑並未特別加以限定，只要是可固定支撐基板10與兩面黏著薄板20的材質即可。在第二黏著劑層23中所含的黏著劑是可因應所需從支撐基板10剝離兩面黏著薄板20之類的黏著劑為理想。 ･支撐基板 　　支撐基板10是用以支撐半導體晶片CP及密封體的基板。支撐基板10並無特別加以限定，只要是以能支撐半導體晶片CP及密封體的材質所形成即可。支撐基板10是以硬質材料所形成為理想。在本實施形態中，支撐基板10是玻璃製為理想。又，支撐基板10是硬質塑料薄膜製為理想。 (密封工程) 　　在圖1C是表示說明密封複數的半導體晶片CP的工程(有時稱為密封工程)的剖面概略圖。 　　使用密封構件30來密封複數的半導體晶片CP的方法並無特別加以限定。在本實施形態中，以半導體晶片CP的電路面W1側不會被密封構件30覆蓋的方式，使用密封構件30來密封，藉此形成密封體3。在複數的半導體晶片CP之間也充填有密封構件30。如圖1C所示般，在密封體3的表面中，半導體晶片CP的電路面W1及連接端子W3會露出。 　　密封構件30的材質是樹脂製為理想，例如可舉環氧樹脂等。在作為密封構件30使用的環氧樹脂中，例如亦可含有苯酚樹脂、彈性體、無機充填材及硬化促進劑等。例如，可使用液狀的密封樹脂來以半導體晶片CP的電路面W1側不會被密封構件30覆蓋的方式密封。 　　亦可在密封工程與其次的工程之間實施更使密封構件30硬化的工程(有時稱為追加的硬化工程)。在此工程中，可舉加熱密封樹脂層來使硬化促進的方法為例。另外，亦可不實施追加的硬化工程，藉由密封工程的加熱來使密封構件30充分地硬化。 (再配線層形成工程) 　　在圖2A是表示說明形成與半導體晶片CP電性連接的再配線層4的工程(有時稱為再配線層形成工程)的剖面概略圖。 　　在本實施形態中，使再配線層4與露出於密封體3的表面的連接端子W3電性連接。在本實施形態中是將再配線層4形成於電路面W1及密封體3的面之上。形成再配線層4的方法是可採用以往周知的方法。 　　再配線層4是具有用以使外部端子電極連接的外部電極焊墊41。在本實施形態中，複數的外部電極焊墊41會被形成於再配線層4的表面側。 (外部端子電極連接工程) 　　在圖2B是表示說明使外部端子電極5電性連接至再配線層4的工程(有時稱為外部端子電極連接工程)的剖面概略圖。藉由此外部端子電極連接工程，半導體晶片CP與外部端子電極5會被電性連接。 　　本實施形態是在外部電極焊墊41載置焊錫球等的外部端子電極5，藉由焊錫接合等來使外部端子電極5與外部電極焊墊41電性連接。焊錫球的材質並未特別加以限定。焊錫球的材質是例如可舉含鉛焊錫及無鉛焊錫等。 (支撐基板剝離工程) 　　在圖2C是表示說明從密封體3剝離支撐基板10而使半導體晶片CP的元件背面W2露出的工程(有時稱為支撐基板剝離工程)的剖面概略圖。 　　從密封體3剝離支撐基板10的方法並未特別加以限定。作為支撐基板剝離工程的方法是可舉在將支撐基板10從兩面黏著薄板20剝離之後，從密封體3剝離兩面黏著薄板20的方法。又，作為支撐基板剝離工程的方法是可舉將支撐基板10及兩面黏著薄板20設為一體來從密封體3剝離的方法。 　　在第一黏著劑層22中調配有能量線重合性化合物時，從支撐基板10側照射能量線至第一黏著劑層22，使能量線重合性化合物硬化。一旦使能量線重合性化合物硬化，則第一黏著劑層22的凝集力變高，可使第一黏著劑層22與密封體3之間的黏著力降低或消失。例如可舉紫外線(UV)及電子線(EB)等作為能量線，較理想是紫外線。使第一黏著劑層22與密封體3之間的黏著力降低或消失的方法是不限於能量線照射。作為使此黏著力降低的方法或消失的方法是例如可舉藉由加熱的方法、藉由加熱及能量線照射的方法、以及藉由冷卻的方法。 (保護膜形成層形成工程) 　　在圖2D是表示說明在露出的半導體晶片CP的元件背面W2形成硬化性的保護膜形成層60的工程(有時稱為保護膜形成層形成工程)的剖面概略圖。本實施形態是在密封體3的背面(與形成有再配線層4等的面相反側的面)側形成保護膜形成層60，藉此覆蓋元件背面W2。 　　作為本實施形態的保護膜形成層60是例如可使用熱硬化性及能量線硬化性的任一方的保護膜形成層。本實施形態的保護膜形成層60是使用含有從外部接受能量而硬化的硬化性的黏著劑組成物之材料來形成為理想。將含有該硬化性的黏著劑組成物之黏著薄板貼附於密封體3的背面，形成保護膜形成層60，而來覆蓋元件背面W2更為理想。 　　作為從外部供給的能量是例如可舉紫外線、電子線及熱等。保護膜形成層60是含有紫外線硬化型黏著劑及熱硬化型黏著劑的至少任一種為理想。保護膜形成層60是含有熱硬化型黏著劑的熱硬化性的層也為理想，含有紫外線硬化型黏著劑的紫外線硬化性的層也為理想。 　　形成保護膜形成層60之後，實施使保護膜形成層60硬化而形成保護膜60A(參照圖3A)的工程(有時稱為保護膜形成工程)。 (第一支撐薄板貼著工程) 　　在圖3A是表示說明使保護膜形成層60硬化而形成保護膜60A之後，在貼著有環框RF的第一支撐薄板70貼著密封體3的工程(有時稱為第一支撐薄板貼著工程)的剖面概略圖。 　　本實施形態的第一支撐薄板70是被使用在半導體裝置的製造工程之切割薄板為理想。作為切割薄板的第一支撐薄板70是具有基材薄膜及黏著劑層為理想。將保護膜60A朝向第一支撐薄板70的黏著劑層，而把密封體3貼著於第一支撐薄板70。此情況，在第一支撐薄板70的黏著劑層之上載置環框RF，輕輕推壓環框RF，將環框RF及第一支撐薄板70固定。然後，將在環框RF的環形狀的內側露出的黏著劑層推到密封體3的保護膜60A上，而把密封體3固定於第一支撐薄板70。 (小片化工程) 　　在圖3B是表示使被貼著於第一支撐薄板70的密封體3小片化的工程(有時稱為小片化工程)的剖面概略圖。 　　在本實施形態中，使密封體3以半導體晶片CP單位來小片化。使密封體3小片化的方法是未特別加以限定。作為小片化的方法是例如可舉使用切割鋸等的切斷手段來小片化的方法、及雷射照射法等。 　　藉由使密封體3小片化，作為半導體裝置的半導體封裝1會被製造。 　　本實施形態的半導體裝置的製造方法是包含將半導體封裝1安裝於印刷配線基板等的工程(有時稱為安裝工程)也為理想。半導體封裝1是在元件背面W2維持附有保護膜60A的情形下從第一支撐薄板70拾取。 ･實施形態的效果 　　若根據本實施形態，則由於在密封工程中，藉由支撐基板10來支撐半導體晶片CP，因此可抑制以密封構件30來密封半導體晶片CP時的彎曲。 　　若根據本實施形態，則可在維持以支撐基板10來支撐密封體3的情形下，實施再配線層形成工程及外部端子電極連接工程。一旦密封體彎曲，則密封體的表面彎曲，難以形成再配線層及外部端子電極，但由於密封體3的彎曲會被抑制，因此對於密封體3中的複數的半導體晶片CP可精度佳形成再配線層4及外部端子電極5。 　　又，由於密封體3是以支撐基板10所支撐，因此密封體3的操縱(handling)性會提升。特別是當半導體晶片CP的厚度及密封體3的厚度薄時，本實施形態的半導體元件的製造方法有效。 [第二實施形態] 　　其次，說明有關本發明的第二實施形態。 　　本實施形態的半導體裝置的製造方法是包含： 　　將元件背面朝向黏著劑層，使具有電路面及與前述電路面相反側的前述元件背面之複數的半導體元件貼著於具有前述黏著劑層的支撐基板的前述黏著劑層之工程； 　　將被貼著於前述支撐基板的前述半導體元件密封，而形成密封體之工程； 　　將外部端子電極形成於前述密封體，而使被貼著於前述支撐基板的前述半導體元件與前述外部端子電極電性連接之工程； 　　在使前述半導體元件與前述外部端子電極電性連接之後，將前述密封體貼著於前述第二支撐薄板之工程； 　　在將前述密封體貼著於前述第二支撐薄板之後，從前述密封體剝離前述支撐基板，而使前述半導體元件的前述元件背面露出之工程； 　　在露出的前述半導體元件的前述元件背面形成硬化性的保護膜形成層之工程； 　　使前述保護膜形成層硬化而形成保護膜之工程；及 　　使被貼著於前述第二支撐薄板的前述密封體小片化之工程。 　　前述密封體是使前述外部端子電極朝向第二支撐薄板來貼著於第二支撐薄板。 　　在本實施形態的半導體裝置的製造方法中，與從第一實施形態的半導體晶片貼著工程到外部端子電極連接工程為止同樣的工程會被實施。 　　本實施形態的半導體裝置的製造方法是主要外部端子電極連接工程的後的工程會與第一實施形態不同。第二實施形態是在其他的點與第一實施形態同樣，因此省略說明或簡略化。 　　圖5(圖5A、圖5B、圖5C及圖5D)是表示本實施形態的半導體裝置的製造方法之一例的圖。 (第二支撐薄板貼著工程) 　　在圖5A是表示說明使外部端子電極5電性連接至半導體晶片CP之後，從密封體3剝離支撐基板10之前，將密封體3貼著於第二支撐薄板71的工程(有時稱為第二支撐薄板貼著工程)的剖面概略圖。 　　在第二支撐薄板貼著工程中，將以支撐基板10所支撐的狀態的密封體3貼著於第二支撐薄板71。密封體3是將外部端子電極5朝向第二支撐薄板71而貼著。在本實施形態中也是第二支撐薄板71具有基材薄膜及黏著劑層為理想。在本實施形態中也是使密封體3支撐於貼著有環框RF的第二支撐薄板71為理想。又，第二支撐薄板71是被使用在半導體裝置的製造工程的切割薄板為理想。 (支撐基板剝離工程) 　　在圖5B是表示說明將密封體3貼著於第二支撐薄板71之後，從密封體3剝離支撐基板10而使半導體晶片CP的元件背面W2露出的工程(支撐基板剝離工程)的剖面概略圖。 　　在本實施形態中也是從密封體3剝離支撐基板10的方法未被特別加以限定。例如，可採用在第一實施形態說明的方法等。作為本實施形態的支撐基板剝離工程的方法是可舉在將支撐基板10從兩面黏著薄板20剝離之後，從密封體3剝離兩面黏著薄板20的方法。並且，作為本實施形態的支撐基板剝離工程的方法是可舉將支撐基板10及兩面黏著薄板20設為一體來從密封體3剝離的方法。 (保護膜形成層形成工程) 　　在圖5C是表示說明在露出的半導體晶片CP的元件背面W2形成硬化性的保護膜形成層60的工程(保護膜形成層形成工程)的剖面概略圖。 　　在本實施形態中是在被第二支撐薄板71支撐的密封體3形成保護膜形成層60。藉由在密封體3的背面(與形成有再配線層4等的面相反側的面)側形成保護膜形成層60，來覆蓋元件背面W2。 　　本實施形態的保護膜形成層60的形成方法是與第一實施形態的保護膜形成層60的情況同樣。當第二支撐薄板71為具備耐熱性時，因為可抑制熱硬化時的殘留應力的發生及殘膠等，所以保護膜形成層60是含有熱硬化型黏著劑的熱硬化性的層為理想。保護膜形成層60是含有紫外線硬化型黏著劑的紫外線硬化性的層為理想。 　　在本實施形態中也是實施使被第二支撐薄板71支撐的密封體3的保護膜形成層60硬化而形成保護膜60A(參照圖5D)的工程(保護膜形成工程)。使保護膜形成層60硬化的方法是與第一實施形態同樣。 (小片化工程) 　　在圖5D是表示說明被貼著於第二支撐薄板71的密封體3小片化的工程(小片化工程)的剖面概略圖。 　　在本實施形態中也與第一實施形態同樣地使密封體3小片化。藉由使密封體3小片化，作為半導體裝置的半導體封裝1會被製造。 　　本實施形態的半導體裝置的製造方法是包含將半導體封裝1安裝於印刷配線基板等的工程(有時稱為安裝工程)也為理想。半導體封裝1是在元件背面W2維持附有保護膜60A的情形下從第二支撐薄板71拾取。 ･實施形態的效果 　　若根據本實施形態，則可取得與第一實施形態同樣的效果。 　　而且，若根據本實施形態，則由於支撐基板剝離工程是可對於被第二支撐薄板71支撐的密封體3實施，因此可容易從密封體3剝離支撐基板10。 　　而且，若根據本實施形態，則由於剝離支撐基板10後的密封體3是被第二支撐薄板71支撐，因此容易實施保護膜形成層形成工程。 　　當第二支撐薄板71為切割薄板時，從支撐基板剝離工程到小片化工程，由於可在維持以第二支撐薄板71來支撐密封體3的情形下實施，因此可使半導體裝置的製造工程簡略化。 [第三實施形態] 　　其次，說明有關本發明的第三實施形態。 　　本實施形態的半導體裝置的製造方法是包含： 　　將元件背面朝向黏著劑層，使具有電路面及與前述電路面相反側的前述元件背面之複數的半導體元件貼著於具有前述黏著劑層的支撐基板的前述黏著劑層之工程； 　　將被貼著於前述支撐基板的前述半導體元件密封，而形成密封體之工程； 　　將外部端子電極形成於前述密封體，而使被貼著於前述支撐基板的前述半導體元件與前述外部端子電極電性連接之工程； 　　在使前述半導體元件與前述外部端子電極電性連接之後，將前述密封體貼著於前述第二支撐薄板之工程； 　　在將前述密封體貼著於前述第二支撐薄板之後，從前述密封體剝離前述支撐基板，而使前述半導體元件的前述元件背面露出之工程； 　　在露出的前述半導體元件的前述元件背面形成硬化性的保護膜形成層之工程； 　　使前述保護膜形成層硬化而形成保護膜之工程； 　　在形成前述保護膜之後，從前述第二支撐薄板剝離前述密封體，而貼著於第三支撐薄板之工程；及 　　使被貼著於前述第三支撐薄板的前述密封體小片化之工程。 　　將前述密封體貼著於前述第二支撐薄板時，前述密封體是將前述外部端子電極朝向第二支撐薄板而貼著。 　　將前述密封體貼著於前述第三支撐薄板時，前述密封體是將前述保護膜朝向前述第三支撐薄板而貼著。 　　在本實施形態的半導體裝置的製造方法中，與從第一實施形態的半導體晶片貼著工程到外部端子電極連接工程為止同樣的工程會被實施。 　　並且，在本實施形態的半導體裝置的製造方法中，外部端子電極連接工程之後，與從第二實施形態的第二支撐薄板貼著工程到保護膜形成工程為止同樣的工程會被實施。 　　本實施形態的半導體裝置的製造方法主要是保護膜形成工程之後的工程會與第一實施形態及第二實施形態不同。由於第三實施形態在其他的點是與第一實施形態及第二實施形態同樣，因此將說明省略或簡略化。 　　圖6(圖6A及圖6B)是表示本實施形態的半導體裝置的製造方法之一例的圖。 (第三支撐薄板貼著工程) 　　在圖6A是表示說明在形成保護膜60A之後，從第二支撐薄板71剝離密封體3，而貼著於第三支撐薄板72的工程(有時稱為第三支撐薄板貼著工程)的剖面概略圖。 　　在第三支撐薄板貼著工程中，將形成保護膜60A後的密封體3貼著於第三支撐薄板72。密封體3是將保護膜60A朝向第三支撐薄板72而貼著。本實施形態的第三支撐薄板72也是與第一實施形態同樣，被使用在半導體裝置的製造工程的切割薄板為理想。在本實施形態中也是使密封體3支撐於貼著有環框RF2的第三支撐薄板72為理想。 (小片化工程) 　　在圖6B是表示說明使被貼著於第三支撐薄板72的密封體3小片化的工程(小片化工程)的剖面概略圖。 　　在本實施形態中也與第一實施形態同樣地使密封體3小片化。藉由使密封體3小片化，作為半導體裝置的半導體封裝1會被製造。 　　本實施形態的半導體裝置的製造方法是包含將半導體封裝1安裝於印刷配線基板等的工程(有時稱為安裝工程)也為理想。 　　半導體封裝1是在元件背面W2維持附有保護膜60A的情形下從第三支撐薄板72拾取。 ･實施形態的效果 　　若根據本實施形態，則取得與第一實施形態同樣的效果。 　　而且，在本實施形態中也是與第二實施形態同樣，由於支撐基板剝離工程是可對於被第二支撐薄板71支撐的密封體3實施，因此可容易從密封體3剝離支撐基板10。 　　而且，在本實施形態中也是與第二實施形態同樣，由於剝離支撐基板10後的密封體3是被第二支撐薄板71支撐，因此可容易實施保護膜形成層形成工程。 　　若根據本實施形態，則即使第二支撐薄板71未具有作為切割薄板的特性，還是可藉由在作為切割薄板的第三支撐薄板72貼著密封體3，來使密封體3小片化，可取得半導體封裝1。 [實施形態的變形] 　　本發明是不限於前述實施形態。本發明是包含在可達成本發明的目的之範圍將前述實施形態變形後的形態等。 　　在前述實施形態的半導體裝置的製造方法的任一中，亦可實施雷射印字於保護膜的工程(有時稱雷射印字工程)。 　　雷射印字是藉由雷射標記法來進行，藉由雷射光的照射來削掉保護膜的表面，藉此在保護膜標記產品的編號等。 　　在雷射印字工程中，亦可直接照射雷射光至保護膜，或隔著支撐薄板照射雷射光。 　　例如，在前述實施形態的半導體裝置的製造方法的任一中，雷射印字工程是在形成保護膜之後，比使被貼著於支撐薄板的密封體小片化的工程更前面實施為理想。若根據前述實施形態的半導體裝置的製造方法的任一，則可抑制密封體的彎曲，因此在實施雷射印字工程時，雷射光的焦點會正確地確定，可精度佳標記。 　　在前述實施形態的半導體裝置的製造方法及實施形態的變形的半導體裝置的製造方法的任一中，亦可在支撐基板剝離工程與保護膜形成層形成工程之間實施將密封體的露出的元件背面側研削的工程(有時稱為密封體研削工程)。藉由實施此研削工程，可將密封體的厚度形成薄，可謀求半導體裝置的薄型化。實施密封體研削工程時，在密封體的研削面形成保護膜形成層。 　　在前述實施形態中，是舉在支撐基板10貼附兩面黏著薄板20，使半導體晶片CP貼著於兩面黏著薄板20所具有的第一黏著劑層22的形態為例進行說明，但本發明是不限於如此的形態。 　　例如，在前述實施形態的半導體裝置的製造方法及實施形態的變形的半導體裝置的製造方法的任一中，亦可在支撐基板的表面形成黏著劑層，使半導體元件貼著於此黏著劑層。此情況的黏著劑層是含有與第一黏著劑層22同樣的黏著劑為理想。 　　利用密封構件來密封複數的半導體晶片CP的方法是不限於在前述實施形態說明的方法。例如，在前述實施形態的半導體裝置的製造方法及實施形態的變形的半導體裝置的製造方法的任一中，亦可採用將被支撐於支撐基板10的狀態的複數的半導體晶片CP載置於金屬模具內，在金屬模具內注入具有流動性的密封樹脂材料，使密封樹脂材料加熱硬化而形成密封樹脂層的方法。 　　並且，在前述實施形態的半導體裝置的製造方法及實施形態的變形的半導體裝置的製造方法的任一中，亦可採用將薄板狀的密封樹脂載置成覆蓋複數的半導體晶片CP的電路面W1，將薄板狀的密封樹脂載置成覆蓋半導體晶片CP，使密封樹脂加熱硬化，而形成密封樹脂層的方法。 　　在使用薄板狀的密封樹脂時，是藉由真空層壓法來密封半導體晶片CP為理想。 　　在前述實施形態的半導體裝置的製造方法及實施形態的變形的半導體裝置的製造方法的任一密封工程中，亦可用密封構件30來覆蓋半導體晶片CP的電路面W1側。此情況，實行使半導體晶片CP的連接端子W3露出於密封體3的表面的工程(有時稱為連接端子露出工程)。 　　在此連接端子露出工程中，除去覆蓋半導體晶片CP的電路面W1或連接端子W3的密封體3的表面側的密封樹脂層的一部分或全體來使連接端子W3露出。使半導體晶片CP的連接端子W3露出的方法並未被特別加以限定。作為使半導體晶片CP的連接端子W3露出的方法是例如可舉將密封樹脂層研削而使連接端子W3露出的方法，藉由雷射照射等的方法來除去密封樹脂層而使連接端子W3露出的方法，及藉由蝕刻法來除去密封樹脂層而使連接端子W3露出的方法等。只要連接端子W3與再配線層4及外部端子電極5能夠電性連接，亦可使連接端子W3的全體露出，或使連接端子W3的一部分露出。 　　半導體封裝是不限於在前述實施形態及實施形態的變形中說明的形態。亦可為使外部電極焊墊扇出於密封體的半導體元件的領域外，使外部端子電極連接至該外部電極焊墊的FO-WLP型的半導體封裝。 　　在前述實施形態及實施形態的變形是舉以半導體元件單位來使密封體小片化的形態為例進行說明，但本發明並非限於如此的形態。例如，亦可如包含複數的半導體元件之方式使密封體小片化，藉此製造包含複數的半導體元件的半導體封裝。[First Embodiment] 　　 Hereinafter, a method of manufacturing a semiconductor device according to this embodiment will be described. The manufacturing method of the semiconductor device of this embodiment includes: 　　 turn the back surface of the element toward the adhesive layer, and stick a plurality of semiconductor elements having a circuit surface and the back surface of the element opposite to the circuit surface on a support having the adhesive layer The process of the aforementioned adhesive layer of the substrate; 　　 the process of sealing the semiconductor element attached to the supporting substrate to form a sealed body; 　　 forming the external terminal electrode on the aforementioned sealing body, so that the substrate is attached to the supporting substrate The process of electrically connecting the semiconductor element and the external terminal electrode; 　　 after electrically connecting the semiconductor element and the external terminal electrode, the process of peeling the supporting substrate from the sealing body to expose the back surface of the semiconductor element　　 the process of forming a curable protective film forming layer on the exposed back surface of the semiconductor element; 　　 curing the protective film forming layer to form a protective film; 　　 after forming the protective film, attaching the sealing body to the first A process of supporting a thin plate; and a process of making the sealing body attached to the first supporting thin plate into small pieces. 1 (FIG. 1A, FIG. 1B, and FIG. 1C), FIG. 2 (FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D), and FIG. 3 (FIG. 3A and FIG. Diagram of an example. (Semiconductor wafer attaching process) 　　 In FIGS. 1A and 1B are cross-sections illustrating the process of attaching a semiconductor chip CP as a semiconductor element to a supporting substrate 10 having an adhesive layer (sometimes referred to as a semiconductor wafer attaching process) Sketch map. In addition, in FIG. 1A, one semiconductor wafer CP is shown, but in this embodiment, as shown in FIG. 1B, plural semiconductor wafers CP are attached to the adhesive layer. When attaching the semiconductor wafer CP, it is also possible to attach one by one, or attach a plurality of semiconductor wafers CP at the same time.　　 In this embodiment, the semiconductor chip CP is attached to the adhesive layer of the double-sided adhesive sheet 20, which is attached to the support substrate 10. ･Double-sided adhesive sheet 　　 Fig. 4 is a schematic cross-sectional view showing the double-sided adhesive sheet 20. The "double-sided adhesive sheet 20" has a base material 21, a first adhesive layer 22, and a second adhesive layer 23. The substrate 21 has a first substrate surface 211 and a second substrate surface 212 opposite to the first substrate surface 211. “”The first adhesive layer 22 is formed on the first substrate surface 211. The “second adhesive layer 23” is formed on the second substrate surface 212. "In this embodiment, the semiconductor chip CP is attached to the first adhesive layer 22, and the second adhesive layer 23 is attached to the support substrate 10. "As shown in FIG. 1, the semiconductor wafer CP used in this embodiment has the circuit surface W1 provided with the connection terminal W3, and the element back surface W2 on the opposite side of the circuit surface W1. In this embodiment, the back surface W2 of the element is attached to the first adhesive layer 22. In this way, the method of making the circuit surface W1 face up to stick to the first adhesive layer 22 is sometimes referred to as the face-up method.　　The first adhesive layer 22 contains an adhesive. The adhesive contained in the first adhesive layer 22 is not particularly limited, and various types of adhesives can be applied to the first adhesive layer 22. Examples of the adhesive contained in the first adhesive layer 22 include adhesives selected from the group consisting of rubber-based, acrylic-based, silicone-based, polyester-based, and polyurethane-based adhesives. In addition, the type of adhesive is selected in consideration of the application and the type of the object to be attached. When the first adhesive layer 22 is equipped with an energy-ray superimposing compound, energy rays are irradiated from the support substrate 10 side to the first adhesive layer 22 to harden the energy-beam superimposing compound. Once the energy-beam superimposing compound is hardened, the cohesive force of the first adhesive layer 22 becomes higher, and the adhesive force between the first adhesive layer 22 and the semiconductor chip CP, and the first adhesive layer 22 and the sealing member can be increased. The adhesion between the two decreases or disappears. For example, ultraviolet rays (UV) and electron rays (EB) can be cited as energy rays, and ultraviolet rays are preferable.　　The first adhesive layer 22 may also contain a foaming agent that is foamed by heating. In this case, by heating the foaming agent to foam, the adhesive force between the first adhesive layer 22 and the semiconductor chip CP, and the adhesive force between the first adhesive layer 22 and the sealing member can be reduced or eliminated .　　 The second adhesive layer 23 also contains an adhesive. The adhesive contained in the second adhesive layer 23 is not particularly limited, as long as it is a material that can fix the support substrate 10 and the double-sided adhesive sheet 20. The adhesive contained in the second adhesive layer 23 is preferably an adhesive such as the double-sided adhesive sheet 20 that can be peeled from the support substrate 10 as required. ･Support substrate The 　　support substrate 10 is a substrate for supporting the semiconductor wafer CP and the sealing body. The support substrate 10 is not particularly limited, as long as it is formed of a material that can support the semiconductor wafer CP and the sealing body. The supporting substrate 10 is preferably formed of a hard material. In this embodiment, the supporting substrate 10 is preferably made of glass. In addition, the support substrate 10 is preferably made of a rigid plastic film. (Sealing process) 　　 Fig. 1C is a schematic cross-sectional view illustrating a process of sealing a plurality of semiconductor wafers CP (may be referred to as a sealing process). ""The method of sealing the plural semiconductor wafers CP using the sealing member 30 is not specifically limited. In this embodiment, the sealing member 30 is used for sealing so that the circuit surface W1 side of the semiconductor wafer CP is not covered by the sealing member 30, thereby forming the sealing body 3. The sealing member 30 is also filled between the plurality of semiconductor wafers CP. As shown in FIG. 1C, on the surface of the sealing body 3, the circuit surface W1 of the semiconductor wafer CP and the connection terminal W3 are exposed. The material of the "sealing member 30" is preferably made of resin, and for example, epoxy resin or the like can be mentioned. The epoxy resin used as the sealing member 30 may contain, for example, a phenol resin, an elastomer, an inorganic filler, a hardening accelerator, and the like. For example, a liquid sealing resin can be used to seal so that the circuit surface W1 side of the semiconductor wafer CP is not covered by the sealing member 30.　　A process of further hardening the sealing member 30 (sometimes called an additional hardening process) may be performed between the sealing process and the subsequent process. In this process, a method of heating the sealing resin layer to promote hardening can be cited as an example. In addition, the additional hardening process may not be performed, and the sealing member 30 may be sufficiently hardened by the heating of the sealing process. (Rewiring layer forming process) 　　 In FIG. 2A is a schematic cross-sectional view illustrating a process of forming a rewiring layer 4 electrically connected to the semiconductor wafer CP (sometimes referred to as a rewiring layer forming process). "In the present embodiment, the rewiring layer 4 is electrically connected to the connection terminal W3 exposed on the surface of the sealing body 3. In this embodiment, the rewiring layer 4 is formed on the circuit surface W1 and the surface of the sealing body 3. The method of forming the rewiring layer 4 can be a conventionally known method. The "rewiring layer 4" has external electrode pads 41 for connecting external terminal electrodes. In this embodiment, a plurality of external electrode pads 41 are formed on the surface side of the rewiring layer 4. (External terminal electrode connection process) 　　 Fig. 2B is a schematic cross-sectional view illustrating a process of electrically connecting the external terminal electrode 5 to the rewiring layer 4 (sometimes referred to as an external terminal electrode connection process). Through this external terminal electrode connection process, the semiconductor chip CP and the external terminal electrode 5 will be electrically connected. "In the present embodiment, the external terminal electrode 5 such as a solder ball is placed on the external electrode pad 41, and the external terminal electrode 5 and the external electrode pad 41 are electrically connected by solder bonding or the like. The material of the solder balls is not particularly limited. Examples of the material of the solder balls include lead-containing solder and lead-free solder. (Support substrate peeling process) 　　 In FIG. 2C is a schematic cross-sectional view illustrating a process of peeling the support substrate 10 from the sealing body 3 to expose the device back surface W2 of the semiconductor wafer CP (may be referred to as a support substrate peeling process). "" The method of peeling the support substrate 10 from the sealing body 3 is not specifically limited. As a method of the support substrate peeling process, after peeling the support substrate 10 from the double-sided adhesive sheet 20, the method of peeling the double-sided adhesive sheet 20 from the sealing body 3 is mentioned. In addition, as a method of the support substrate peeling process, a method in which the support substrate 10 and the double-sided adhesive sheet 20 are integrated and peeled from the sealing body 3 can be mentioned. "When the first adhesive layer 22 is equipped with an energy-ray superimposing compound, energy rays are irradiated from the support substrate 10 side to the first adhesive layer 22 to harden the energy-ray superimposing compound. Once the energy-beam superimposing compound is hardened, the cohesive force of the first adhesive layer 22 becomes higher, and the adhesive force between the first adhesive layer 22 and the sealing body 3 can be reduced or disappeared. For example, ultraviolet rays (UV) and electron rays (EB) can be cited as energy rays, and ultraviolet rays are preferable. The method of reducing or disappearing the adhesive force between the first adhesive layer 22 and the sealing body 3 is not limited to energy ray irradiation. As a method of reducing or disappearing this adhesive force, for example, a method by heating, a method by heating and energy ray irradiation, and a method by cooling are mentioned. (Protective film forming layer formation process) 　　 is a schematic cross-sectional view illustrating the process of forming a curable protective film forming layer 60 on the device back surface W2 of the exposed semiconductor wafer CP (sometimes referred to as a protective film forming layer forming process) in FIG. 2D picture. In this embodiment, the protective film forming layer 60 is formed on the back surface (the surface opposite to the surface on which the rewiring layer 4 and the like are formed) of the sealing body 3 to cover the element back surface W2. "As the protective film forming layer 60 of this embodiment, for example, any one of thermosetting properties and energy ray curable properties can be used. The protective film forming layer 60 of the present embodiment is preferably formed using a material containing a curable adhesive composition that is cured by receiving energy from the outside. It is more desirable to attach an adhesive sheet containing the curable adhesive composition to the back surface of the sealing body 3 to form a protective film forming layer 60 to cover the back surface W2 of the device. """The energy supplied from the outside includes, for example, ultraviolet rays, electron rays, heat, and the like. The protective film forming layer 60 preferably contains at least one of an ultraviolet curable adhesive and a thermosetting adhesive. The protective film forming layer 60 is also preferably a thermosetting layer containing a thermosetting adhesive, and also preferably an ultraviolet curable layer containing an ultraviolet curing adhesive. "After forming the protective film forming layer 60, the process of hardening the protective film forming layer 60 to form the protective film 60A (refer to FIG. 3A)) (it may be called a protective film forming process) is implemented. (The first support sheet attaching process) 　　 In FIG. 3A, after the protective film forming layer 60 is cured to form the protective film 60A, the first support sheet 70 attached to the ring frame RF is attached to the sealing body 3 ( Sometimes referred to as the first supporting sheet pasting project) cross-sectional schematic diagram.　　The first support sheet 70 of this embodiment is preferably a dicing sheet used in the manufacturing process of a semiconductor device. It is desirable that the first supporting sheet 70 as a cutting sheet has a base film and an adhesive layer. The protective film 60A is directed to the adhesive layer of the first supporting sheet 70, and the sealing body 3 is attached to the first supporting sheet 70. In this case, the ring frame RF is placed on the adhesive layer of the first support sheet 70, and the ring frame RF is gently pushed to fix the ring frame RF and the first support sheet 70. Then, the adhesive layer exposed inside the ring shape of the ring frame RF is pushed onto the protective film 60A of the sealing body 3, and the sealing body 3 is fixed to the first supporting sheet 70. (Slicing process) 　　 In FIG. 3B is a schematic cross-sectional view showing a process of slicing the sealing body 3 attached to the first support sheet 70 (may be referred to as a slicing process). "In this embodiment, the sealing body 3 is small-sized by the unit of a semiconductor wafer CP." The method of forming the sealing body 3 into small pieces is not particularly limited. As a method of slicing, for example, a method of slicing using a cutting means such as a dicing saw, a laser irradiation method, and the like can be mentioned.　　 By making the sealing body 3 into small pieces, the semiconductor package 1 as a semiconductor device is manufactured. "It is also preferable that the manufacturing method of the semiconductor device of the present embodiment includes a process of mounting the semiconductor package 1 on a printed wiring board (sometimes referred to as a mounting process). The semiconductor package 1 is picked up from the first supporting sheet 70 while maintaining the protective film 60A attached to the back surface W2 of the element. ･Effects of the embodiment 　　 According to the present embodiment, since the semiconductor wafer CP is supported by the support substrate 10 in the sealing process, it is possible to suppress warpage when the semiconductor wafer CP is sealed with the sealing member 30. "According to the present embodiment, the rewiring layer formation process and the external terminal electrode connection process can be performed while maintaining the supporting substrate 10 to support the sealing body 3. Once the sealing body is bent, the surface of the sealing body is bent, and it is difficult to form a rewiring layer and external terminal electrodes. However, since the bending of the sealing body 3 is suppressed, the plural semiconductor wafers CP in the sealing body 3 can be formed with high precision. Wiring layer 4 and external terminal electrode 5. "Furthermore, since the sealing body 3 is supported by the supporting substrate 10, the handling performance of the sealing body 3 is improved. Especially when the thickness of the semiconductor wafer CP and the thickness of the sealing body 3 are thin, the manufacturing method of the semiconductor element of this embodiment is effective. [Second Embodiment] 　　 Next, the second embodiment of the present invention will be described. The manufacturing method of the semiconductor device of this embodiment includes: 　　 turn the back surface of the element toward the adhesive layer, and stick a plurality of semiconductor elements having a circuit surface and the back surface of the element opposite to the circuit surface on a support having the adhesive layer The process of the aforementioned adhesive layer of the substrate; 　　 the process of sealing the semiconductor element attached to the supporting substrate to form a sealed body; 　　 forming the external terminal electrode on the aforementioned sealing body, so that the substrate is attached to the supporting substrate The process of electrically connecting the semiconductor element and the external terminal electrode; 　　 after electrically connecting the semiconductor element and the external terminal electrode, the process of attaching the sealing body to the second supporting sheet; 　　 attaching the sealing body to the After the second supporting sheet, the process of peeling the supporting substrate from the sealing body to expose the back surface of the semiconductor element; 　　 forming a curable protective film forming layer on the back surface of the exposed semiconductor element; The process of hardening the protective film forming layer to form a protective film; and the process of making the sealing body attached to the second supporting sheet into small pieces.　　The sealing body is made to adhere to the second supporting sheet with the external terminal electrode facing the second supporting sheet. "In the method of manufacturing a semiconductor device of the present embodiment, the same processes as the semiconductor wafer bonding process of the first embodiment to the external terminal electrode connection process are carried out. "The manufacturing method of the semiconductor device of this embodiment differs from the first embodiment in the process after the main external terminal electrode connection process." The second embodiment is the same as the first embodiment in other points, so the description is omitted or simplified.　　 FIG. 5 (FIG. 5A, FIG. 5B, FIG. 5C, and FIG. 5D) is a diagram showing an example of a method of manufacturing a semiconductor device of this embodiment. (Second support sheet attaching process) 　　 In FIG. 5A, after the external terminal electrode 5 is electrically connected to the semiconductor chip CP, the sealing body 3 is attached to the second support sheet before the support substrate 10 is peeled from the sealing body 3 A schematic cross-sectional view of the 71 project (sometimes called the second supporting sheet pasting project).　　 In the second supporting sheet attaching process, the sealing body 3 in a state supported by the supporting substrate 10 is attached to the second supporting sheet 71. The sealing body 3 is attached with the external terminal electrode 5 facing the second supporting sheet 71. In this embodiment, it is also desirable that the second support sheet 71 has a base film and an adhesive layer. In this embodiment, it is also desirable to support the sealing body 3 on the second supporting sheet 71 to which the ring frame RF is attached. In addition, the second supporting sheet 71 is preferably a dicing sheet used in the manufacturing process of a semiconductor device. (Support Substrate Peeling Process) 　　 In FIG. 5B, the process of peeling the support substrate 10 from the sealing body 3 to expose the device back surface W2 of the semiconductor wafer CP (support substrate peeling) after the sealing body 3 is attached to the second support sheet 71 is shown. Engineering) cross-sectional schematic diagram.　　 Also in this embodiment, the method of peeling the support substrate 10 from the sealing body 3 is not particularly limited. For example, the method described in the first embodiment can be adopted. As a method of the support substrate peeling process of the present embodiment, a method of peeling the double-sided adhesive sheet 20 from the sealing body 3 after peeling the support substrate 10 from the double-sided adhesive sheet 20 is exemplified. In addition, as a method of the support substrate peeling process of the present embodiment, a method in which the support substrate 10 and the double-sided adhesive sheet 20 are integrated and peeled from the sealing body 3 can be mentioned. (Protective film forming layer formation process) 　　 In FIG. 5C is a schematic cross-sectional view illustrating the process (protective film forming layer forming process) of forming the curable protective film forming layer 60 on the element back surface W2 of the exposed semiconductor wafer CP. "In the present embodiment, the protective film forming layer 60 is formed on the sealing body 3 supported by the second supporting sheet 71. The protective film forming layer 60 is formed on the back surface (the surface opposite to the surface on which the rewiring layer 4 and the like are formed) of the sealing body 3 to cover the device back surface W2. "The method of forming the protective film forming layer 60 of the present embodiment is the same as that of the protective film forming layer 60 of the first embodiment. When the second support sheet 71 has heat resistance, it is possible to suppress the occurrence of residual stress and glue residue during thermal curing. Therefore, the protective film forming layer 60 is preferably a thermosetting layer containing a thermosetting adhesive. The protective film forming layer 60 is preferably an ultraviolet curable layer containing an ultraviolet curable adhesive. "In this embodiment, too, the process of hardening the protective film forming layer 60 of the sealing body 3 supported by the second support sheet 71 to form the protective film 60A (refer to FIG. 5D) (protective film forming process) is performed. The method of curing the protective film forming layer 60 is the same as in the first embodiment. (Slicing process) 　　 In FIG. 5D is a schematic cross-sectional view illustrating the process of slicing the sealing body 3 attached to the second support sheet 71 (the slicing process).　　 In this embodiment, the sealing body 3 is also made into small pieces in the same manner as in the first embodiment. By making the sealing body 3 into small pieces, the semiconductor package 1 as a semiconductor device is manufactured. "It is also preferable that the manufacturing method of the semiconductor device of the present embodiment includes a process of mounting the semiconductor package 1 on a printed wiring board (sometimes referred to as a mounting process). The semiconductor package 1 is picked up from the second supporting sheet 71 while maintaining the protective film 60A attached to the back surface W2 of the element. ･Effects of the embodiment 　　 According to this embodiment, the same effect as the first embodiment can be obtained. "Furthermore, according to the present embodiment, since the support substrate peeling process can be performed on the sealing body 3 supported by the second support sheet 71, the support substrate 10 can be easily peeled from the sealing body 3. "Moreover, according to this embodiment, since the sealing body 3 after peeling the support substrate 10 is supported by the 2nd support sheet 71, it is easy to implement the protective film formation layer formation process. When the second support sheet 71 is a dicing sheet, the process from the peeling process of the support substrate to the slicing process can be carried out while maintaining the second support sheet 71 to support the sealing body 3, so that the manufacturing process of the semiconductor device can be simplified. change. [Third Embodiment] 　　 Next, a third embodiment of the present invention will be described. The manufacturing method of the semiconductor device of this embodiment includes: 　　 turn the back surface of the element toward the adhesive layer, and stick a plurality of semiconductor elements having a circuit surface and the back surface of the element opposite to the circuit surface on a support having the adhesive layer The process of the aforementioned adhesive layer of the substrate; 　　 the process of sealing the semiconductor element attached to the supporting substrate to form a sealed body; 　　 forming the external terminal electrode on the aforementioned sealing body, so that the substrate is attached to the supporting substrate The process of electrically connecting the semiconductor element and the external terminal electrode; 　　 after electrically connecting the semiconductor element and the external terminal electrode, the process of attaching the sealing body to the second supporting sheet; 　　 attaching the sealing body to the After the second supporting sheet, the process of peeling the supporting substrate from the sealing body to expose the back surface of the semiconductor element; 　　 forming a curable protective film forming layer on the back surface of the exposed semiconductor element; The process of hardening the protective film forming layer to form a protective film; 　　 after forming the protective film, peeling the sealing body from the second supporting sheet and attaching it to the third supporting sheet; and making it adhere to the foregoing The third supporting sheet is a process of slicing the aforementioned sealing body. "When the sealing body is stuck to the second supporting sheet, the sealing body is stuck with the external terminal electrode facing the second supporting sheet. "When the sealing body is attached to the third supporting sheet, the sealing body is attached with the protective film facing the third supporting sheet. "In the method of manufacturing a semiconductor device of the present embodiment, the same processes as the semiconductor wafer bonding process of the first embodiment to the external terminal electrode connection process are carried out. "In addition, in the manufacturing method of the semiconductor device of this embodiment, after the external terminal electrode connection process, the same process as the process from the second support sheet sticking process of the second embodiment to the protective film formation process is performed. "The manufacturing method of the semiconductor device of the present embodiment is mainly different from the first embodiment and the second embodiment in the process after the protective film formation process. Since the third embodiment is the same as the first embodiment and the second embodiment in other points, the description will be omitted or simplified.　　 FIG. 6 (FIG. 6A and FIG. 6B) is a diagram showing an example of a method of manufacturing a semiconductor device of this embodiment. (The third support sheet attaching process) 　　 In FIG. 6A, after the protective film 60A is formed, the sealing body 3 is peeled from the second support sheet 71 and attached to the third support sheet 72 (sometimes referred to as the first Three support sheet attached to the project) schematic cross-sectional view.　　 In the third supporting sheet attaching process, the sealing body 3 after the protective film 60A is formed is attached to the third supporting sheet 72. The sealing body 3 adheres the protective film 60A toward the third supporting sheet 72. The third supporting sheet 72 of this embodiment is also the same as the first embodiment, and a dicing sheet used in the manufacturing process of a semiconductor device is ideal. In this embodiment, it is also desirable to support the sealing body 3 on the third supporting sheet 72 to which the ring frame RF2 is attached. (Slicing process) 　　 In FIG. 6B is a schematic cross-sectional view illustrating the process of slicing the sealing body 3 attached to the third supporting sheet 72 (the slicing process).　　 In this embodiment, the sealing body 3 is also made into small pieces in the same manner as in the first embodiment. By making the sealing body 3 into small pieces, the semiconductor package 1 as a semiconductor device is manufactured. "It is also preferable that the manufacturing method of the semiconductor device of the present embodiment includes a process of mounting the semiconductor package 1 on a printed wiring board (sometimes referred to as a mounting process). "The semiconductor package 1 is picked up from the third supporting sheet 72 while maintaining the protective film 60A attached to the back surface W2 of the element. ･Effects of the embodiment 　　 According to this embodiment, the same effect as the first embodiment can be obtained. "Furthermore, in this embodiment, as in the second embodiment, since the support substrate peeling process can be performed on the sealing body 3 supported by the second support sheet 71, the support substrate 10 can be easily peeled from the sealing body 3. "Furthermore, in this embodiment, as in the second embodiment, since the sealing body 3 after peeling the support substrate 10 is supported by the second support sheet 71, the protective film forming layer forming process can be easily performed. According to this embodiment, even if the second supporting sheet 71 does not have the characteristics of a cutting sheet, the sealing body 3 can be made into small pieces by sticking the sealing body 3 to the third supporting sheet 72 which is a cutting sheet. Get semiconductor package 1. [Modifications of the embodiment] "The present invention is not limited to the aforementioned embodiment. The present invention includes a modified form of the foregoing embodiment within the scope of achieving the object of the present invention. "In any of the manufacturing methods of the semiconductor device of the foregoing embodiment, a process of laser printing on the protective film (sometimes called a laser printing process) may be performed.　　Laser printing is performed by the laser marking method. The surface of the protective film is shaved off by the irradiation of laser light, thereby marking the product number on the protective film.　　In the laser printing process, the laser light can also be directly irradiated to the protective film, or the laser light can be irradiated through the supporting sheet. "For example, in any of the semiconductor device manufacturing methods of the foregoing embodiments, the laser printing process is preferably performed before the process of slicing the sealing body attached to the support sheet after the protective film is formed. According to any of the semiconductor device manufacturing methods of the foregoing embodiments, the bending of the sealing body can be suppressed. Therefore, when the laser printing process is performed, the focus of the laser light can be accurately determined, and marking can be performed with high accuracy. In any of the semiconductor device manufacturing method of the foregoing embodiment and the semiconductor device manufacturing method of the modification of the embodiment, the element for exposing the sealing body may be performed between the supporting substrate peeling process and the protective film forming layer forming process The grinding process of the back side (sometimes called the sealing body grinding process). By implementing this grinding process, the thickness of the sealing body can be made thin, and the thickness of the semiconductor device can be reduced. When the sealing body grinding process is carried out, a protective film forming layer is formed on the grinding surface of the sealing body. In the foregoing embodiment, the double-sided adhesive sheet 20 is attached to the support substrate 10, and the semiconductor chip CP is attached to the first adhesive layer 22 of the double-sided adhesive sheet 20 as an example. However, the present invention is It is not limited to such a form. For example, in any of the semiconductor device manufacturing method of the foregoing embodiment and the modified semiconductor device manufacturing method of the embodiment, an adhesive layer may be formed on the surface of the support substrate, and the semiconductor element may be attached to the adhesive layer . In this case, the adhesive layer preferably contains the same adhesive as the first adhesive layer 22. "The method of sealing the plural semiconductor wafers CP with the sealing member is not limited to the method demonstrated in the foregoing embodiment." For example, in any of the semiconductor device manufacturing method of the foregoing embodiment and the semiconductor device manufacturing method of the modification of the embodiment, a plurality of semiconductor wafers CP in a state supported on the support substrate 10 may be mounted on a metal A method of injecting a fluid sealing resin material into a metal mold in a mold, and heating and hardening the sealing resin material to form a sealing resin layer. In addition, in any of the semiconductor device manufacturing method of the foregoing embodiment and the semiconductor device manufacturing method of the modification of the embodiment, a thin plate-shaped sealing resin may be placed so as to cover the circuit surface W1 of the plurality of semiconductor wafers CP. A method of placing a thin plate-shaped sealing resin to cover the semiconductor wafer CP, and heating and hardening the sealing resin to form a sealing resin layer.　　 When a thin-plate-shaped sealing resin is used, it is ideal to seal the semiconductor wafer CP by a vacuum lamination method. "In any of the sealing process of the manufacturing method of the semiconductor device of the foregoing embodiment and the manufacturing method of the semiconductor device of the modification of the embodiment, the sealing member 30 may cover the circuit surface W1 side of the semiconductor wafer CP. In this case, a process of exposing the connection terminal W3 of the semiconductor wafer CP on the surface of the sealing body 3 (may be referred to as a connection terminal exposure process) is performed. "In this connection terminal exposure process, part or all of the sealing resin layer on the surface side of the sealing body 3 covering the circuit surface W1 of the semiconductor chip CP or the connection terminal W3 is removed, and the connection terminal W3 is exposed. The method of exposing the connection terminal W3 of the semiconductor wafer CP is not particularly limited. As a method of exposing the connection terminal W3 of the semiconductor chip CP, for example, a method of grinding the sealing resin layer to expose the connection terminal W3, and removing the sealing resin layer by a method such as laser irradiation to expose the connection terminal W3 A method, a method of removing the sealing resin layer by an etching method and exposing the connection terminal W3, and the like. As long as the connection terminal W3 can be electrically connected to the rewiring layer 4 and the external terminal electrode 5, the entire connection terminal W3 may be exposed, or a part of the connection terminal W3 may be exposed. The "semiconductor package" is not limited to the form described in the foregoing embodiment and the modification of the embodiment. It may also be a FO-WLP type semiconductor package in which external electrode pads are fanned out of the area of the semiconductor element of the sealed body, and external terminal electrodes are connected to the external electrode pads.　　 In the foregoing embodiment and the modification of the embodiment, a mode in which the sealing body is divided into small pieces in the unit of a semiconductor element is described as an example, but the present invention is not limited to such a mode. For example, it is also possible to singulate the sealing body into small pieces as it includes a plurality of semiconductor elements, thereby manufacturing a semiconductor package including a plurality of semiconductor elements.

1‧‧‧半導體封裝3‧‧‧密封體4‧‧‧再配線層5‧‧‧外部端子電極10‧‧‧支撐基板20‧‧‧兩面黏著薄板21‧‧‧基材22‧‧‧第一黏著劑層23‧‧‧第二黏著劑層30‧‧‧密封構件41‧‧‧外部電極焊墊60‧‧‧保護膜形成層60A‧‧‧保護膜70‧‧‧第一支撐薄板71‧‧‧第二支撐薄板72‧‧‧第三支撐薄板211‧‧‧第一基材面212‧‧‧第二基材面CP‧‧‧半導體晶片W1‧‧‧電路面W2‧‧‧元件背面W3‧‧‧連接端子RF‧‧‧環框1‧‧‧Semiconductor package 3‧‧‧Sealing body 4‧‧‧Rewiring layer 5‧‧‧External terminal electrode 10‧‧‧Support substrate 20‧‧‧Both sides adhesive sheet 21‧‧‧Base material 22‧‧‧Section An adhesive layer 23‧‧‧Second adhesive layer 30‧‧‧Sealing member 41‧‧‧External electrode pad 60‧‧‧Protective film forming layer 60A‧‧‧Protective film 70‧‧‧First supporting sheet 71 ‧‧‧Second supporting sheet 72‧‧‧Third supporting sheet 211‧‧‧First substrate surface 212‧‧‧Second substrate surface CP‧‧‧Semiconductor wafer W1‧‧‧Circuit surface W2‧‧‧Component W3‧‧‧Connecting terminal RF‧‧‧Ring frame

圖1A是說明第一實施形態的半導體裝置的製造方法的剖面圖。 　　圖1B是說明第一實施形態的半導體裝置的製造方法的剖面圖。 　　圖1C是說明第一實施形態的半導體裝置的製造方法的剖面圖。 　　圖2A是接續於圖1A、圖1B及圖1C，說明第一實施形態的製造方法的剖面圖。 　　圖2B是接續於圖1A、圖1B及圖1C，說明第一實施形態的製造方法的剖面圖。 　　圖2C是接續於圖1A、圖1B及圖1C，說明第一實施形態的製造方法的剖面圖。 　　圖2D是接續於圖1A、圖1B及圖1C，說明第一實施形態的製造方法的剖面圖。 　　圖3A是接續於圖2A、圖2B、圖2C及圖2D，說明第一實施形態的製造方法的剖面圖。 　　圖3B是接續於圖2A、圖2B、圖2C及圖2D，說明第一實施形態的製造方法的剖面圖。 　　圖4是使用在第一實施形態的兩面黏著薄板的剖面圖。 　　圖5A是說明第二實施形態的半導體裝置的製造方法的剖面圖。 　　圖5B是說明第二實施形態的半導體裝置的製造方法的剖面圖。 　　圖5C是說明第二實施形態的半導體裝置的製造方法的剖面圖。 　　圖5D是說明第二實施形態的半導體裝置的製造方法的剖面圖。 　　圖6A是說明第三實施形態的半導體裝置的製造方法的剖面圖。 　　圖6B是說明第三實施形態的半導體裝置的製造方法的剖面圖。FIG. 1A is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment.　　 FIG. 1B is a cross-sectional view illustrating the method of manufacturing the semiconductor device of the first embodiment.　　 FIG. 1C is a cross-sectional view illustrating the method of manufacturing the semiconductor device of the first embodiment.　　 FIG. 2A is a cross-sectional view continued from FIG. 1A, FIG. 1B, and FIG. 1C to illustrate the manufacturing method of the first embodiment.　　 FIG. 2B is a cross-sectional view continued from FIG. 1A, FIG. 1B, and FIG. 1C to illustrate the manufacturing method of the first embodiment.　　 FIG. 2C is a cross-sectional view continued from FIG. 1A, FIG. 1B, and FIG. 1C to illustrate the manufacturing method of the first embodiment.　　 FIG. 2D is a cross-sectional view continued from FIG. 1A, FIG. 1B, and FIG. 1C to illustrate the manufacturing method of the first embodiment.　　 FIG. 3A is a cross-sectional view continuing from FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D, illustrating the manufacturing method of the first embodiment.　　 FIG. 3B is a cross-sectional view continuing from FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D, illustrating the manufacturing method of the first embodiment.　　 Figure 4 is a cross-sectional view of the double-sided adhesive sheet used in the first embodiment.　　 FIG. 5A is a cross-sectional view illustrating the method of manufacturing the semiconductor device of the second embodiment.　　 FIG. 5B is a cross-sectional view illustrating the method of manufacturing the semiconductor device of the second embodiment.　　 FIG. 5C is a cross-sectional view illustrating the method of manufacturing the semiconductor device of the second embodiment.　　 FIG. 5D is a cross-sectional view illustrating the method of manufacturing the semiconductor device of the second embodiment.　　 FIG. 6A is a cross-sectional view illustrating the method of manufacturing the semiconductor device of the third embodiment.　　 FIG. 6B is a cross-sectional view illustrating the method of manufacturing the semiconductor device of the third embodiment.

3‧‧‧密封體 3‧‧‧Seal body

4‧‧‧再配線層 4‧‧‧Rewiring layer

5‧‧‧外部端子電極 5‧‧‧External terminal electrode

10‧‧‧支撐基板 10‧‧‧Support substrate

20‧‧‧兩面黏著薄板 20‧‧‧Two-sided adhesive sheet

30‧‧‧密封構件 30‧‧‧Sealing components

41‧‧‧外部電極焊墊 41‧‧‧External electrode pad

60‧‧‧保護膜形成層 60‧‧‧Protection film forming layer

CP‧‧‧半導體晶片 CP‧‧‧Semiconductor chip

W1‧‧‧電路面 W1‧‧‧Circuit surface

W2‧‧‧元件背面 W2‧‧‧The back of the component

W3‧‧‧連接端子 W3‧‧‧Connecting terminal

Claims (4)

一種半導體裝置的製造方法，其特徵為包含：將元件背面朝向黏著劑層，使具有電路面及與前述電路面相反側的前述元件背面之複數的半導體元件貼著於具有前述黏著劑層的支撐基板的前述黏著劑層之工程；將被貼著於前述支撐基板的前述半導體元件密封，而形成密封體之工程；將外部端子電極形成於前述密封體，而使被貼著於前述支撐基板的前述半導體元件與前述外部端子電極電性連接之工程；在使前述半導體元件與前述外部端子電極電性連接之後，從前述密封體剝離前述支撐基板，而使前述半導體元件的前述元件背面露出之工程；在露出的前述半導體元件的前述元件背面形成硬化性的保護膜形成層之工程；使前述保護膜形成層硬化而形成保護膜之工程。更包含：使前述半導體元件與前述外部端子電極電性連接之後，從前述密封體剝離前述支撐基板之前，將前述密封體貼著於第二支撐薄板之工程，將前述密封體的前述外部端子電極朝前述第二支撐薄板貼著。 A method of manufacturing a semiconductor device, comprising: turning the back surface of the element toward an adhesive layer, and attaching a plurality of semiconductor elements having a circuit surface and the back surface of the element opposite to the circuit surface on a support having the adhesive layer The process of the adhesive layer of the substrate; the process of sealing the semiconductor element attached to the supporting substrate to form a sealed body; forming the external terminal electrode on the sealing body so that the substrate is attached to the supporting substrate The process of electrically connecting the semiconductor element and the external terminal electrode; after electrically connecting the semiconductor element and the external terminal electrode, the process of peeling the supporting substrate from the sealing body to expose the back surface of the semiconductor element The process of forming a curable protective film forming layer on the exposed back surface of the element of the semiconductor element; the process of curing the protective film forming layer to form a protective film. It further includes: after electrically connecting the semiconductor element and the external terminal electrode, before peeling off the supporting substrate from the sealing body, the process of attaching the sealing body to the second supporting sheet, and facing the external terminal electrode of the sealing body The aforementioned second supporting sheet is attached to it. 如申請專利範圍第1項之半導體裝置的製造方法，其中，將前述密封體貼著於前述第二支撐薄板，從前述密封體剝離前述支撐基板之後，在露出的前述半導體元件的前述元件背面形成前述保護膜形成層。 The method for manufacturing a semiconductor device according to the first patent application, wherein the sealing body is attached to the second supporting sheet, and the supporting substrate is peeled from the sealing body, and then the semiconductor device is exposed on the back surface of the semiconductor device. The protective film forms the layer. 如申請專利範圍第2項之半導體裝置的製造方法，其中，更包含：在形成前述保護膜之後，使被貼著於前述第二支撐薄板的前述密封體小片化之工程。 For example, the method for manufacturing a semiconductor device according to the second patent application, further comprising: after forming the protective film, the process of slicing the sealing body attached to the second supporting sheet. 如申請專利範圍第2項之半導體裝置的製造方法，其中，更包含：在形成前述保護膜之後，從前述第二支撐薄板剝離前述密封體，而貼著於第三支撐薄板之工程；使被貼著於前述第三支撐薄板的前述密封體小片化之工程。 For example, the method of manufacturing a semiconductor device of the second patent application, which further includes: after forming the protective film, peeling the sealing body from the second supporting sheet and attaching it to the third supporting sheet; The process of making the sealing body attached to the third supporting sheet into small pieces.
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JP7238301B2 (en) * 2018-09-05 2023-03-14 株式会社レゾナック Material selection method and panel manufacturing method
TWI872063B (en) * 2019-04-26 2025-02-11 日商琳得科股份有限公司 Method for manufacturing a third laminate, and method for manufacturing a fourth laminate
JP7395898B2 (en) * 2019-09-18 2023-12-12 大日本印刷株式会社 Components for semiconductor multi-sided mounting boards, semiconductor multi-sided mounting boards, and semiconductor components
WO2022185489A1 (en) * 2021-03-04 2022-09-09 昭和電工マテリアルズ株式会社 Method for manufacturing semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006222164A (en) * 2005-02-08 2006-08-24 Shinko Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
US20130078770A1 (en) * 2011-09-28 2013-03-28 Nitto Denko Corporation Method for producing semiconductor device
US20130157419A1 (en) * 2011-12-19 2013-06-20 Nitto Denko Corporation Method of manufacturing semiconductor device
US20140191406A1 (en) * 2011-10-19 2014-07-10 Panasonic Corporation Manufacturing method for semiconductor package, semiconductor package, and semiconductor device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3456462B2 (en) * 2000-02-28 2003-10-14 日本電気株式会社 Semiconductor device and manufacturing method thereof
JP3455948B2 (en) 2000-05-19 2003-10-14 カシオ計算機株式会社 Semiconductor device and manufacturing method thereof
JP4719042B2 (en) * 2006-03-16 2011-07-06 株式会社東芝 Manufacturing method of semiconductor device
JP2009032929A (en) * 2007-07-27 2009-02-12 Sanyo Electric Co Ltd Semiconductor device and manufacturing method thereof
JP5456440B2 (en) * 2009-01-30 2014-03-26 日東電工株式会社 Dicing tape integrated wafer back surface protection film
JP5718005B2 (en) 2010-09-14 2015-05-13 日東電工株式会社 A heat-resistant adhesive tape for manufacturing a semiconductor device and a method for manufacturing a semiconductor device using the tape.
JP2014197568A (en) * 2011-10-19 2014-10-16 パナソニック株式会社 Method for manufacturing semiconductor package, semiconductor package and semiconductor device
US9385102B2 (en) * 2012-09-28 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package
CN103887251B (en) * 2014-04-02 2016-08-24 华进半导体封装先导技术研发中心有限公司 Fan-out-type wafer level packaging structure and manufacturing process
CN104103528A (en) 2014-07-22 2014-10-15 华进半导体封装先导技术研发中心有限公司 Fan out type square piece level semiconductor three dimension chip packaging technology
JP6417142B2 (en) * 2014-07-23 2018-10-31 株式会社ジェイデバイス Semiconductor device and manufacturing method thereof
CN204497228U (en) * 2015-03-16 2015-07-22 苏州晶方半导体科技股份有限公司 Chip-packaging structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006222164A (en) * 2005-02-08 2006-08-24 Shinko Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
US20130078770A1 (en) * 2011-09-28 2013-03-28 Nitto Denko Corporation Method for producing semiconductor device
US20140191406A1 (en) * 2011-10-19 2014-07-10 Panasonic Corporation Manufacturing method for semiconductor package, semiconductor package, and semiconductor device
US20130157419A1 (en) * 2011-12-19 2013-06-20 Nitto Denko Corporation Method of manufacturing semiconductor device

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