TWI789663B - Memory device and method of fabricating the same - Google Patents

Abstract

A memory device includes: a substrate, including a plurality of blocks, each block includes a staircase region, a memory array region and a word line cutting region; a stack structure located on the substrate in the memory array region, wherein the stack structure includes a plurality of first insulating layers and a plurality of conductor layers alternately stacked on each other; a first staircase structure located on the substrate in the staircase region, wherein the first staircase region structure includes a plurality of first insulating layers and a plurality of conductive layers alternately stacked with each other; and a first part of a second staircase structure located on the substrate in the word line cutting region, wherein the first part of the second staircase structure includes a plurality of first insulating layers and a plurality of conductive layers alternately stacked with each other, and two first parts of two second staircase structure in adjacent two blocks are separated from each other.

Description

Memory element and manufacturing method thereof

The embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof, and in particular to a memory device and a manufacturing method thereof.

Non-volatile memory devices (eg, flash memory) are widely used in personal computers and other electronic devices due to the advantage that stored data will not disappear after power failure.

Currently, the flash memory arrays commonly used in the industry include Negative-OR (NOR) flash memory and Negative-And (NAND) flash memory. Since the structure of NAND flash memory is to connect memory cells in series, its integration and area utilization are better than that of NOR flash memory, and it has been widely used in various electronic products. In addition, in order to further enhance the integration of memory components, a three-dimensional NAND flash memory has been developed. However, there are still many challenges associated with 3D NAND flash memory.

The invention provides a memory device capable of separating word lines of two adjacent blocks from each other.

In one embodiment of the present invention, a memory device includes: a substrate including a plurality of blocks, each block including a step area, a memory array area and a word line cutting area, wherein the memory array area is located in the Between the step area and the word line cutting area; a stack structure located on the substrate in the memory array area, wherein the stack structure includes a plurality of first insulating layers and a plurality of conductor layers stacked alternately with each other a first stepped structure located on the substrate in the stepped region, wherein the first stepped structure includes a plurality of first insulating layers and a plurality of conductor layers alternately stacked on each other; and a first part of the second stepped structure , located on the substrate in the word line cutting area, wherein the first part of the second ladder structure includes a plurality of first insulating layers and a plurality of conductor layers stacked alternately, and two adjacent The two second ladder structures of the blocks are separated from each other.

In one embodiment of the present invention, a method for manufacturing a memory device includes: providing a substrate, including a plurality of blocks, each block including a step area, a memory array area, and a word line cutting area, wherein the memory array The area is located between the step area and the word line cut area; a stack structure is formed on the substrate in the step area, the memory array area and the word line cut area, wherein the stack The structure includes a plurality of first insulating layers and a plurality of second insulating layers stacked alternately; patterning the stacked structure in the step area to form a first step structure; patterning the word line cutting area The stacked structure is used to form the first part of the second ladder structure, so that the two second ladder structures of two adjacent blocks are separated from each other; and a replacement process is performed to separate the memory array area. stack structure, the first ladder structure in the ladder area, and the second ladder junction in the word line cutting area The first portion of the structure is replaced by a plurality of conductor layers.

Based on the above, in the embodiment of the present invention, the stacked structure between two adjacent blocks is patterned into a ladder structure and a dielectric layer with an inverted ladder structure is provided to separate word lines of different blocks from each other.

10: Base

20: Component layer

30, 40: Metal interconnection structure

32, 42: dielectric layer

34, 44: plug

33: Metal interconnection

36, 46: Wire

90, 101: stack structure

92, 102, 102 ₁₄ , 102 ₁₃ , 102 ₁₂ , 102 ₁₁ , 102 ₁₀ , 102 ₉ , 102 8, 102 ₇ , 102 ₆ , 102 ₅ , 102 ₄ , 102 ₃ , 102 _{2 ,} 102 ₁ : insulating layer

94: conductor layer

106, OP1, OP2, OP3, OP4, OP11, OP12, OP13, OP14, OP21, OP22, OP23, OP24, OP31, OP32, OP33, OP34, OP41, OP42, OP43, OP44: opening

102T: top insulating layer

103: Dielectric layer

103 ₁ , 103 ₂ , 103 ₃ : island-shaped dielectric layer

104, 104 ₁₄ , 104 ₁₃ , 104 ₁₂ , 104 ₁₁ , 104 ₁₀ , 104 9 , 104 ₈ , 104 ₇ , 104 ₆ , 104 ₅ , 104 ₄ , _{104 3} , 104 ₂ , 104 ₁ : sacrificial layer

105: stop layer

107:Choose the source line to cut the wall

108:Charge storage structure

110: Channel layer

111: Groove

112: Insulation column

113: insulation wall

114: conductor plug

115: insulating roof layer

116, 119: ditches

117: gap wall

118, 118 ₁ , 118 ₂ , 118 ₃ : source line conductor wall

121: horizontal opening

120: source line

122: barrier layer

124: metal layer

126: gate layer

A1: District 1

A2: The second area

A3: The third area

A4: District 4

B, B1, B2, B3, B4: blocks

C1, C2, C3, C5: contact window

CP: vertical channel column

D1, D2: direction

H1, H2, H3, H4: Depth

P1, P2, P3, P4: part

PL1, PL2, PL3, PL4: Support structure

R1, R5: Surrounding area

R2: Ladder area

R3: memory array area

R4: character line cutting area

PR1, PR1', PR2, PR2': mask layer

SC1, SC2, SC3, SC4: ladder structure

SC4a, SC4b, SC4c, SC4d, SC4e, SC4f: sub-ladder structure

SC4 ₁ , SC4 ₂ , SC4 ₃ : island-like ladder structure

T1: first stage

T2: the second stage

T3: The third stage

T4: The fourth stage

TSC1, TSC2, TSC4, TSC1', TSC4': transition ladder structure

W1, W2, W3, W4, W5: Width

I-I, II-II, A-A, B-B, C-C: tangent

FIG. 1 is a top view of a three-dimensional memory device according to an embodiment of the present invention.

2A to 2P are schematic cross-sectional views of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing cut lines A-A, B-B, and C-C in FIG. 1 .

4A, 5A, 6A, and 7A are respectively top views of a three-dimensional memory device according to an embodiment of the present invention.

4B, 5B, 6B, and 7B are cross-sectional views of tangent line I-I in FIGS. 4A, 5A, 6A, and 7A, respectively.

FIG. 1 is a top view of a three-dimensional memory device according to an embodiment of the present invention. 2A to 2P are schematic cross-sectional views of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention. 2A to 2P are schematic cross-sectional views along line I-I in FIG. 1 . For clarity, only some components are shown in FIG. 1 .

Please refer to FIG. 1 and FIG. 2A , a three-dimensional memory device 100 is formed on a substrate 10 . Along the direction D2, the substrate 10 is divided into a plurality of blocks B arranged along the direction D2, such as blocks B1, B2, B3 and B4. Along the direction D1, each block B includes a peripheral area R1, a stepped area R2, a memory array area R3, a word line cutting area R4, and a peripheral area R5. Along the direction D2, each block B includes a first area A1, a second area A2, a third area A3, and a fourth area A4.

The three-dimensional memory device 100 includes a plurality of source line conductor walls (source line slit) 118 and a selective source line cut wall (Selective Source Line cut slit) 107 extending along the direction D1. There are some source line conductor walls (source line slit) 118 between the fourth area A4 and the first area A1 of two adjacent blocks B, extending from the step area R2 to the word line cutting area R4. There are other source line conductor walls 118 between the second area A2 and the third area A3 of each block B, extending from the memory array area R3 to the word line cutting area R4. The selection source line cutting wall 107 is located between the first area A1 and the second area A2 and between the third area A3 and the second area A4 of each block B.

In the disclosed embodiment, the word line cut region R4 and the peripheral region R5 of the three-dimensional memory device 100 have a stepped structure SC4. The ladder structure SC4 includes a portion P3 and a portion P4. The portion P3 and the portion P4 are located in the word line cutting region R4 and the peripheral region R5 respectively, and are separated from each other by the dielectric layer 103 . Thereby, a plurality of word lines between two adjacent blocks B can be separated from each other.

The three-dimensional memory device 100 can be formed with reference to the manufacturing method shown in FIGS. 2A to 2P , but the present invention is not limited thereto.

Referring to FIG. 2A , an element layer 20 and a metal interconnection structure 30 are sequentially formed on a substrate 10 . The substrate 10 can be a semiconductor substrate, such as a silicon-containing substrate. The device layer 20 may include active devices or passive devices. Active components such as transistors, two polar body etc. Passive components are, for example, capacitors, inductors, and the like. The transistor can be an N-type metal oxide semiconductor (NMOS) transistor, a P-type metal oxide semiconductor (PMOS) transistor or a complementary metal oxide semiconductor device (CMOS).

The metal interconnect structure 30 may include a multilayer dielectric layer 32 and a metal interconnect 33 formed in the multilayer dielectric layer 32 . The metal interconnection 33 includes a plurality of plugs 34 and a plurality of wires 36 and the like. The dielectric layer 32 separates adjacent conductive lines 36 . The wires 36 can be connected by plugs 34 , and the wires 36 can be connected to the device layer 20 by the plugs 34 .

Referring to FIG. 2A , a stack structure 90 is formed on the metal interconnection structure 30 . The stack structure 90 includes a plurality of insulating layers 92 and a plurality of conductive layers 94 stacked alternately. In one embodiment, the material of the insulating layer 92 includes silicon oxide, and the material of the conductive layer 94 includes doped polysilicon.

Referring to FIG. 1 and FIG. 2A , the stacked structure 90 is patterned to form a groove 111 , and a dielectric layer 95 (such as silicon oxide) is filled in the trench 111 . A stack structure 101 is formed on the stack structure 90 . The stack structure 101 includes a plurality of insulating layers 102 and a plurality of sacrificial layers 104 stacked alternately. The insulating layer 102 includes top insulating layers 102T, 102 ₁₄ , 102 ₁₃ , 102 ₁₂ , 102 ₁₁ , 102 10 , 102 ₉ , _{102 8} , 102 ₇ , 102 ₆ , 102 ₅ , 102 ₄ , 102 ₃ , 102 ₂ , 102 ₁ . The sacrificial layer 104 includes 104 ₁₄ , 104 ₁₃ , 104 ₁₂ , 104 ₁₁ , 104 10 , 104 ₉ , 104 ₈ , 104 ₇ , 104 ₆ , 104 ₅ , 104 ₄ , 104 ₃ , 104 _{2 ,} 104 ₁ . The insulating layer 102 and the sacrificial layer 104 can also be referred to as a first insulating layer 102 and a second insulating layer 104 respectively. In one embodiment, the material of the insulating layer 102 includes silicon oxide, and the material of the sacrificial layer 104 includes silicon nitride. Afterwards, a stop layer 105 is formed on the stacked structure 101 . The material of the stop layer 105 is different from that of the insulating layer 102 and the sacrificial layer 104 , such as polysilicon. In one embodiment, the stack structure 101 and the stop layer 105 are located on the peripheral region R1 , the step region R2 , the memory array region R3 , the word line cutting region R4 and the peripheral region R5 of each block B.

2B to 2K, the sacrificial layer 104 and the insulating layer 102 of the stacked structure 101 of the peripheral region R1, the stepped region R2, the word line cutting region R4 and the peripheral region R5 are patterned to form the stepped structures SC1, SC2, respectively. SC3 and SC4, as shown in Figures 2B to 2K. In some embodiments, the stepped structures SC1 , SC2 , SC3 and SC4 are formed through a four-stage patterning process, but the invention is not limited thereto. The patterning process of the first stage T1 is illustrated in FIGS. 2B to 2D . The patterning process of the second stage T2 is illustrated in FIGS. 2E to 2I. The third stage T3 of the patterning process is illustrated in FIG. 2J . The patterning process of the fourth stage T4 is illustrated in FIG. 2K.

Referring to FIG. 2B , the stop layer 105 is patterned to form openings OP1 , OP2 , OP3 and OP4 . The opening OP1 exposes the top insulating layer 102T of the stacked structure 101 of the peripheral region R1 and the stepped region R2, the opening OP2 exposes the top insulating layer 102T of the stacked structure 101 of the stepped region R2, and the opening OP3 exposes the top insulating layer 102 of the stacked structure 101 of the stepped region R2. In the top insulating layer 102T, the opening OP4 exposes the top insulating layer 102T of the stacked structure 101 of the word line cutting region R4 and the peripheral region R5.

Referring to FIG. 2B , the patterning process of the first stage T1 is performed. A mask layer PR1 is formed on the stopper layer 105 and the top insulating layer 102T. The mask layer PR1 is, for example, a patterned photoresist layer. The mask layer PR1 has openings OP11 , OP12 , OP13 , OP14 which are smaller than the openings OP1 , OP2 , OP3 and OP4 respectively. Next, an etching process is performed by using the mask layer PR1 as a mask to pattern the stack structure 101 , so as to transfer the patterns of the openings OP11 , OP12 , OP13 , and OP14 to the top insulating layer 102T and the sacrificial layer 104 ₁₄ .

Referring to FIG. 2C , the mask layer PR1 is trimmed to form the mask layer PR1 ′. The mask layer PR1' has openings OP21, OP22, OP23, and OP24, which are respectively larger than the openings OP11, OP12, OP13, and OP14, and smaller than the openings OP1, OP2, OP3, and OP4, exposing the top insulating layer 102T and the top insulating layer 102 ₁₄ and the top insulating layer 102T and the sidewalls of the sacrificial layer 104 ₁₄ .

2D, with the mask layer PR1' and the top insulating layer 102T having the openings OP11, OP12, OP13, OP14 and the sacrificial layer ₁₀₄₁₄ as the mask, an etching process is performed to pattern the stacked structure 101, thereby opening The patterns of OP21 , OP22 , OP23 and OP24 are transferred to the top insulating layer 102T and the sacrificial layer 104 ₁₄ , and the patterns of the openings OP11 , OP12 , OP13 , OP14 are transferred to the insulating layer 102 ₁₄ and the sacrificial layer 104 ₁₃ .

Referring to FIG. 2E, the mask layer PR1' is removed, and then the patterning process of the second stage T2 is performed. A mask layer PR2 is formed on the stop layer 105 and the stack structure 101 . The mask layer PR2 is, for example, a patterned photoresist layer. The mask layer PR2 has openings OP31 , OP32 , OP33 and OP34 . The openings OP31 , OP32 , OP33 are smaller than the openings OP11 , OP12 , OP13 respectively, and the opening OP34 is equal in size to the opening OP14 and aligned with the opening OP14 .

Referring to FIG. 2F, the etching process is performed with the mask layer PR2 as a mask to pattern the stacked structure 101, thereby transferring the patterns of the openings OP31, OP32, OP33 and OP34 to the insulating layers _102-13 and the sacrificial layers _104-12. .

Referring to FIG. 2G, the mask layer PR2 is trimmed to form a mask layer PR2'. The mask layer PR2' has openings OP41, OP42 and OP43 which are respectively larger than the openings OP31, OP32 and OP33 and smaller than the openings OP11, OP12 and OP13. The opening OP41 is larger than the openings OP14 and OP34 and equal to the opening OP24. The openings OP41 , OP42 and OP43 respectively expose the top surfaces of the insulating layers 102 ₁₃ and 102 ₁₂ and the sidewalls of the insulating layers 102 ₁₃ and the sacrificial layer 104 ₁₂ . The opening OP44 exposes the top surfaces of the insulating layers 102 ₁₄ , 102 ₁₂ and the sidewalls of the top insulating layer 102T, the insulating layers 102 ₁₄ , 102 ₁₃ and the sacrificial layers 104 ₁₄ , 104 ₁₃ , 104 ₁₂ .

Please refer to FIG. 2H, with mask layer PR2′, insulating layers 102 ₁₃ with openings OP31, OP32, OP33 and sacrificial layers 104 ₁₂ and insulating layers 102 ₁₄ with opening OP14 and sacrificial layers 104 ₁₃ as masks, the stacked structure 101 patterned. The patterns of the openings OP41 , OP42 and OP43 are transferred to the insulating layer 102 ₁₃ and the sacrificial layer 104 ₁₂ . The pattern of the opening OP44 is transferred to the insulating layer 102 ₁₄ and the sacrificial layer 104 ₁₃ . The patterns of the openings OP31 , OP32 , OP33 and the opening OP14 are transferred to the insulating layer 102 ₁₂ and the sacrificial layer 104 ₁₁ .

Referring to FIG. 2I, the mask layer PR2' is removed. So far, the transitional stepped structures TSC1 , TSC2 , the stepped structure SC3 and the transitional stepped structure TSC4 are formed.

Referring to FIGS. 1 and 2J , the patterning process of the third stage T3 is performed. A mask layer (not shown) is formed, and a selective etching process is performed on the transitional stepped structures TSC1, TSC2, and TSC4 to form the transitional stepped structure TSC1', the stepped structure SC2, and the transitional stepped structure TSC4'. The mask layer is then removed.

Referring to FIGS. 1 and 2K , the patterning process of the fourth stage T4 is performed. A mask layer (not shown) is formed, and a selective etching process is performed on the transitional stepped structures TSC1' and TSC4' to form the stepped structures SC1 and SC4. The stepped structure SC1 is located in the peripheral region R1 and the stepped region R2. The stepped structures SC2, SC3 are located in the stepped region R2. The stepped structure SC4 is located in the word line cut region R4 and the peripheral region R5. The mask layer is then removed.

The side profiles of the stepped structures SC1 , SC2 , SC3 , and SC4 are approximately symmetrical. The stepped structures SC1 and SC4 extend toward the substrate 10 until the insulating layer 102 ₁ is exposed. Therefore, the depth H1 of the stair structure SC1 is greater than the depth H2 of the stair structure SC2. The depth H2 of the stepped structure SC2 is greater than the depth H3 of the stepped structure SC3. The depth H4 of the stepped structure SC4 is equal to the depth H1 of the stepped structure SC1. However, the number of steps in the stepped structure SC4 is smaller than the number of steps in the stepped structure SC1. For example, in FIG. 2K , the number of steps in the stepped structure SC4 is 4, and the number of steps in the stepped structure SC1 is 6. The height of the first step of the stepped structure SC4 is the sum of the heights of the first step and the second step of the stepped structure SC1. The height of the second step of the stepped structure SC4 is the sum of the heights of the third and fourth steps of the stepped structure SC1. The height of the third step of the stepped structure SC4 is equal to the height of the fifth step of the stepped structure SC1. The height of the fourth step of the stepped structure SC4 is equal to the height of the sixth step of the stepped structure SC1.

In addition, the ladder structure SC1 includes parts P1 and P2; the ladder structure SC4 includes parts P3 and P4. The part P1 is located in the peripheral area R1; the part P2 is located in the stepped area R2. Part P1 and part P2 are separated from each other. The part P3 is located in the word line cutting area R4; the part P4 is located in the peripheral area R5. Part P3 and part P4 are separated from each other.

Please refer to FIGS. 1 and 2K. Furthermore, the portion P2 of the stepped structure SC1, the stepped structures SC2, SC3, and the portion P3 of the stepped structure SC4 are located in the first area A1, the second area A2, and the second area A2 of the stepped area R2 of each block B. The third area A3 and the fourth area A4. In the memory array region R3, the stop layer 105 and the stacked structures 101 and 90 are not patterned, therefore, no ladder structure is formed.

Referring to FIG. 2L , a dielectric layer 103 is formed on the substrate 10 to cover the stepped structures SC1 , SC2 , SC3 and SC4 . The dielectric layer 103 has a reverse ladder structure. The material of the dielectric layer 103 is, for example, silicon oxide. The method of forming the dielectric layer 103 is, for example, forming a dielectric material layer to fill the covering step structures SC1 , SC2 , SC3 and SC4 and the stop layer 105 . Then use the stop layer 105 as a stop layer to perform a planarization process, such as a chemical mechanical polishing process, to remove the dielectric above the stop layer 105. material layer.

Referring to FIG. 2M , the stop layer 105 is removed. An insulating cap layer 115 is formed above the stack structure 101 . In one embodiment, the material of the insulating cap layer 115 includes silicon oxide. Afterwards, a patterning process is performed to remove part of the insulating cap layer 115, part of the stacked structure 101 and part of the stacked structure 90 in the memory array region R3 to form a part of the insulating cap layer 115, the stacked structure 101 and the stacked structure 90. or a plurality of openings 106 . In one embodiment, the opening 106 may have slightly sloped sidewalls, as shown in FIG. 2M . In another embodiment, opening 106 may have substantially vertical sidewalls (not shown). In one embodiment, the opening 106 is also called a vertical channel (VC) hole. Vertical channel pillars CP are then formed in the openings 106 . The vertical channel pillar CP can be formed by the method described below.

Referring to FIG. 2M , a charge storage structure 108 is formed on the sidewall of the opening 106 . The charge storage structure 108 is in contact with the insulating capping layer 115 , the insulating layer 102 , the sacrificial layer 104 , the insulating layer 92 and the conductive layer 94 . In one embodiment, the charge storage structure 108 is an oxide/nitride/oxide (ONO) composite layer. In one embodiment, the charge storage structure 108 is formed on the sidewall of the opening 106 in the form of a spacer, and the bottom surface of the opening 106 is exposed.

Then, referring to FIG. 2M , a channel layer 110 is formed on the charge storage structure 108 . In one embodiment, the material of the channel layer 110 includes polysilicon. In one embodiment, the channel layer 110 covers the charge storage structure 108 on the sidewall of the opening 106 , and also covers the channel layer 110 on the bottom of the opening 106 . Next, an insulating post 112 is formed at the lower portion of the opening 106 . In one embodiment, the material of the insulating pillar 112 includes silicon oxide. Afterwards, a conductive plug 114 is formed on the upper portion of the opening 106 , and the conductive plug 114 is in contact with the channel layer 110 . In one embodiment, the material of the conductive plug 114 includes polysilicon. The channel layer 110 and the conductor plug 114 may be collectively referred to as a vertical channel column CP. The charge storage structure 108 surrounds the vertical outer surface of the vertical channel pillar CP.

In some embodiments, when the opening 106, the charge storage structure 108, and the vertical channel pillar CP are formed, the support structures PL1, PL2, PL3, and PL4 are also formed in the step region R2 and the word line cutting region R4 at the same time, so as to avoid the step structure The portion P2 of SC1 , the stepped structures SC2 , SC3 and the portion P3 of the stepped structure SC4 collapse during the subsequent removal of the sacrificial layer 104 . The supporting structures PL1 , PL2 , PL3 and PL4 may respectively have the same structure as the combined structure of the charge storage structure 108 and the vertical channel pillar CP, but the invention is not limited thereto. In other embodiments, the support structures PL1 , PL2 , PL3 and PL4 may be formed separately, and their structures may be different from the combined structure of the charge storage structure 108 and the vertical channel pillar CP. In this embodiment, the sacrificial layer 104 of the portion P1 of the stepped structure SC1, the portion P4 of the stepped structure SC4, and the second region A2 and the third region A3 of the stepped region R2 will not be removed in the subsequent process. Therefore, There is no support structure formed in the portion P1 of the stepped structure SC1 , the portion P4 of the stepped structure SC4 , and the second area A2 and the third area A3 of the stepped area R2 .

Referring to FIGS. 1 and 2N, a patterning process is performed to remove the insulating cap layer 115 between two adjacent blocks B, for example, between the fourth region A4 of the block B1 and the first region A1 of the block B2. , the partial stack structure 101 and the partial stack structure 90 to form a plurality of trenches 116 passing through the insulating cap layer 115 and the stack structure 101 and passing through the partial stack structure 90 . In one embodiment, the trench 116 may have substantially vertical sidewalls, as shown in FIG. 2N . In another embodiment, trench 116 may have slightly sloped sidewalls (not shown). The trench 116 exposes the sidewalls of the insulating cap layer 115 , the sacrificial layer 104 , the insulating layer 102 , the insulating layer 92 and the conductive layer 94 .

Please refer to Figures 1 and 2N, after that, a selective etching process is performed to make the etching The agent flows through the first area A1 and the fourth area A4 on both sides through the ditch 116 , and then flows through the second area A2 and the third area A3 . Thereby, a plurality of horizontal openings 121 are formed by removing the sacrificial layer 104 of the portion P2 of the stepped structure SC1 , the stepped structures SC2 , SC3 , and the portion P3 of the stepped structure SC4 . The horizontal opening 121 exposes part of the sidewalls of the charge storage structure 108 and the insulating layer 102 in the memory array region R3 , and exposes part of the sidewalls of the supporting structures PL1 , PL2 , PL3 and PL4 . During this process, due to the setting of the supporting structures PL1 , PL2 , PL3 and PL4 , the part P2 of the stepped structure SC1 , the part P3 of the stepped structures SC2 , SC3 and the part P3 of the stepped structure SC4 can be avoided from collapsing. The selective etching process can be an isotropic etching process, such as a wet etching process. The etchant used in the wet etching process is, for example, hot phosphoric acid. The etchant flows into the step region R2, the memory array region R3, the first region A1 and the fourth region A4 of the word line cutting region R4 of each block B through the trench 116, and then extends to the memory array region R3 and the word line cutting region The second area A2 and the third area A3 of the area R4.

1 and 2N, the dielectric layer 103 separates the portions P1 and P2 of the stepped structure SC1 from each other, and separates the portions P3 and P4 of the stepped structure SC4 from each other. Therefore, the sacrificial layer 104 of the portion P1 of the stepped structure SC1 and the portion P4 of the stepped structure SC4 is blocked by the dielectric layer 103 and cannot be removed, and thus remains. Furthermore, in some embodiments, before the selective etching process is performed to remove the sacrificial layer 104 , an insulating wall 113 is formed around the second region A2 and the third region A3 of the stepped region R2 . Therefore, after the etchant flows through the first region A1 and the fourth region A4 on both sides through the trench 116, the etchant cannot flow through the second region A2 and the third region of the step region R2 due to the barrier of the insulating wall 113. A3, so the second zone A2 of the stepped zone R2 is related to The sacrificial layer 104 of the third area A3 is not removed, but remains.

Referring to FIG. 2N , then, a conductive layer is formed in the trench 116 and the horizontal opening 121 . The conductive layer includes, for example, a barrier layer 122 and a metal layer 124 . In one embodiment, the material of the barrier layer 122 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the material of the metal layer 124 includes tungsten (W ). The conductive layer in the horizontal opening 121 serves as the gate layer 126 .

Referring to FIG. 2N , the sacrificial layer 104 of the portion P2 of the stepped structure SC1 , the stepped structures SC2 , SC3 , and the portion P3 of the stepped structure SC4 is replaced by a gate layer 126 . The sacrificial layer 104 of the portion P1 of the stepped structure SC1 and the portion P4 of the stepped structure SC4 is retained. Parts P1 and P2 of the stepped structure SC1 have symmetrical side profiles, but are formed by stacking different material layers. Part P1 of the stepped structure SC1 is formed by stacking the insulating layer 102 and the sacrificial layer 104 ; part P2 of the stepped structure SC1 is formed by stacking the insulating layer 102 and the gate layer 126 . The stepped structures SC2 and SC3 are respectively formed by stacking the insulating layer 102 and the gate layer 126 , and each have a symmetrical structure. Parts P3 and P4 of the stepped structure SC4 have symmetrical side profiles, but are formed by stacking different material layers. Part P3 of the stepped structure SC4 is formed by stacking the insulating layer 102 and the gate layer 126 ; part P4 of the stepped structure SC4 is formed by stacking the insulating layer 102 and the sacrificial layer 104 . In some embodiments, the portion P2 of the stair structure SC1 in the stair region R2 and the stair structures SC2 and SC3 may be collectively referred to as the stair structure SC. The part P2 of the stepped structure SC1 and the stepped structures SC2 and SC3 may be referred to as sub-stepped structures of the stepped structure SC, respectively. In this embodiment, three sub-ladder structures (such as P2, SC2, SC3) are used for illustration, however, the present invention is not limited thereto, and the ladder structure SCs may include more or fewer sub-echelons.

Referring to FIG. 2N , next, a spacer 117 is formed on the sidewall of the trench 116 . The spacer 117 includes a dielectric material different from that of the insulating layer 102 , such as silicon nitride or a silicon oxide/silicon nitride/silicon oxide composite layer. Afterwards, the conductor layer 94 in the middle of the stack structure 90 in the memory array region R3 is removed, and the insulating layer 92 above and below the conductor layer 94 is removed to form horizontal openings (not shown) in the stack structure 90 . Then fill the conductive layer in the trench 116 and the horizontal opening. The conductive layer in the horizontal opening together with the conductive layer 94 above and below form the source line 120 .

Referring to FIG. 2O , a conductive layer is formed in the trench 116 to form a source line slit 118 for conducting current from the source line 120 . The spacer 117 isolates the source line conductor wall 118 from contacting the gate layer 126 .

Referring to FIGS. 1 and 2P , thereafter, contact holes C1 and C5 are formed in the peripheral regions R1 and R5 to be electrically connected to the conductor layer 36 of the metal interconnection structure 30 . A plurality of contact windows C2 are formed in the first region A1 and the fourth region A4 of the stepped region R2 to be connected to the end of the gate layer 126 . A plurality of contact windows (not shown) are formed in the second region A2 and the third region A3 of the stepped region R2 to be electrically connected to the conductor layer 36 of the metal interconnection structure 30 . A plurality of contact windows C3 are formed in the memory array region R3 to be electrically connected to the conductor plugs 114 of the vertical channel pillars CP. The contact windows C1 , C2 , C3 and C5 can be formed simultaneously or separately. In addition, the contact windows C1 , C2 , C3 and C5 may respectively include one or more plugs. A plurality of plugs contacting the windows C1 , C2 , C3 and C5 can be formed simultaneously or separately. In one embodiment, each of the contacts C1 , C2 , C3 and C5 may include a barrier layer and a conductor layer. The material of the barrier layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the material of the conductor layer is, for example, tungsten (W). Furthermore, in this embodiment, as shown in FIG. 2P, No contact window is formed in the word line cutting region R4, that is, the word line cutting region R4 does not include a contact window.

In some embodiments, since the portion P1 of the stepped structure SC1 will not be electrically connected to the contact C1, the portion P3 of the stepped structure SC4 will not form a contact, and the portion P4 of the stepped structure SC4 will not be electrically connected to the contact C5. , the part P1 of the stair structure SC1 and the stair structure SC4 may also be referred to as a dummy stair structure.

Referring to FIGS. 1 and 2P , a metal interconnection structure 40 is formed. The metal interconnection structure 40 may include a multilayer dielectric layer 42 and a plurality of plugs 44 and a plurality of wires 46 formed in the multilayer dielectric layer 42 . A dielectric layer 42 separates adjacent conductive lines 46 . The wires 46 can be connected by plugs 44 , and the wires 46 can be electrically connected with the contact windows C1 , C2 , C3 and C5 . The wire 46 connected to the contact window C3 can be used as a bit line BL.

Thereafter, follow-up related processes are carried out to complete the production of the memory device.

1, 2P and 3, in some embodiments of the present invention, in each block B, the part P3 of the stepped structure SC4 in the word line cutting area R4 and the portion of the stepped structure SC4 in the peripheral area R5 Portions P4 are separated from each other and completely separated by the dielectric layer 103, as shown in FIG. 2P. Parts P3 of the stepped structure SC4 of two adjacent blocks B (for example, blocks B2 and B3 ) are also separated from each other and completely separated by the dielectric layer 103 . Therefore, the gate layers (multiple word lines) 126 of the same level in two adjacent blocks B (for example, blocks B2 and B3 ) are separated from each other and separated by the dielectric layer 103 , as shown in FIG. 3 .

1, 2K and 2L, in the above embodiments, the ladder structure SC4 of each block B extends continuously from the first area A1 of the word line cutting area R4 to the fourth area A4. Therefore, the portion P3 of the stepped structure SC4 and the portion P4 of the stepped structure SC4 in the peripheral region R5 are separated from each other, and the trench 119 formed between them will be separated from each other. Block B1 extends continuously to block B4. Therefore, the dielectric layer 103 between the word line cutting region R4 and the peripheral region R5 is also filled into the trench 119 and extends continuously from the block B1 to the block B4.

4A and 4B, in some other embodiments, the step structure SC4 of the word line cutting region R4 and the peripheral region R5 does not extend continuously from the first region A1 to the fourth region A4, but includes a plurality of island-like steps Structures SC4 ₁ , SC4 ₂ and SC4 ₃ . The island ladder structures SC4 ₁ , SC4 ₂ and SC4 ₃ are respectively formed at ends of source line slits 118 between two adjacent blocks B. As shown in FIG. That is, the island-shaped stepped structure _SC41 is formed in the fourth area A4 of the block B1 and the first area A1 of the block B2, and the island-shaped stepped structure _SC42 is formed in the fourth area A4 of the block B2 and the first area A1 of the block B3. The first area A1 and the island-like stepped structure _SC43 are formed in the fourth area A4 of the block B3 and the first area A1 of the block B4. In some embodiments, the island ladder structures SC4 ₁ , SC4 ₂ and SC4 ₃ are formed through a patterning process of four stages (ie T1 , T2 , T3 and T4 ), but the invention is not limited thereto.

Therefore, the dielectric layer 103 of each block B does not continuously extend from the first region A1 of the word line cutting region R4 to the fourth region A4, but includes island-shaped dielectric layers 103 ₁ , 103 ₂ , 103 separated from each other. ₃ . The island-shaped dielectric layers 103 ₁ , 103 ₂ , 103 ₃ are respectively formed on the sides of the source line slit 118 (ie, 118 ₁ , 118 ₂ , 118 ₃ ) between two adjacent blocks B. end, as shown in Figure 4A. That is, the dielectric layer 103 is formed between two adjacent blocks B. As shown in FIG. For example, the island-shaped dielectric layer ₁₀₃₁ is formed in the fourth area A4 of the block B1 and the first area A1 of the block B2, and the island-shaped dielectric layer ₁₀₃₂ is formed in the fourth area A4 and the area of the block B2. The first area A1 of the block B3 and the island-shaped dielectric layer ₁₀₃₃ are formed in the fourth area A4 of the block B3 and the first area A1 of the block B4.

Parts P3 of the sub-step structures SC4 ₁ , SC4 ₂ and SC4 ₃ on the side of the island-shaped dielectric layers 103 ₁ , 103 ₂ , 103 ₃ close to the memory array region R3 are formed by stacking the insulating layer 102 and the gate layer 126 . Parts P4 of the sub-step structures SC4 ₁ , SC4 ₂ and SC4 ₃ on the side of the island-shaped dielectric layers 103 ₁ , 103 ₂ , 103 ₃ away from the memory array region R3 are formed by stacking the insulating layer 102 and the sacrificial layer 104 . Other parts of the ladder structures SC4 ₁ , SC4 ₂ and SC4 ₃ can be formed by stacking the insulating layer 102 and the gate layer 126 , or stacking the insulating layer 102 and the sacrificial layer 104 , or a combination thereof.

1 and 4A, in the above embodiments, the width W4 of the word line cutting region R4 is quite small, for example, it is smaller than the width W1 of the peripheral region R1, the width W2 of the step region R2 or the width W3 of the memory array region R3 .

Referring to FIGS. 5A and 5B , in another embodiment, the width W4 of the word line cutting region R4 may be equal to the width W2 of the step region R2 . The stepped structure SC4 in the word line cutting region R4 and the peripheral region R5 may include a plurality of sub-stepped structures SC4a, SC4b, SC4c. Sub-step structure SC4a may have a similar width and side profile to step structure SC3, Sub-step structure SC4b may have a similar width and side profile to step structure SC2, Sub-step structure SC4c may have a similar width and side profile to step structure SC1 . The sub-ladder structures SC4 a and SC4 b are formed by stacking the insulating layer 102 and the gate layer 126 . The sub-step structure SC4c includes parts P3 and P4 separated from each other. The part P3 of the sub-step structure SC4c is formed by stacking the insulating layer 102 and the gate layer 126 ; the part P4 of the sub-step structure SC4c is formed by stacking the insulating layer 102 and the sacrificial layer 104 . In some embodiments, the sub-step structure SC4a is formed through the patterning process of the first stage T1 and the second stage T2; the sub-step structure SC4b is formed through the patterning process of the first stage T1, the second stage T2 and the third stage T3 The sub-step structure SC4c is formed through the patterning process of the first stage T1, the second stage T2, the third stage T3 and the fourth stage T4, but the present invention is not limited thereto.

The dielectric layer 103 between the portions P3 and P4 of the sub-step structure SC4c extends continuously from the block B1 to the block B4, so that the gate layers (word lines) 126 of adjacent blocks B are separated from each other, as shown in FIG. 5A shown.

Please refer to FIGS. 6A and 6B. In yet another embodiment, the stepped structure SC4 in the word line cutting region R4 and the peripheral region R5 may have the same width and similar width as the stepped structure SC1 in the peripheral region R1 and the stepped region R2. profile. Likewise, the stepped structure SC4 includes portions P3 and P4 separated from each other. Part P3 of the stepped structure SC4 is formed by stacking the insulating layer 102 and the gate layer 126 ; part P4 of the stepped structure SC4 is formed by stacking the insulating layer 102 and the sacrificial layer 104 . In some embodiments, the stepped structure SC4 is formed through a four-stage (ie T1 , T2 , T3 and T4 ) patterning process, but the invention is not limited thereto.

The dielectric layer 103 between the portions P3 and P4 of the stepped structure SC4 extends continuously from the block B1 to the block B4, so that the gate layers (word lines) 126 of adjacent blocks B are separated from each other, as shown in FIG. 6A Show.

7A and 7B, in yet another embodiment, the ladder structure SC4 in the word line cutting region R4 and the peripheral region R5 includes a plurality of sub-step structures SC4d, SC4e, SC4f. The widths of the sub-step structures SC4d, SC4e, SC4f are respectively smaller than the widths of the step structures SC3, SC2 and SC1. The sub-ladder structures SC4d and SC4e are respectively formed by stacking the insulating layer 102 and the gate layer 126 . The sub-step structure SC4f includes parts P3 and P4 separated from each other. Part P3 of the sub-step structure SC4f is formed by stacking the insulating layer 102 and the gate layer 126 ; part P4 of the step structure SC4f is formed by stacking the insulating layer 102 and the sacrificial layer 104 . In some embodiments, the sub-step structure SC4d is formed through the patterning process of the first stage T1 and the second stage T2; the sub-step structure SC4e is formed through the first stage T1, the second stage T2 and the third stage T3 The patterning process is formed; the sub-step structure SC4f is formed through the patterning process of the first stage T1, the second stage T2, the third stage T3 and the fourth stage T4, but the present invention is not limited thereto.

The dielectric layer 103 between the portions P3 and P4 of the stepped structure SC4f continuously extends from the block B1 to the block B4, so that the gate layers (word lines) 126 of adjacent blocks B are separated from each other, as shown in FIG. 7A Show.

In this embodiment, in the embodiment of the present invention, the stacked structure between two adjacent blocks is patterned into a ladder structure of two parts separated from each other, and a dielectric layer with a reverse ladder structure is provided between them, so as to The multiple word lines of different blocks are separated from each other to avoid short circuit between the multiple word lines of two blocks. Furthermore, since the stepped structure between two adjacent blocks can be formed simultaneously with the stepped structure in the stepped area, it can be integrated with existing manufacturing processes without increasing manufacturing costs and burdens.

10: Base

20: Component layer

30: Metal interconnection structure

32: Dielectric layer

34: plug

36: Wire

90, 101: stack structure

92, 102 ₁₄ , 102 ₁₃ , 102 ₁₂ , 102 ₁₁ , 102 ₁₀ , 102 9 , 102 ₈ , 102 ₇ , 102 ₆ , 102 ₅ , 102 ₄ , 102 ₃ , 102 _{2 ,} 102 ₁ : insulating layer

94: conductor layer

102T: top insulating layer

103: Dielectric layer

104 ₁₄ , 104 ₁₃ , 104 ₁₂ , 104 ₁₁ , 104 ₁₀ , 104 ₉ , 104 8 , 104 ₇ , 104 ₆ , 104 ₅ , 104 ₄ , 104 ₃ , 104 _{2 ,} 104 ₁ : sacrificial layer

105: stop layer

119: Ditch

P1, P2, P3, P4: part

SC1, SC2, SC3, SC4: ladder structure

I-I, II-II: Tangent

R1, R5: Surrounding area

R2: Ladder area

R3: memory array area

R4: character line cutting area

Claims (10)

A memory element, comprising: a base, including a plurality of blocks, each block including a step area, a memory array area and a word line cutting area, wherein the memory array area is located between the step area and the word line Between the cutting areas; a stack structure located on the substrate in the memory array area, wherein the stack structure includes a plurality of first insulating layers and a plurality of conductor layers alternately stacked on each other; a first ladder structure located in the memory array area on the substrate in the stepped region, wherein the first stepped structure includes a plurality of first insulating layers and a plurality of conductor layers stacked alternately; and the first part of the second stepped structure is located at the word line cut On the substrate in the area, wherein the first part of the second stepped structure includes a plurality of first insulating layers and a plurality of conductor layers stacked alternately with each other, and two of the adjacent two blocks The two first parts of the second ladder structure are separated from each other, wherein the word line cutting area does not include a contact window. The memory device according to claim 1, wherein the second ladder structure has multiple sets of sub-ladder structures located in the plurality of blocks. The memory device according to claim 1, wherein the second ladder structure includes a plurality of island-like ladder structures, and each island-like ladder structure is located between two adjacent blocks. The memory device according to claim 1, wherein the number of steps of the second ladder structure is smaller than the number of steps of the first ladder structure. The memory element according to claim 1, further comprising: a plurality of first contact windows respectively connected to the plurality of conductor layers of the first ladder structure; a plurality of first supporting pillars penetrating through the first ladder The plurality of first insulating layers and the plurality of conductor layers of the structure; and a plurality of second supporting pillars passing through the plurality of first insulating layers and the plurality of first insulating layers of the first part of the second stepped structure multiple conductor layers. The memory device according to claim 5, wherein: the substrate further includes a peripheral area, the word line cutting area is located between the memory array area and the peripheral area; and the second step structure of the second A portion located on the substrate in the peripheral region, wherein the second portion of the second stepped structure includes a plurality of first insulating layers and a plurality of second insulating layers alternately stacked on each other. The memory element according to claim 6, wherein the plurality of conductor layers of the first ladder structure connects the plurality of conductor layers of the stack structure and the first part of the second ladder structure The plurality of conductor layers are separated from the plurality of second insulating layers of the second portion of the second stepped structure, and the first portion of the second stepped structure is separated from the second The second portion of the ladder structure is separated by a dielectric layer having an inverted ladder structure, and the dielectric layer having an inverted ladder structure extends continuously in the plurality of blocks. A method for manufacturing a memory element, comprising: providing a substrate, including a plurality of blocks, each block including a stepped area, a memory array area and word line cutting area, wherein the memory array area is located between the step area and the word line cutting area; in the step area, the memory array area and the word line cutting area A stacked structure is formed on the substrate, wherein the stacked structure includes a plurality of first insulating layers and a plurality of second insulating layers alternately stacked on each other; the stacked structure in the step region is patterned to form a first Ladder structure: pattern the stacked structure in the word line cutting area to form the first part of the second ladder structure, so that the two second ladder structures of the two adjacent blocks A part is separated from each other; a replacement process is performed, and all of the stacked structure in the memory array area, the first ladder structure in the ladder area, and the second ladder structure in the word line cutting area a plurality of second insulating layers in the first part are replaced by a plurality of conductor layers; and a plurality of first contact windows are formed in the step region to connect with ends of the plurality of conductor layers, but not on the word line The cut area forms a contact window. The manufacturing method of the memory device as claimed in item 8, wherein the substrate further includes a peripheral area, the word line cutting area is located between the memory array area and the peripheral area, and the stack structure is further formed in on the substrate in the peripheral region, and when patterning the stacked structure in the stepped region, further includes patterning the stacked structure in the peripheral region to form the first The second portion of the second stepped structure, the second portion of the second stepped structure and the first portion of the second stepped structure are separated from each other. The manufacturing method of the memory device according to claim 9, further comprising forming an interlayer with a reverse ladder structure between the first part of the second ladder structure and the second part of the second ladder structure The electrical layer is used to separate the first parts of the two second ladder structures of two adjacent blocks from each other.

Images