TWI860857B - Memory device - Google Patents

Abstract

A memory device includes a stack structure, a first stop layer, a dielectric layer, at least one separation wall and a conductive plug. The stacked structure is located over a substrate. The stacked structure has an opening exposing a stepped structure of the stacked structure. The first stop layer covers the stepped structure and at least at least one portion of sidewalls of the opening. The dielectric layer fills the opening and covers the first stop layer. The separation wall extends through the dielectric layer and the first stop layer in the opening. The conductive plug extends through the dielectric layer and the first stop layer, and is electrically connected to the stepped structure. The memory device may be a 3D NAND flash memory with high capacity and high performance.

Description

Memory device

The present invention relates to a semiconductor device, and more particularly to a memory device.

Non-volatile memory devices (such as flash memory) have the advantage that the stored data will not disappear even after power failure. Therefore, they have become a type of memory device widely used in personal computers and other electronic devices.

The flash memory arrays commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of NAND flash memory is to connect each memory cell in series, its integration and area utilization are better than NOR flash memory, and it has been widely used in many electronic products. In addition, in order to further improve the integration of memory components, a three-dimensional NAND flash memory has been developed. However, there are still many challenges related to three-dimensional NAND flash memory.

For example, multiple word lines of a three-dimensional NAND flash memory are electrically connected via conductive plugs. However, since the conductive plugs have various depths, it is difficult to control the process, so that some conductive plugs cannot land on the word lines, or some conductive plugs pass through the word lines, resulting in short circuits with multiple word lines, thus causing poor process yield.

The present invention provides a memory device that can enable conductive plugs of various depths to land on a word line of a staircase structure and can improve the yield of the manufacturing process.

A memory element of an embodiment of the present invention includes a stacking structure, a first stop layer, a dielectric layer, at least one separation wall and a conductive plug. The stacking structure is located above the substrate, wherein the stacking structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately, and the stacking structure has an opening, exposing the step structure of the stacking structure. The first stop layer covers the step structure and at least a portion of the plurality of side walls of the opening. The dielectric layer is filled in the opening, covering the first stop layer. At least one separation wall extends through the dielectric layer and the first stop layer in the opening. The conductive plug extends through the dielectric layer and the first stop layer, and is electrically connected to the step structure.

A memory element of an embodiment of the present invention includes a substrate, a stacking structure, a first stop layer, a dielectric layer, at least one separation wall and a conductive plug. The stacking structure is located above the substrate, wherein the stacking structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately, and the stacking structure has an opening to expose the step structure of the stacking structure, wherein the opening includes a first sidewall, a second sidewall, a third sidewall, a fourth sidewall and a bottom. The second sidewall is connected to the first sidewall. The third sidewall is connected to the second sidewall, wherein the first sidewall is opposite to the third sidewall. The fourth sidewall is connected to the third sidewall, wherein the second sidewall is opposite to the fourth sidewall. The bottom is connected to the first side wall, the second side wall, the third side wall and the fourth side wall. The first stop layer includes a first portion and a second portion. The first portion covers the step structure. The second portion covers at least the first side wall and the third side wall. A dielectric layer is filled in the opening and covers the first stop layer. At least one partition wall extends through the dielectric layer in the opening and the first portion and the second portion of the first stop layer. A conductive plug extends through the dielectric layer and the first portion of the first stop layer and is electrically connected to the step structure.

Based on the above, the memory device of the embodiment of the present invention can enable conductive plugs of various depths to be landed on the word line of the staircase structure and can improve the yield of the process.

Figures 1D and 8D are top views of several memory devices at intermediate stages according to embodiments of the present invention. Figures 2R and 9E are schematic cross-sectional views of various memory devices according to embodiments of the present invention. Figures 3A and 3B and Figures 10A and 10B show conductive plugs of different depths.

Referring to FIG. 2R and FIG. 9E , the memory chips SM1 and SM2 of the embodiments of the present invention each include a memory array region ARR, a step region SCR, and a peripheral region PRR. The memory array region ARR includes a stacking structure SK2. The stacking structure SK2 includes a plurality of insulating layers 102 and a plurality of conductive layers 126 stacked alternately. The plurality of conductive layers 126 can serve as a plurality of word lines WL. A plurality of channel pillars VC extend through the stacking structure SK2. A plurality of charge storage structures 108 surround the vertical outer surfaces of the channel pillars VC. And are located between the plurality of conductive layers 126 and the plurality of channel pillars VC. A plurality of word lines WL, a plurality of channel pillars VC, and a plurality of charge storage structures 108 sandwiched therebetween form a plurality of memory cells MC. The plurality of memory cells MC form a memory array ARY. In other words, the stack structure SK2 has a memory array ARY.

2R and 9E, the peripheral region PRR includes a stacking structure SK1. The stacking structure SK1 includes a plurality of insulating layers 102 and a plurality of intermediate layers 104 stacked alternately. The step region SCR includes a plurality of step structures SC exposed by openings 105 or 105A, as shown in FIG. 2Q and FIG. 9D. In FIG. 2R and FIG. 9E, the step structure SC is reversed, and therefore can also be referred to as a reverse step structure RSC.

Referring to FIG. 2R and FIG. 9E , the memory chips SM1 and SM2 further include a plurality of conductive plugs COA’, COA, and through-holes TV. The conductive plug COA’ is located in the memory array region ARR, and electrically connects a plurality of channel pillars VC to the bit lines BL. The conductive plug COA is located in the ladder region SCR, and extends through the dielectric layer 107 in the opening 105, and electrically connects one of the plurality of conductive layers 126 (i.e., a plurality of word lines WL) of the ladder structure SC to the underlying internal connection structure 130. The through-hole TV is located in the peripheral region PRR, and electrically connects the conductive plug 46 and the wire 48 of the upper internal connection structure 40. The through-hole TV extends through the dielectric layer 107 in the opening 105 and electrically connects to the underlying internal connection structure 130. Since the conductive plugs COA are connected to the conductive layers 126 of multiple steps of the step structure SC with different heights, the multiple conductive plugs COA have various depths. For example, the conductive plugs COA in FIG. 3A or 10A are shallower in depth, and the conductive plugs COA in FIG. 3B or 10B are deeper in depth.

Referring to FIG. 2R and FIG. 9EB, the plurality of conductive plugs COA and the plurality of through-holes TV have different depths. In particular, the depths of the through-holes TV and some conductive plugs COA connected to lower steps are quite deep, which is very difficult to control in the manufacturing process. In the embodiment of the present invention, after the formation of the step structure SC, before the formation of the plurality of conductive plugs COA and the plurality of through-holes TV, the surface of the step structure SC is first covered with a liner 150 and stop layers 152 and 154 (as shown in FIG. 1D, FIG. 2D, FIG. 8D and FIG. 9E). As shown in FIG. 2R and FIG. 9E, the plurality of conductive plug holes OP1 and the plurality of through-hole openings OP2 of the plurality of conductive plugs COA and the plurality of through-holes TV are formed by a multi-stage etching process. In the multi-stage etching process, the stop layers 152 and 154 can be used as etching stop layers in the first stage etching process. The liner 150 can be used as an etching stop layer in the second stage etching process. Therefore, the embodiment of the present invention helps to form a plurality of conductive plug holes OP1 and a plurality of through-hole openings OP2 of various depths by providing the liner 150 and the stop layers 152 and 154. A more detailed method for manufacturing a memory device will be described in the subsequent description.

The present invention can be applied to memory devices of various structures. The following is a method for manufacturing a memory device with a CMOS-Bonded-Array (CbA) structure. However, the present invention is not limited thereto. The present invention can also be used for a memory device with a CMOS-Under-Array (CUA) structure.

FIG. 1A to FIG. 1D are top views of a method for manufacturing a memory element in an intermediate stage according to an embodiment of the present invention. FIG. 2A to FIG. 2R are schematic cross-sectional views of a method for manufacturing a memory element according to an embodiment of the present invention. For the sake of clarity, FIG. 1A and FIG. 1D are top views of lines III-III’ and IV-IV’ of the step region SCR in FIG. 2A and FIG. 2Q. FIG. 2A and FIG. 2Q are schematic cross-sectional views of the step region SCR (including cross-sections of lines I-I’ and II-II’ in two different directions D1 and D2 of FIG. 1A to FIG. 1D) and the memory array region ARR. Direction D1 is, for example, a direction parallel to the bit line. Direction D2 is, for example, a direction parallel to the word line. FIG. 2R is a schematic cross-sectional view of the stair region SCR, the memory array region ARR, and the peripheral region PRR.

2A , a substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon-containing substrate. An insulating layer 101 and a stop structure 103 are formed on the substrate 100. The insulating layer 101 is, for example, silicon oxide. The stop structure 103 is formed on the insulating layer 101. The stop structure 103 may include a plurality of insulating layers 92 and a plurality of conductive layers 94 alternately stacked on each other. The insulating layer 92 is, for example, silicon oxide, and the conductive layer 94 is, for example, polycrystalline silicon. An insulating structure 103a has been formed in the stop structure 103.

2A , a lower portion LP of a stacked structure (or first stacked structure) SK1 is formed on the surface of the stop structure 103. The lower portion LP of the stacked structure SK1 includes a plurality of insulating layers 102 and a plurality of intermediate layers 104 alternately stacked with each other. In some embodiments, the material of the insulating layer 102 includes silicon oxide, and the material of the intermediate layer 104 includes silicon nitride. The intermediate layer 104 can be used as a sacrificial layer, which will be partially removed in a subsequent process.

Referring to FIG. 2A , a plurality of dummy columns DVC are then formed to extend through the lower LP of the stacked structure SK1. The plurality of dummy columns DVC can be formed into an opening (not shown) by a single-stage lithography and etching process or a multi-stage lithography and etching process. The opening extends through the lower LP of the stacked structure SK1 to the stop structure 103, and even to the insulating layer 101. Then, a filling material (or self-alignment material) is filled into the opening to form it. The profile of the sidewall of the opening formed by the multi-stage lithography and etching process is, for example, in the shape of a bamboo node.

2A , an upper portion UP of a stacked structure SK1 is formed on a substrate 100. The upper portion UP of the stacked structure SK1 includes a plurality of insulating layers 102 and a plurality of intermediate layers 104 stacked on each other. The materials of the insulating layers 102 and the intermediate layers 104 of the upper portion UP of the stacked structure SK1 are the same as the materials of the insulating layers 102 and the intermediate layers 104 of the lower portion LP of the stacked structure SK1. Thereafter, a hard mask layer HM is formed on the upper portion UP of the stacked structure SK1. The hard mask layer HM is, for example, polycrystalline silicon.

Referring to FIG. 2B , the hard mask layer HM is then patterned. The hard mask layer HM is then used as a mask to pattern the middle layer 104 and the insulating layer 102 of the stacked structure SK1 to form an opening 105 and a step structure SC. In some embodiments, the opening 105 and the step structure SC can be formed by a multi-stage patterning process. The patterning process can include processes such as lithography, etching, and trimming.

FIG. 1A is a top view along lines III-III’ and IV-IV’ of FIG. 2B to FIG. 2D .

Referring to FIG. 1A and FIG. 2B , the opening 105 is, for example, rectangular. For example, the opening 105 has four side walls sw1, sw2, sw3, and sw4. The side wall sw1 is connected to the side wall sw2, the side wall sw2 is connected to the side wall sw3, the side wall sw3 is connected to the side wall sw4, and the side wall sw4 is connected to the side wall sw2. The side walls sw1 and sw3 are disposed opposite to each other, and the side walls sw2 and sw4 are disposed opposite to each other. The bottom ends of the side walls sw1, sw2, sw3, and sw4 are connected to the step structure SC at the bottom of the opening 105.

1A and 2B, a liner 150 and a stop layer 152 are formed on the hard mask layer HM and on the multiple steps S1-S10 of the step structure SC in the opening 105. The liner 150 is a conformal layer, covering the upper surface of the hard mask layer HM and the surface of the step structure SC at the bottom of the opening 105, as well as the sidewalls sw1, sw2, sw3 and sw4. The stop layer 152 covers the surface of the liner 150. The material of the liner 150 includes silicon oxide. The material of the stop layer 152 can be the same as or similar to the material of the intermediate layer 104. The material of the stop layer 152 includes silicon nitride. In the embodiment of the present invention, the thickness T1 of the stop layer 152 is greater than the thickness T2 of the intermediate layer 104. For example, the thickness T1 is more than twice the thickness T2.

2C , a dielectric material (not shown) is formed on the stacked structure SK1 and fills the opening 105 . The dielectric material is, for example, silicon oxide. A planarization process is then performed, such as a chemical mechanical polishing process, using the hard mask layer HM as a polishing stop layer to remove excess insulating material, so as to form a dielectric layer 107 in the opening 105 .

2D , the hard mask layer HM and the liner layer 150 and the stop layer 152 thereon are removed, leaving the liner layer 150 and the stop layer 152 filling the opening 105 .

1A and 2C, the liner 150 remaining in the opening 105 includes a plurality of portions 150a and 150b. The stop layer 152 remaining in the opening 105 includes a plurality of portions 152a and 152b. The portions 150a and 152a cover the surface of the step structure SC. The portions 150b and 152b cover the sidewall of the stacking structure SK1 exposed in the opening 105. For simplicity, the plurality of portions 150a of the liner 150 are also referred to as liner 150a. The plurality of portions 150b of the liner 150 are also referred to as liner 150b. The plurality of portions 152a of the stop layer 152 are also referred to as stop layer 152a. The portions 152b of the stop layer 152 are also referred to as stop layers 152b.

Referring to FIG. 2D and FIG. 2E , a patterning process is then performed to remove a portion of the stacked structure SK1 to form an opening (not shown) and expose the dummy column DVC. Next, the dummy column DVC exposed by the opening is removed to form one or more openings 106 extending through the stacked structure SK1. In one embodiment, the opening 106 may have slightly inclined side walls. In another embodiment, the opening 106 may have substantially vertical side walls (not shown). In one embodiment, the opening 106 is also referred to as a vertical channel hole. In one embodiment, the opening 106 can be formed by a single-stage lithography and etching process. In another embodiment, the opening 106 is formed by multiple-stage lithography and etching processes. The profile of the sidewall of the opening 106 formed by multiple stages of lithography and etching processes is, for example, a bamboo-node shape.

Referring to FIG. 2E , a charge storage structure 108 is then formed in the opening 106. The charge storage structure 108 contacts the insulating layer 102 and the intermediate layer 104. In one embodiment, the charge storage structure 108 is an oxide/nitride/oxide (ONO) composite layer. The charge storage structure 108 is, for example, a conformal layer formed on the sidewalls and bottom of the opening 106. A channel column VC is then formed in the remaining space of the opening 106. The channel column VC can be formed by the following method.

Continuing with reference to FIG. 2E , a channel layer 110 is formed on the inner sidewall and bottom surface of the charge storage structure 108. In one embodiment, the material of the channel layer 110 includes undoped polysilicon. Next, an insulating column (or core insulating column) 112 is formed on the inner surface of the channel layer 110. In one embodiment, the material of the insulating column 112 includes silicon oxide. Thereafter, a channel plug 114 is formed in the opening 106, and the channel plug 114 contacts the channel layer 110. The channel plug 114 extends from the top surface of the uppermost insulating layer 102 to a certain depth of the opening 106. In one embodiment, the material of the channel plug 114 includes a semiconductor material with doping, such as polysilicon with doping. The channel layer 110, the insulating column 112 and the channel plug 114 can be collectively referred to as a channel column VC. The channel column VC passes through the stacked structure SK1 and extends to the stop structure 103 and even to the insulating layer 101. The charge storage structure 108 surrounds the vertical outer surface of the channel column VC.

Continuing with reference to FIG. 2E , thereafter, a dielectric layer 115 is formed on the stacked structure SK1. Next, a plurality of supporting pillars PIC are formed. The plurality of supporting structures PIC may extend from the top surface of the dielectric layer 115 through the stacked structure SK1 and the stop layer 103 to prevent the step structure SC from collapsing during the subsequent removal of the intermediate layer 104. The supporting structure PIC may include an insulating material or an insulating material and a conductive material. In other embodiments, the supporting structure PIC may be formed simultaneously with the formation of the charge storage structure 108 and the channel pillar VC. The plurality of supporting structures PIC have the same structure as the structure in which the charge storage structure 108 and the channel pillar VC are combined, but the present invention is not limited thereto. For the sake of simplicity, the multiple supporting structures PIC will not be shown in the following.

Referring to FIG. 2F , a dielectric layer 128 is formed on the stacked structure SK1. The dielectric layer 128 is, for example, silicon oxide. A patterning process is performed to form one or more separation trenches 116. The separation trenches 116 may have wavy sidewalls, vertical sidewalls (not shown), or slightly inclined sidewalls (not shown). The separation trenches 116 may include separation trenches 116 ₁ and 116 ₂ .

2F, the separation trench ₁₁₆₁ extends through the dielectric layers 128, 115, 107, the portion 152a of the stop layer 152, the portion 150a of the liner 150, and the topmost conductive layer 94 of the stop layer 103. The separation trench ₁₁₆₂ extends through the dielectric layers 128, 115, the stacking structure SK1, and the stop layer 103, and divides the stacking structure SK1 into a plurality of blocks (not shown).

FIG. 1B is a top view along lines III-III’ and -IV-IV’ of FIG. 2F .

1B , the partition trenches 116 ₁ and 116 ₂ extend along the direction D2 and are arranged along the direction D1. The partition trenches 116 ₁ and 116 ₂ are substantially parallel. The partition trench 116 ₁ is between the partition trenches 116 _2. The partition trench 116 ₁ extends through the step structure SC and divides the step structure SC into two parts SC1 and SC2. The partition trench 116 ₂ is between two step structures SC or between two openings 105.

Referring to FIG. 1B , the partition trench 116 ₁ extends through the side walls sw1 and sw3 of the opening 105. That is, the partition trench 116 intersects the side walls sw1 and sw3. The partition trench 116 ₁ is located between the side walls sw2 and sw4 of the same opening 105, and is separated from the stop layer 152b on the side walls sw2 and sw4 by distances d3 and d4. In the embodiment of the present invention, the side walls sw1 and sw3 intersecting with the partition trench 116 ₁ can also be referred to as intersecting side walls. The side walls sw2 and sw4 not intersecting with the partition trench 116 ₁ can also be referred to as non-intersecting side walls or parallel side walls. The parallel sidewalls described herein may not actually be completely parallel, but only refer to the sidewalls that do not intersect with the separation trench 116 _1. In the embodiment of the present invention, the stop layer 152b and the liner 150b on the sidewalls sw1 and sw3 intersecting with the separation trench 116 ₁ and the stop layer 152a and the liner 150a on the bottom surface are exposed by the separation trench 116. The stop layer 152b and the liner 150b on the sidewalls sw2 and sw4 that do not intersect with the separation trench 116 ₁ are not exposed by the separation trench 116 ₁ . The separation trench ₁₁₆₂ is located between the side walls sw2 and sw4 of two adjacent openings 105 and does not intersect any side wall of the opening 105. The separation trench 1162 is separated from the stop layer 152b on the side walls sw2 and sw4 by distances d5 and d6. The distances d5 and d6 are smaller than the distances d3 and d4.

Continuing with reference to FIG. 2F to FIG. 2H , a gate replacement process is performed to replace part of the middle layer 104 with the conductive layer 126, and part of the stop layer 152 with the conductive layer 126. First, referring to FIG. 2F and FIG. 2G , a selective etching process is performed to allow the etchant to contact the middle layer 104 of the stacked structure SK1 on both sides through the separation trench 116. Thereby, part of the middle layer 104 is removed to form a plurality of horizontal openings 121 a, leaving the middle layer 104 in the peripheral area (shown in FIG. 2R ). The selective etching process may be an isotropic etching, such as a wet etching process. The wet etching process uses an etchant such as hot phosphoric acid.

FIG. 1C is a top view along lines III-III’ and IV-IV’ of FIG. 2G .

1B, 1C and 2G, during the selective etching process, the portion of the stop layer 152 exposed in the separation trench ₁₁₆₁ is also exposed to the etchant and partially removed. In the embodiment of the present invention, the stop layer 152b on the sidewalls sw1 and sw3 of the opening 105 and the stop layer 152a on the bottom surface of the opening 105 are exposed to the etchant and partially removed to form a U-shaped tunnel 121b (shown in FIG. 2G). The stop layer 152b on the sidewalls sw2 and sw4 of the opening 105 is not exposed by the separation trenches 116 ₁ and 116 ₂ and is relatively far from the separation trench 116 ₁ (distances d3 and d4). As the flow path of the etchant is limited, the stop layer 152b cannot contact the etchant flowing out of the separation trench 116 _1. On the other hand, although the stop layer 152b on the sidewalls sw2 and sw4 of the opening 105 is relatively close to the separation trench 116 ₂ (distances d5 and d6), it cannot contact the etchant flowing out of the separation trench 116 ₂ due to the obstruction of the liner 150b. Therefore, the stop layer 152b on the sidewalls sw2 and sw4 of the opening 105 will be left. In addition, as shown in FIG. 2R , the stop layer 152 in the peripheral region PRR is farther from the separation trench 116 and is retained because it cannot contact the etchant. The stop layer 152 will serve as an etching stop layer in the subsequent process of forming the through hole opening OP2, which will be described in detail later.

2G , in the embodiment of the present invention, since the thickness T1 of the stop layer 152 is greater than the thickness T2 of the middle layer 104, after the stop layer 152 and the middle layer 104 are partially removed, the width W1 of the U-shaped tunnel 121b at the bottom of the opening 105 is greater than the width W2 of the horizontal opening 121a. In some embodiments, the width W1 of the U-shaped tunnel 121b is, for example, more than twice that of the horizontal opening 121a. The width W1 of the U-shaped tunnel 121b is less than the minimum width (e.g., bottom width) W3 of the separation trench 116.

Continuing with reference to FIG. 2G and FIG. 2H , a conductive layer 126 is formed on the dielectric layer 128. The conductive layer 126 is also filled into the separation trench 116, the horizontal opening 121a, and the U-shaped tunnel 121b. The conductive layer 126, for example, includes a barrier layer and a metal layer. In one embodiment, the material of the barrier layer includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The material of the metal layer includes tungsten (W). Part of the intermediate layer 104 is replaced by the conductive layer 126, thereby forming a stacking structure (also referred to as a second stacking structure) SK2. Another part of the intermediate layer 104 is retained in the peripheral region PRR, as shown in FIG. 2R .

In the embodiment of the present invention, the thickness T3 of the conductive layer 126 is smaller than the width W1 of the U-shaped tunnel 121b at the bottom of the opening 105 (below the dielectric layer 107) and the bottom width W3 of the separation trench 116. The conductive layer 126 can fill the horizontal opening 121a but cannot fill the U-shaped tunnel 121b and the separation trench 116.

Referring to FIG. 2I , an etching process is performed to remove the conductive layer 126 in the U-shaped tunnel 121 b and the separation trench 116. During the etching process, the etchant can pass through the remaining space between the separation trench 116 and the U-shaped tunnel 121 b and contact the conductive layer 126, so that the conductive layer 126 in the U-shaped tunnel 121 b and the separation trench 116 can be completely removed. The conductive layer 126 in the horizontal opening 121 a is left as a gate layer or a word line WL. A plurality of conductive layers 126 and a plurality of insulating layers 102 are alternately stacked to form a stacking structure SK2.

Referring to FIG. 2J , a stop layer 154 is formed on the dielectric layer 128. The stop layer 154 also fills the U-shaped tunnel 121 b and the separation trench 116. The stop layer 154 may fill the U-shaped tunnel 121 b but not the separation trench 116. The stop layer 154 includes a material different from that of the dielectric layer 107. The stop layer 154 may be a single layer or multiple layers. The stop layer 154 may be an insulating material, a conductive material, or a combination thereof, which will be described in detail later.

2K , an etching process is performed to remove all the stop layer 154 on the dielectric layer 128 and in the separation trench 116, exposing the top surface of the dielectric layer 128 and the sidewalls and bottom surface of the separation trench 116. The stop layer 154 in the U-shaped tunnel 121 b is left. The stop layer 154 is located between the dielectric layer 107 and the liner 150.

The stop layer 154 remaining in the U-shaped tunnel 121b includes a plurality of portions 154a and 154b. For simplicity, the plurality of portions 154a of the stop layer 154 are also referred to as the stop layer 154a. The plurality of portions 154b of the stop layer 154 are also referred to as the stop layer 154b. The stop layer 154a covers the surface of the step structure SC. The stop layer 154b covers the side wall of the dielectric layer 107. The side wall of the stop layer 154a below the dielectric layer 107 is connected to the stop layer 152b. The liner 150a and the stop layer 154a extend continuously to cover the plurality of steps of the step structure SC.

Figure 1D is a top view along lines III-III’ and IV-IV’ of Figures 2I, 2K, 2L to 2O.

1D and 2K , the opening 105 includes a dielectric layer 107, a liner 150, a stop layer 152b, and a stop layer 154. The stop layer 152b is between the sidewall sw2 of the opening 105 and the sidewall of the dielectric layer 107. The stop layer 154b is between the sidewall sw1 of the opening 105 and the sidewall of the dielectric layer 107. The stop layer 154b is also between the sidewall sw3 of the opening 105 and the sidewall of the dielectric layer 107. The stop layer 154a is between the bottom of the opening 105 and the step structure SC. The liner 150b is on the sidewalls sw1-sw4 of the opening 105 and surrounds the sidewalls of the stop layer 152b and the stop layer 154b. The liner 150a is located at the bottom of the opening 105 and between the stop layer 154a and the step structure SC.

2K , an etching process is then performed to deepen the separation trench 116 and partially remove the middle conductive layer 94 and the upper and lower insulating layers 92 in the stop structure 103 to form a horizontal opening 123 .

Referring to Figure 2L, a conductive layer 93 is formed in the horizontal opening 123. The conductive layer 93 in the horizontal opening 123 can form a common source line CSL with the conductive layer 94. The common source line CSL is electrically connected to multiple channel pillars VC. The conductive layer 93 is, for example, doped polysilicon. Then, a filling layer 118 is formed in the space of the separation trench 116 to form a separation wall SLT. The filling layer 118 may include a material different from the stop layer 152 and 154. The filling layer 118 includes an insulating material, such as silicon oxide. The separation wall SLT may include separation walls SLT ₁ and SLT _2. The separation walls SLT ₁ and SLT ₂ are electrically insulated from each other.

1D and 2L, the separation wall SLT ₁ extends through the step structure SC in the opening 105. The separation wall SLT ₁ is located between two rows (C1 and C2) of conductive plugs COA formed subsequently, extends through the dielectric layer 107, the portion 154a4 of the stop layer 154, the liner 150 and the step structure SC, and divides the stop layer 154a into a plurality of sub-portions F1 and F2.

1D, the partition wall SLT ₂ is between two step structures SC, or between two openings 105. The partition wall SLT ₂ extends through the stacking structure SK2. The two parts 152b of the stop layer 152, the stop layer 154, the two rows (C1 and C2) of conductive plugs COA formed later, and the partition wall SLT ₁ are located between the two partition walls SLT ₂ .

2L , a stop layer 129 and a dielectric layer 131 are then formed on the dielectric layer 128. The stop layer 129 is, for example, silicon nitride, and the dielectric layer 131 is, for example, silicon oxide.

Referring to FIGS. 2M to 2O, a plurality of conductive plugs COA are then formed in the step region SCR to electrically connect the conductive layer 126 and the channel pillar VC, respectively. Also, referring to FIG. 2R, a plurality of through-holes TV are formed in the peripheral region PRR. In this embodiment, referring to FIG. 2M, the method for forming the conductive plugs COA and the through-holes TV may firstly perform lithography and etching processes to form a plurality of conductive plug holes OP1 and a plurality of through-hole openings OP2. In the embodiment of the present invention, the etching process is a multi-stage etching process. First, a first stage etching process is performed using the stop layer 154a in the step region SCR and the stop layer 152a in the peripheral region PRR as etching stop layers to form a plurality of conductive plug holes OP1 exposing the stop layer 154a in the dielectric layer 131 to the dielectric layer 107, and to form a plurality of perforated openings OP2 exposing the stop layer 152a. Since the stop layers 154a and 152a have sufficient thickness and have sufficient etching selectivity with the dielectric layer 107, even if the thickness difference of the dielectric layer 107 in different regions of the substrate 100 (the step region SCR and the peripheral region PRR) or on each step of the step structure SC is quite large, the multiple conductive plug holes OP1 and the through-hole openings OP2 with a large depth difference can still be effectively controlled to stop on the stop layer 154a and the stop layer 152a respectively.

Referring to FIG. 2N and FIG. 2R , the second stage etching process is performed, and the liner 150a can be used as an etching stop layer to remove the stop layers 152a and 154a. Then, the third stage etching process is performed to remove the liner 150, so that the depth of the conductive plug hole OP1 and the through-hole opening OP2 is deepened until the conductive layer 126 and the conductive layer 93 of the stop structure 103 are exposed. Due to the second and third stage etching processes, the stop layers 154a and 152a are removed first, and then the liner 150a is removed. Compared to the first stage etching process that removes the relatively thick dielectric layer 107, the thickness of the stop layers 154a and 152a and the liner 150a in each region of the substrate 100 (the step region SCR and the peripheral region PRR) or each step of the step structure SC is relatively thin. Therefore, the etching processes in the second and third stages are easier to control the depth of the conductor plug hole OP1 and the through-hole opening OP2, thereby exposing the conductor layer 126 and the conductor layer 93 respectively without etching through the conductor layer 126 or 93.

Referring to FIG. 2O and FIG. 2R , a conductive material is formed on the dielectric layer 131, and the conductive material is also filled into the conductive plug hole OP1 and the through-hole opening OP2. Afterwards, an etch-back or chemical mechanical polishing process is performed to remove the conductive material on the dielectric layer 131, and a plurality of conductive plugs COA and a plurality of through-holes TV are formed in the conductive plug hole OP1 and the through-hole opening OP2. The conductive material, for example, includes a barrier layer and a metal layer. In one embodiment, the material of the barrier layer includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The material of the metal layer includes tungsten (W). Referring to FIG. 3A , FIG. 3B and FIG. 2R , a plurality of conductive plugs COA and a plurality of through-holes TV having different depths can be formed by the method of the embodiment of the present invention.

Referring to Figures 2P and 2R, an internal connection structure 130 is formed above the substrate 100. The internal connection structure 130 may include multiple dielectric layers (not shown) and internal connections (not shown) formed in the multiple dielectric layers. The internal connections include multiple plugs (not shown) and multiple wires (not shown), etc. The dielectric layer separates adjacent wires. The wires can be connected by plugs, and the wires can be connected to multiple conductive plugs COA and multiple through-holes TV by multiple plugs. The internal connection structure 130 can be formed by a single metal inlay, a dual metal inlay process, or any known method. The internal connection structure 130 may include multiple bit lines BL. The multiple bit lines BL can be electrically connected to the channel pillars VC via multiple conductive plugs COA'. The conductive plug COA' can be formed simultaneously when forming a plurality of conductive plugs COA and a plurality of through-holes TV, or can be formed at different times.

Referring to FIG. 2Q , a bonding structure 132 is formed on the inner connection structure 130. The bonding structure 132 includes a bonding dielectric layer (not shown), a bonding plug (not shown) and a bonding pad (not shown) buried in the bonding dielectric layer. The bonding pad can be connected to the wire of the inner connection structure 130 via the bonding plug. The bonding dielectric layer, the bonding plug and the bonding pad can be formed by any known method. At this point, the manufacture of the chip 100W is completed.

2R, the chip 100W is turned over. After the chip 100W is turned over, the stair structure SC on the substrate 100 becomes a reverse stair structure RSC. The conductive plug COA is below the reverse stair structure RSC.

Next, a bonding process is performed, such as a hybrid bonding process. The bonding structure 132 is bonded to the bonding structure 32 of another chip 10W. The chip 10W may include a substrate 10, a component layer 20, an internal connection structure 30, and a bonding structure 32. The substrate 10 may be a semiconductor substrate, such as a silicon-containing substrate. The component layer 20 is formed on the substrate 10. The component layer 20 may include active components or passive components. Active components are, for example, transistors, diodes, etc. Passive components are, for example, capacitors, inductors, etc. The transistor may be an N-type metal oxide semiconductor (NMOS) transistor, a P-type metal oxide semiconductor (PMOS) transistor, or a complementary metal oxide semiconductor (CMOS) component. The component layer 20 may include a page buffer, peripheral circuits, and a row decoder and a column decoder. The interconnect structure 30 and the bonding structure 32 may have the same or similar components as the interconnect structure 130 and the bonding structure 132, respectively. In the embodiment of the present invention, the device layer 20 having complementary metal oxide semiconductor devices (CMOS) and the memory array ARY originally belong to different chips 10W and 100W, but are bonded to the memory array ARY in a bonding manner. This structure can also be called a CMOS-Bonded-Array (CbA) structure.

In some embodiments, a semiconductor through hole (or silicon via) 16 is further formed in the substrate 100 of the chip 10W. The semiconductor through hole (or silicon via) 16 is electrically isolated from the substrate 10 by the liner 14. The semiconductor through hole 46 is electrically connected to the through hole TV via the interconnect structure 30, the bonding structure 32, 132 and the interconnect structure 130. The liner 14 is, for example, silicon oxide. The material of the semiconductor through hole (or silicon via) 16 is, for example, copper or tungsten.

Referring to FIG. 2R , after the bonding process, the substrate 100 is removed to expose the insulating layer 101. The substrate 100 can be removed by grinding, polishing or etching. In other embodiments, the substrate 100 is thinned, and a portion is still retained (not shown) and connected to the internal connection structure 130 through a semiconductor through hole (or silicon through hole) formed in the substrate 100.

Referring to FIG. 2R , the back-end process is performed. A liner 44, a conductive plug 46, a wire 48, and a dielectric layer 50 of the internal connection structure 40 are formed on the insulating layer 101. The conductive plug 46 electrically connects the through-hole TV and the wire 48. The conductive plug 46 is electrically isolated by the liner 44 and the conductive layer 94 of the stop structure 103. The method for forming the internal connection structure 40 is described as follows. First, a lithography and etching process is performed to form a conductive plug opening 43 in the insulating layer 101 and the stop structure 103. Then, a liner 44 and a conductive plug 46 are formed in the conductive plug opening 43. The method for forming the liner 44 is, for example, to form a dielectric material on the insulating layer 101 and in the conductive plug opening 43, and then perform anisotropic etching. The method for forming the conductive plug 46 is, for example, to form a conductive material on the insulating layer 101 and in the conductive plug opening 43, and then perform a chemical mechanical polishing process or etching back. The dielectric material is, for example, silicon nitride or a silicon oxide/silicon nitride/silicon oxide composite layer. The conductive material is, for example, doped polysilicon. Thereafter, a wire 48 and a dielectric layer 50 are formed on the insulating layer 101. The material of the wire 48 is, for example, copper or tungsten. The dielectric layer 50 can be a single layer or multiple layers. The material of the dielectric layer 50 may be silicon oxide, silicon oxynitride, silicon nitride or a combination thereof. The interconnect structure 40 may be electrically connected to the interconnect structures 130 and 30 via the via TV. In addition to being connected to the via TV, the interconnect structure 130 may also be electrically connected to the channel pillar VC or the conductive layer 126 (e.g., the word line WL) via the conductive plug COA'.

Afterwards, a connector 52 is formed on the wire 48. The connector 52 may be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a C2 bump, a micro bump, a bump formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), or a similar component. At this point, the fabrication of the memory chip SM1 is completed.

1D and 2R, in this embodiment, a plurality of alternately stacked conductive layers 126 and a plurality of insulating layers 102 remain between two adjacent openings 105 in the step region SCR. The liner 150 and the stop layer 154 in the step region SCR remain not only at the bottom of the opening 105 as an etching stop layer, but also on the side walls sw1 and sw3 of the opening 105 (as shown in FIG. 1D). The liner 150 and the stop layer 152 in the step region SCR remain on the side walls sw2 and sw4 of the opening 105 (as shown in FIG. 1D). The liner layer 150 and the stop layer 152 in the peripheral region PRR remain at the bottom of the opening 105 as an etching stop layer, and also remain on the sidewalls of the opening 105 (as shown in FIG. 2R ).

4A and 4B are partial cross-sectional schematic diagrams showing a plurality of stop layers and liner layers according to an embodiment of the present invention.

4A and 4B , the stop layers 154 and 152b, the liner 150, and the dielectric layer 107 of the embodiment of the present invention are located in the opening 105. The stop layers 154 and 152b are located between the liner 150 and the dielectric layer 107. The stop layer 152b is located between the sidewall of the opening 105 and the sidewall of the dielectric layer 107. The stop layer 154a located at the bottom of the opening 105 is buried under the dielectric layer 107, covers the conductive layer 126 of the step structure SC, and is laterally adjacent to and connected to the stop layer 152b. The separation wall _SLT1 extends through the dielectric layer 107, the stop layer 154 and the liner 150 and the step structure SC in the opening 105. The stop layer 154a at the bottom of the opening 105 is extended through by the separation wall _SLT1 and is divided into two sub-portions F1 and F2.

4A and 4B , the width T4 of the stop layer 154a at the bottom of the opening 105 (below the dielectric layer 107) is greater than the width T3 of the conductive layer 126. In some embodiments, the thickness T4 of the stop layer 154a at the bottom of the opening 105 (below the dielectric layer 107) is more than twice the thickness T3 of the conductive layer 126. The thickness T4 of the stop layer 154a is less than the bottom width W3 of the separation wall SLT. Therefore, in the process of forming the stop layer 154, the stop layer 154 cannot fill the separation trench 116 (shown in FIG. 2J ) to facilitate the subsequent removal process. The length L1 of the sub-portion F1 (or F2) of the stop layer 154a at the bottom of the opening 105 (below the dielectric layer 107) is smaller than the distance P1 between the separation walls _SLT1 and _SLT2 , and larger than half of the distance P1.

4A and 4B , the stop layer 154 may be a single layer or multiple layers. The material of the stop layer 154 may include an insulating layer, a conductive layer, or a combination thereof. The insulating layer may include SIN, SiCN, SiCON, a high dielectric constant material (e.g., Al ₂ O ₃ , Hf ₂ O ₅ ) or a combination thereof. The conductive layer may include polysilicon, tungsten, cobalt, copper, tantalum, titanium, tantalum nitride, titanium nitride, metal silicide, or a combination thereof.

4A, for example, the stop layer 154 may include material layers ₁₅₄₁ and _1542. The material layer ₁₅₄₁ covers the upper and lower surfaces of the material layer ₁₅₄₂ and the sidewalls adjacent to the stop layer 152b. The material layer ₁₅₄₁ is, for example, a high dielectric constant material layer. The high dielectric constant material layer may be formed before forming the conductor layer 126, so that it also extends to cover the upper and lower surfaces of the conductor layer 126 and the sidewalls of the separation trench 116. The material layer ₁₅₄₂ may be an insulating filling layer, such as silicon nitride, or a conductive filling layer, such as polysilicon. The material layer 154 ₂ may be formed by a deposition method, and an interface 154I is formed in the material layer 154 ₂ .

4B, for example, the stop layer 154 may include material layers ₁₅₄₁ , ₁₅₄₂ , and _1543. The material layer ₁₅₄₁ covers the outer sidewall of the material layer _1542. The material layer ₁₅₄₂ is between the material layers ₁₅₄₁ and _1543. The material layer ₁₅₄₁ is, for example, a high dielectric constant material layer. The high dielectric constant material layer may be formed before forming the conductor layer 126, so that it also extends to cover the upper and lower surfaces of the conductor layer 126 and the sidewalls of the separation trench 116. The material layer ₁₅₄₁ may remain in the separation trench 116 and form a separation wall SLT together with the filling layer 118.

The material layer 154 ₂ may be a barrier layer, such as tantalum, titanium, tantalum nitride, titanium nitride or a combination thereof. The barrier layer may be formed before forming the conductor layer 126, so that it also extends to cover the upper and lower surfaces of the conductor layer 126 and the sidewalls of the separation wall SLT. The barrier layer covering the upper and lower surfaces of the conductor layer 126 may be retained, while the barrier layer on the sidewalls of the separation trench 116 is removed. The material layer 154 ₃ may be a conductor filling layer. The conductor filling layer includes a metal layer, such as tungsten. The material layer 154 ₃ may be formed by a deposition method, and an interface 154I is formed in the material layer 154 ₃ .

4C and 4D are partial cross-sectional schematic views showing a conductive plug extending through a plurality of stop layers and liner layers according to an embodiment of the present invention.

4C and 4D , the conductive plug COA of the embodiment of the present invention is located between the separation walls SLT ₁ and SLT _2. The conductive plug COA extends through the dielectric layer 107, the stop layer 154, and the liner 150, and lands on the conductive layer 126 of the step structure SC, and is electrically connected to the conductive layer 126. The conductive plug COA may include a single layer or multiple layers. The conductive plug COA may include an insulating material, a conductive material, or a combination thereof. The insulating material is, for example, silicon oxide, and the conductive material is, for example, polysilicon, tungsten, tantalum, titanium, tantalum nitride, titanium nitride, or a combination thereof.

4C , when the stop layer 154 is an insulating material, the conductive plug COA may be a conductive material 156, such as a barrier layer 156 ₁ and a conductive filling layer 156 ₂ . The barrier layer 156 ₁ is on the sidewall and bottom of the conductive filling layer 156 ₂ , such as tungsten, titanium, tungsten nitride, titanium nitride or a combination thereof. The conductive filling layer 156 ₂ includes a metal layer, such as tungsten.

4D , when the stop layer 154 includes a conductive material (i.e., the material layer 154 ₂ is a barrier layer, and the material layer 154 ₃ is a conductive filling layer), the conductive plug COA may include a liner material 157 and a conductive material 156. The conductive material 156 may include a barrier layer 156 ₁ and a conductive filling layer 156 ₂ . The liner material 157 surrounds the sidewall of the barrier layer 156 ₁ to electrically isolate the barrier layer 156 ₁ from the material layer 154 ₂ (barrier layer), and to electrically isolate the barrier layer 156 ₁ from the material layer 154 ₃ (conductive filling layer). The liner material 157 is, for example, silicon oxide or silicon nitride or a combination thereof. The barrier layer 156 ₁ is formed on the sidewall and bottom of the conductive filling layer 156 ₂ , and is, for example, tantalum, titanium, tantalum nitride, titanium nitride or a combination thereof. The conductive filling layer 156 ₂ includes a metal layer, for example, tungsten.

In the above embodiments, referring to FIG. 2J and FIG. 2K , the stop layer 154 on the dielectric layer 128 and in the separation trench 116 is completely removed, however, the present embodiment is not limited thereto. The stop layer 154 may be thinned or not thinned and remain on the sidewall and bottom of the separation trench 116, or the stop layer 154 at the bottom of the separation trench 116 may be partially removed, as shown in FIGS. 5A to 5C , 6A to 6B , and 7A to 7C , respectively.

In the process of FIG. 5A to FIG. 5C , the stop layer 154 (shown in FIG. 5A ) on the dielectric layer 128 and in the separation trench 116 is thinned to a stop layer 154 ′ (shown in FIG. 5B ). Thereafter, the stop layer 154 ′ on the dielectric layer 128 is removed by an anisotropic etching process, leaving the stop layer 154 ′ on the sidewall and bottom surface of the separation trench 116 . The stop layer 154 ′ and the subsequently formed filling layer 118 together form the separation walls SLT ₁ and SLT ₂ (shown in FIG. 5C ).

In the process of FIG. 6A to FIG. 6B , after the stop layer 154 is formed (shown in FIG. 6A ), the stop layer 154 is not thinned, but directly subjected to an anisotropic etching process to remove the stop layer 154 on the dielectric layer 128, leaving the stop layer 154 on the sidewall and bottom of the separation trench 116. The stop layer 154 and the subsequently formed filling layer 118 together form the separation walls SLT ₁ and SLT ₂ (shown in FIG. 6B ).

In the process of FIG. 7A to FIG. 7C , after the stop layer 154 is formed (shown in FIG. 7A ), the stop layer 154 is not thinned, but directly subjected to an anisotropic etching process to remove the stop layer 154 on the dielectric layer 128 and the bottom of the separation trench 116, leaving the stop layer 154 on the sidewall of the separation trench 116 (shown in FIG. 7B ). The stop layer 154 and the subsequently formed filling layer 118 together form the separation walls SLT ₁ and SLT ₂ (shown in FIG. 7C ).

8A to 8D are top views of a method for manufacturing a memory element in an intermediate stage according to another embodiment of the present invention. FIG. 9A to 9E are schematic cross-sectional views of a method for manufacturing a memory element according to another embodiment of the present invention. For clarity, FIG. 8A and FIG. 8D show top views of lines VIII-VIII’ and IX-IX’ of the step region in FIG. 9A and FIG. 9D. FIG. 9A and FIG. 9D show schematic cross-sectional views of the step region (including the cross-sections of lines VI-I’ and VII-VII’ in two different directions D1 and D2 of FIG. 8A to FIG. 8D) and the memory array region ARR. Direction D1 is, for example, a direction parallel to the bit line. Direction D2 is, for example, a direction parallel to the word line. FIG. 9E is a schematic cross-sectional view of the step region SCR, the memory array region ARR, and the peripheral region PRR.

Referring to FIG. 9A , according to the above method, an insulating layer 101, a stop structure 103, and a lower portion LP of a stacking structure (or first stacking structure) SK1 are formed on a substrate 100. Then, a plurality of dummy columns DVC are formed in the lower portion LP of the stacking structure SK1. Thereafter, an upper portion UP of the stacking structure SK1 and a hard mask layer HM are formed above the substrate 100. Then, the hard mask layer HM is patterned. Then, using the hard mask layer HM as a mask, the middle layer 104 and the insulating layer 102 of the stacking structure SK1 are patterned to form an opening 105A and a step structure SC.

FIG8A is a top view along lines VIII-VIII’ and -IX-IX’ of FIG9A to FIG9B.

Referring to FIG. 8A and FIG. 9A , the opening 105A is, for example, rectangular. The scope of the opening 105A is quite large, covering the two adjacent openings 105 of FIG. 1A and the area between them and the surrounding area. In FIG. 1A , the step structures SC exposed by the two openings 105 are each independent and separated. In FIG. 8A , the step structure SC exposed by the opening 105A is continuously extended. The opening 105A extends in the direction D1 , and therefore, only the side walls sw1 and sw3 are shown.

8A and 9B, a liner 150, a stop layer 152 and a dielectric layer 107 are formed in the opening 105A according to the above method, and after the liner 150, the stop layer 152 and the dielectric layer 107 on the hard mask layer HM are removed according to the above method, the hard mask layer HM is removed.

8A and 9B , the liner 150 remaining in the opening 105A includes a plurality of portions 150a and 150b. The stop layer 152 remaining in the opening 105A includes a plurality of portions 152a and 152b. The portions 150a and 152a cover the surface of the step structure SC. The portions 150b and 152b cover the sidewalls sw1 and sw3 of the stacking structure SK1 exposed in the opening 105A.

9C , the charge storage structure 108 , the channel pillar VC , the dielectric layer 115 , a plurality of supporting pillars (not shown), the dielectric layer 128 and the separation trench 116 are formed according to the above method. Referring to FIG 8B and FIG 9C , the separation trench 116 may include separation trenches 116 ₁ and 116 ₂ .

8C and 9C , a selective etching process is performed to remove the intermediate layer 104 and a portion of the stop layer 152 on both sides of the separation trenches 116 ₁ and 116 ₂ to form the horizontal opening 121 a as described above. Thereafter, the conductive layer 126 is refilled in the horizontal opening 121 a (as shown in FIG. 8D and FIG. 9C ). In this embodiment, when performing the selective etching process, the etchant can contact the stop layer 152 through the separation trenches ₁₁₆₁ and ₁₁₆₂ on both sides. Therefore, the stop layer 152b on the side walls sw1 and sw3 of the opening 105A and the stop layer 152a on the bottom surface of the opening 105A contact the etchant and are removed, thereby forming a U-shaped tunnel 121b (shown in FIG. 9C).

It is worth noting that in the above-mentioned embodiment, referring to FIG. 1B , the stop layer 152b on the side walls sw2 and sw4 will be left. The stop layer 152b covers the liner 150b on the side walls sw2 and sw4. In the present embodiment, referring to FIG. 8C , except for the side walls sw1 and sw3 of the opening 105A, there is no stop layer 152b between the two sides of the separation trenches 116 ₁ and 116 ₂ , and the stop layer 152a on the bottom surface of the opening 105A is left. Similarly, the stop layer 152 in the peripheral region PRR will only leave the stop layer 152a on the bottom surface of the opening 105A, as shown in FIG. 9E . As described in the above embodiment, when the conductive layer 126 is formed, the conductive layer 126 is also formed in the U-shaped tunnel 121b. Then, an etching process is performed to remove the conductive layer 126 in the U-shaped tunnel 121b and the separation trench 116, so that the U-shaped tunnel 121b and the separation trench 116 are exposed.

Referring to FIG. 9D and FIG. 9E, according to the method of the above-mentioned embodiment, a stop layer 154 is formed in the U-shaped tunnel 121b. Thereafter, the depth of the separation trench 116 is deepened, and the middle conductive layer 94 in the stop structure 103 and the insulating layers 92 above and below it are replaced by a conductive layer 93. The conductive layer 93 can form a common source line CSL with the conductive layer 94. Separation walls SLT ₁ and SLT ₂ are formed according to the method of the above-mentioned embodiment. Then, a plurality of conductive plugs COA are formed to electrically connect the conductive layer 126 respectively. And, referring to FIG. 9E, a plurality of through holes TV are formed. In the first stage etching process of forming a plurality of conductive plug holes OP1 and a plurality of through-hole openings OP2 of a plurality of conductive plugs COA and a plurality of through-holes TV, the stop layers 154a and 152a may be used as etching stop layers. Since the stop layers 154a and 152a have sufficient thickness and have sufficient etching selectivity with the dielectric layer 107, even if the thickness difference of the dielectric layer 107 in each region of the substrate 100 (the step region SCR and the peripheral region PRR) or each step of the step structure SC is quite large, the plurality of conductive plug holes OP1 and through-hole openings OP2 with a large depth difference can still be effectively controlled to stop on the stop layer 154a and the stop layer 152a respectively, without etching through the conductive layer 126 or 93. Referring to FIG. 10A, FIG. 10B and FIG. 9E, a plurality of conductive plugs COA and a plurality of through-holes TV with different depths can be formed by the method of the embodiment of the present invention.

9E, an internal connection structure 130 and a bonding structure 132 are formed on the substrate 100 according to the method of the above embodiment. Then, the bonding structure 132 is bonded to the bonding structure 32 of another chip 10W until a connector 52 is formed on the wire 48. Thus, the memory device SM2 is formed.

8D and 9E, in this embodiment, the opening 105A is different from the opening 105 shown in FIG1D and FIG2R. The multiple conductive layers 126 and the multiple insulating layers 102 alternately stacked between two adjacent openings 105 in FIG1D and FIG2R are removed, thereby forming the opening 105A, as shown in FIG8D and FIG9E. In this embodiment, the liner 150 and the stop layer 154 in the step region SCR remain at the bottom of the opening 105A as an etching stop layer, and the liner 150 and the stop layer 154 also remain on the sidewalls sw1 and sw3 of the opening 105A (as shown in FIG8D). The liner layer 150 and the stop layer 152 in the peripheral region PRR remain at the bottom of the opening 105A as an etch stop layer (as shown in FIG. 9E ).

11A and 11B are partial cross-sectional schematic diagrams showing a plurality of stop layers and liner layers according to an embodiment of the present invention.

11A and 11B , in this embodiment, the stop layer 154, the liner 150, and the dielectric layer 107 are located in the opening 105A. The stop layer 154 is located between the liner 150 and the dielectric layer 107. Unlike the above-mentioned embodiment, the stop layer 152b is not located between the sidewall of the opening 105A and the sidewall of the dielectric layer 107, so the length L1' of the sub-portion F1 (or F2) of the stop layer 154a is longer. Similarly, the stop layer 154 can be a single layer or multiple layers. The material of the stop layer 154 can include an insulating layer, a conductive layer, or a combination thereof. The insulating layer may include silicon nitride, a high dielectric constant material, or a combination thereof. The conductive layer may include polysilicon, tungsten, tantalum, titanium, tantalum nitride, titanium nitride, or a combination thereof.

11A , for example, the stop layer 154 may include material layers 154 ₁ and 154 ₂ as described in the above embodiment, and the material layer 154 ₂ has an interface 154I. Referring to FIG11B , for example, the stop layer 154 may include material layers 154 ₁ , 154 ₂ , and 154 ₃ as described in the above embodiment. The material layer 154 ₃ has an interface 154I.

11C and 11D are partial cross-sectional schematic views of a conductive plug extending through a plurality of stop layers and liner layers according to an embodiment of the present invention.

11C and 11D , the conductive plug COA of the embodiment of the present invention is located between the separation walls SLT ₁ and SLT _2. The conductive plug COA extends through the dielectric layer 107, the stop layer 154 and the liner 150, and lands on the conductive layer 126 of the step structure SC. The conductive plug COA may include a single layer or multiple layers. The conductive plug COA may include an insulating material, a conductive material or a combination thereof. The insulating material is, for example, silicon oxide, and the conductive material is, for example, polysilicon, tungsten, tantalum, titanium, tantalum nitride, titanium nitride or a combination thereof.

11C , when the stop layer 154 is an insulating material, the conductive plug COA may be a conductive material 156, such as a barrier layer 156 ₁ and a conductive filling layer 156 ₂ . The relative positions and materials of the barrier layer 156 ₁ and the conductive filling layer 156 ₂ are as described in the above embodiment.

11C , when the stop layer 154 includes a conductive material (i.e., the material layer 154 ₂ is a barrier layer and the material layer 154 ₃ is a conductive filling layer), the conductive plug COA may include a liner material 157 and a conductive material 156. The conductive material 156 may include a barrier layer 156 ₁ and a conductive filling layer 156 ₂ . The relative positions and materials of the liner material 156 ₃ and the conductive material 156 are as described in the above embodiment.

In the above embodiment, the stop layer 154 on the dielectric layer 128 and in the separation trench 116 is completely removed, however, the present embodiment is not limited thereto. The stop layer 154 may be thinned or not thinned and remain on the sidewall and bottom of the separation trench 116, or the stop layer 154 at the bottom of the separation trench 116 may be partially removed (not shown).

12A to 12C are cross-sectional schematic diagrams of a manufacturing process of a stacked chip according to an embodiment of the present invention.

The present invention can stack the above-mentioned multiple memory chips SM1, multiple memory chips SM2, or memory chips SM1 and memory chips SM2 into a stacked chip. For simplicity, multiple memory chips SM1 are stacked into a stacked chip 200W as an example for explanation.

12A , the substrate 10 of the memory chip SM1 is thinned to expose the semiconductor through-hole (or TSV) 16. Then, a dielectric layer 51 and a connector 52′ connected to the semiconductor through-hole (or TSV) 16 are formed on the semiconductor through-hole (or TSV) 16 to form the memory chip SM1′.

Referring to FIG. 12B , thereafter, the connector 52 of the memory chip SM1 is joined to the connector 52′ of the memory chip SM1′ to form a stacked chip 200W.

Referring to FIG. 12C , a chip 300W is provided. The chip 300W may be a logic chip. The chip 300W may have a substrate 300, a semiconductor through hole (or silicon via) 316, a device layer 320, an internal connection structure 330, and a connector 352. The substrate 300, the semiconductor through hole (or silicon via) 316, the device layer 320, the internal connection structure 330, and the connector 352 may be the same, similar, or different from the substrate 10, the semiconductor through hole (or silicon via) 16, the device layer 20, the internal connection structure 30, and the connector 52 described above.

Referring to FIG. 12D , the stacked wafer 200W is bonded to the wafer 300W to form the stacked wafer 400W. Before the bonding process, the substrate 300 of the wafer 300W may be thinned to expose the semiconductor through-hole (or silicon via) 316. Thereafter, a dielectric layer 351 and a connector 352′ connected to the semiconductor through-hole (or silicon via) 316 are formed on the semiconductor through-hole (or silicon via) 316.

The stacking chip 200W can be bonded to the connector 352' of the chip 300W through the connector 52. Underfills 402 and 404 can be filled between the connectors 52 and 52' and between the connectors 52 and 352'. The stacking chip 200W can be covered with an encapsulation layer 406.

The stacked chip 400W of the embodiment of the present invention includes two memory chips SM1 and SM1' in the vertical direction. However, the embodiment of the present invention is not limited thereto. The stacked chip 500W may include more memory chips SM1 and SM1' in the vertical direction.

FIG13 is a schematic cross-sectional view showing a packaging structure.

13 , the stacked chip 400W can be connected to a controller or directly connected to a host through a semiconductor through-hole to provide wide channel width and high speed per channel, and thus can be used as a high-bandwidth NAND flash memory.

The stacked chip 400W may be bonded to the interposer 600 together with the application specific integrated circuit (ASIC) 500 to form a package structure 700. However, the application of the stacked chip 400W is not limited thereto.

The above description is based on a 3D NAND flash memory, but the present invention is not limited thereto and can also be applied to other 3D flash memories, such as a 3D NOR flash memory.

The embodiment of the present invention can accurately control the formation of contact holes and perforation openings of different depths by setting the stop layer, so as to avoid the contact holes and perforation openings having different depths, which may cause some of the contact holes and perforation openings to fail to land on the word line or conductor layer of the correct step. Therefore, the embodiment of the present invention can prevent the conductor plug from failing to land on the word line and avoid abnormal short circuit of the conductor plug by setting the stop layer. Therefore, the embodiment of the present invention can improve the yield of the process.

10, 100, 300: base

10W, 100W, 300W: Chip

14, 44, 150, 150a, 150b: Lining

16, 316: Semiconductor penetration

20, 320: Component layer

30, 40, 130, 330: Internal connection structure

32, 132: Joint structure

43: Conductor plug opening

46. COA, COA’: Conductor plug

48: Wire

50, 51, 107, 115, 128, 131: dielectric layer

52, 52', 352, 352': Connectors

92, 101, 102: Insulation layer

93, 94, 126: Conductor layer

103: Stop structure

129, 152, 154, 154b', 154': stop layer

103a: Insulation structure

104: Middle layer

105, 105A, 106: Open

108: Charge storage structure

110: Channel layer

112: Insulation Pillar

114: Channel plug

116: Separation Ditch

118: Filling layer

121a, 123: horizontal opening

121b: U-shaped tunnel

150a, 150b: Lining/part

152a, 152b: Stop layer/part

154I: Interface

154: Stop layer

156: Conductor material

156 ₁ : Barrier layer

156 ₂ : Conductor filling layer

156 ₃ : Lining material

200W, 400W, 500W: stacked chips

402, 404: Fill bottom filler

406: Encapsulation layer

500:Application Specific Integrated Circuit

600:Intermediate layer

700: Packaging structure

154 ₁ , 154 ₂ , 154 ₃ : Material layer

ARR: Memory Array Region

ARY: memory array

BL: Bit Line

CSL: Common Source Line

D1: Direction

D2: Direction

d3, d4, d5, d6: distance

DVC: Virtual Column

F1, F2: Subsections

HM:Hard mask

L1, L1’: Length

LP: Lower

MC:Memory unit

OP1: Conductor plug hole

OP2: Perforated opening

P1: Distance

PIC:Support structure

PRR: Peripheral Region

RSC: Reverse ladder structure

SC: Step structure

SC1, SC2: Partial

SCR: Step Area

SK1, SK2: stacking structure

SLT, SLT ₁ , SLT ₂ : Partition wall

SM1, SM1’, SM2: memory chips

T1, T2, T3, T4: thickness

TV:Piercing

UP: Upper

VC: Channel Column

W1: Width

W2: Width

W3: minimum width/bottom width

WL: word line

d3, d4: distance

sw1, sw2, sw3, sw4: side wall

I-I’: Line

II-II’: Line

IV-IV’: Line

VI-VI’: Line

VII-VII’: Line

VIII-VIII’: Line

S1~S10: Stairs

Figures 1A to 1D are top views of an intermediate stage of a method for manufacturing a memory element according to an embodiment of the present invention. Figures 2A to 2R are cross-sectional schematic diagrams of a method for manufacturing a memory element according to an embodiment of the present invention. Figures 3A and 3B show conductive plugs of different depths. Figures 4A and 4B show partial cross-sectional schematic diagrams of multiple stop layers and liner layers of an embodiment of the present invention. Figures 4C and 4D show partial cross-sectional schematic diagrams of conductive plugs extending through multiple stop layers and liner layers of an embodiment of the present invention. Figures 5A to 5C, Figures 6A to 6B, and Figures 7A to 7C show cross-sectional schematic diagrams of intermediate stages of various memory elements of an embodiment of the present invention. 8A to 8D are top views of an intermediate stage of a method for manufacturing a memory element according to another embodiment of the present invention. Figs. 9A to 9E are cross-sectional schematic diagrams of a method for manufacturing a memory element according to another embodiment of the present invention. Figs. 10A and 10B show conductive plugs of different depths. Figs. 11A and 11B show partial cross-sectional schematic diagrams of multiple stop layers and liner layers of an embodiment of the present invention. Figs. 11C and 11D show partial cross-sectional schematic diagrams of conductive plugs extending through multiple stop layers and liner layers of an embodiment of the present invention. Figs. 12A to 12D are cross-sectional schematic diagrams of a manufacturing process of a stacked chip according to an embodiment of the present invention. Fig. 13 shows a cross-sectional schematic diagram of a package structure.

128: Dielectric layer

sw2, sw4: side wall

150: Lining

152b: Stop layer/section

154a: Stop layer/section

F1, F2: Subsections

SLT ₁ , SLT ₂ : Partition wall

COA: Conductor Plug

OP1: Conductor plug hole

105: Open mouth

107: Dielectric layer

SC1, SC2: ladder structure

126: Conductor layer

103: Stop structure

Claims (20)

A memory element comprises: a substrate; a stacking structure located above the substrate, wherein the stacking structure comprises a plurality of conductor layers and a plurality of insulating layers stacked alternately, and the stacking structure has an opening exposing a step structure of the stacking structure; a first stop layer covering the step structure and at least a portion of a plurality of side walls of the opening; a dielectric layer filling the opening and covering the first stop layer; at least one separation wall extending through the dielectric layer in the opening and the first stop layer; and a conductive plug extending through the dielectric layer and the first stop layer and electrically connected to the step structure. The memory device as described in claim 1 further includes: a second stop layer partially covering the step structure and the remaining portion of the plurality of side walls of the opening, wherein the remaining portion of the plurality of side walls is different from the at least a portion of the plurality of side walls of the opening. A memory device as described in claim 1, wherein the first stop layer is located at the bottom of the opening, and the first stop layer has an interface therein. A memory device as described in claim 1, wherein the first stop layer includes an insulating fill layer. A memory element as described in claim 1, wherein the plurality of conductive layers have a first thickness, the first stop layer located at the bottom of the opening has a second thickness, and the second thickness is more than twice the first thickness. A memory element as described in claim 3, wherein the bottom width of the at least one partition wall, the first stop layer located at the bottom of the opening has a second thickness, and the second thickness is less than the bottom width. A memory element as described in claim 1, wherein the first stop layer includes a conductive filling layer, the conductive plug includes a conductive material and a lining material surrounding the sidewalls of the conductive material, and the lining material separates the conductive material from the conductive filling layer. A memory element comprises: a substrate; a stacking structure located above the substrate, wherein the stacking structure comprises a plurality of conductor layers and a plurality of insulating layers stacked alternately, the stacking structure has an opening exposing a step structure of the stacking structure, wherein the opening comprises: a first sidewall; a second sidewall connected to the first sidewall; a third sidewall connected to the second sidewall, wherein the first sidewall is opposite to the third sidewall; a fourth sidewall connected to the third sidewall, wherein the second sidewall is opposite to the fourth sidewall; and a bottom, connected to the first sidewall. , the second sidewall, the third sidewall and the fourth sidewall are connected; the first stop layer includes: a first portion covering the step structure; and a second portion covering at least the first sidewall and the third sidewall; a dielectric layer filled in the opening and covering the first stop layer; at least one partition wall extending through the dielectric layer in the opening and the first portion and the second portion of the first stop layer; and a conductive plug extending through the dielectric layer and the first portion of the first stop layer and electrically connected to the step structure. A memory element as described in claim 8, wherein the at least one partition wall extends in a direction and is parallel to the second side wall and the fourth side wall. A memory device as described in claim 8, wherein the first portion of the first stop layer has an interface. A memory element as described in claim 8, wherein the first stop layer includes a high dielectric constant material layer and an insulating filling layer covered by the high dielectric constant material layer. A memory element as described in claim 8, wherein the first stop layer includes a conductive fill layer. The memory device as described in claim 8 further includes: a first partition wall extending through the dielectric layer, the first portion of the first stop layer and the step structure, and dividing the first portion of the first stop layer into a plurality of sub-portions; and a plurality of second partition walls extending through the stacking structure, wherein the second portion of the first stop layer and the first partition wall are located between the plurality of second partition walls. A memory element as described in claim 13, wherein the first partition wall and the plurality of second partition walls comprise a material different from the first stop layer. The memory device as described in claim 13 further includes a second stop layer covering the second side wall and the fourth side wall. A memory element as described in claim 15, wherein the first partition wall and the plurality of second partition walls comprise a material different from the second stop layer. A memory device as described in claim 13, wherein at least one partition wall includes a first partition wall and a second partition wall, the first partition wall and the second partition wall are separated by a first distance, the multiple sub-portions of the first portion of the first stop layer are located between the first partition wall and the second partition wall, and the length of the sub-portion is greater than half of the first distance. A memory device as described in claim 13, wherein the first partition wall is electrically insulated from the second partition wall. A memory device as described in claim 8, wherein the thickness of the first portion of the first stop layer is less than the bottom width of the at least one partition wall. A memory element as described in claim 8, wherein the plurality of conductive layers have a first thickness, the first portion of the first stop layer has a second thickness, and the second thickness is greater than 2 times the first thickness.