TWI860742B - Memory device and method of fabricating the same - Google Patents

Abstract

A memory device includes a substrate, a composite stacked structure, multiple first insulating structures, and multiple through vias. The substrate includes a memory plane region and a periphery region. The composite stacked structure is located on the substrate in the memory plane region and the periphery region, wherein the composite stacked structure includes a first stacked structure. The first stacked structure includes multiple first insulating layers and multiple intermediate layers alternately stacked on each other, and is located on the substrate in the periphery region. The first insulating structures are separated from each other, extend through the first stacked structure in the periphery region, and are respectively surrounded by the first insulating layers and the intermediate layers. The through vias extend through one of the first insulating structures.

Description

Memory element and method for manufacturing the same

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a memory device and a manufacturing method thereof.

Non-volatile memory devices (such as flash memory) have the advantage that the stored data will not disappear even after power failure. Therefore, they have become a type of memory device widely used in personal computers and other electronic devices.

The flash memory arrays commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of NAND flash memory is to connect each memory cell in series, its integration and area utilization are better than NOR flash memory, and it has been widely used in many electronic products. In addition, in order to further improve the integration of memory components, a three-dimensional NAND flash memory has been developed. However, there are still many challenges related to three-dimensional NAND flash memory.

The present invention provides a memory device which can reduce the amount of insulating material deposited in the peripheral area.

A memory element of an embodiment of the present invention includes a substrate, a composite stacking structure, a plurality of first insulating structures and a plurality of through-holes. The substrate includes a memory surface area and a peripheral area. The composite stacking structure is located on the substrate in the memory surface area and the peripheral area. The composite stacking structure includes a first stacking structure. The first stacking structure includes a plurality of first insulating layers and a plurality of intermediate layers alternately stacked on each other and located on the substrate in the peripheral area. The plurality of first insulating structures are separated from each other, extend through the first stacking structure in the peripheral area, and are respectively surrounded by the plurality of first insulating layers and the plurality of intermediate layers. The plurality of through-holes extend through one of the plurality of first insulating structures.

Based on the above, the stacking structure of the memory element of the embodiment of the present invention is retained in the peripheral area. The perforations in the peripheral area are isolated from each other by multiple insulating structures. The multiple insulating structures are separated from each other. The multiple insulating structures are formed by removing a small portion of the stacking structure in the peripheral area and then backfilling a small amount of insulating material. Therefore, the deposition amount of insulating material can be reduced and the time for grinding excess insulating material can be reduced.

FIG. 1 is a top view of a memory element according to an embodiment of the present invention. FIG. 2D is a cross-sectional schematic diagram of a peripheral region of a memory element according to an embodiment of the present invention. FIG. 3J is a cross-sectional schematic diagram of a memory element according to an embodiment of the present invention. FIG. 4A to FIG. 4N are top views of various perforations and insulating structures according to an embodiment of the present invention. FIG. 4O to FIG. 4P are top views of various sealing rings and insulating structures according to an embodiment of the present invention. FIG. 5A and FIG. 5B are top views of various perforations and insulating structures according to an embodiment of the present invention.

1, a memory device SM1 of an embodiment of the present invention includes a substrate 10, a composite stack structure CSK, a plurality of insulating structures 107P, 107A, 107E, 107G, a plurality of contact windows COA, and a plurality of through holes TV. The substrate 10 includes a memory surface area R1, a peripheral area R2, and a sealing ring area R3. The memory surface area R1 may include a step area SCR and a plurality of array areas AR on both sides of the step area SCR. The peripheral area R2 surrounds the memory surface area R1. The sealing ring area R3 surrounds the peripheral area R2.

Referring to FIG1 , the composite stacking structure CSK is located on the substrate 10 of the memory surface area R1, the peripheral area R2, and the sealing ring area R3. The composite stacking structure CSK includes a first stacking structure SK1 and a second stacking structure SK2. The first stacking structure SK1 is located on the substrate 10 of the peripheral area R2. The second stacking structure SK2 is located on the substrate 10 of the memory surface area R1. The second stacking structure SK2 is surrounded by the first stacking structure SK1. Referring to FIG3J , the first stacking structure SK1 includes a plurality of insulating layers 102 and a plurality of intermediate layers 104 stacked alternately with each other. The second stacking structure SK2 includes a plurality of insulating layers 102 and a plurality of conductive layers 126 stacked alternately with each other. The memory device SM1 may include a plurality of memory cells MC located in an array area AR of a memory area R1.

1 and 3J , a plurality of contact windows COA are disposed in the step region SCR of the memory plane region R1 and are electrically connected to a plurality of conductive layers 126 (as shown in FIG. 3J ).

The memory device SM1 includes a plurality of insulating structures 107A. Each insulating structure 107A surrounds a plurality of contact windows COA to isolate the contact windows COA from the surrounding second stacking structure SK2. The plurality of insulating structures 107A are separated from each other, extend through the second stacking structure SK2 in the step region SCR of the memory plane region R1, and are respectively surrounded by a plurality of insulating layers 102 and a plurality of conductive layers 126.

1 , the memory device SM1 further includes a plurality of insulating structures 107E. The first stacking structure SK1 and the second stacking structure SK2 are separated at the ends of the plurality of array regions AR of the memory plane region R1.

Referring to FIG1 , the memory element SM1 further includes a sealing ring GR and an insulating structure 107G. The sealing ring GR is located in the sealing ring region R3. The sealing ring GR continuously surrounds the first stacking structure SK1. The sealing ring GR can be a single ring (as shown in FIG4O ), or a double ring, including sealing rings GR1 and GR2 (as shown in FIG4P ). The insulating structure 107G is separated from the plurality of insulating structures 107E by the first stacking structure SK1. Referring to FIG1 , the insulating structure 107G surrounds the first stacking structure SK1 and surrounds the sealing ring GR. In other words, the sealing ring GR extends through the insulating structure 107G.

Referring to FIG. 1 , a plurality of through-holes TV and a plurality of insulating structures 107P are disposed in the peripheral region R2. The plurality of through-holes TV and the plurality of insulating structures 107P extend through the first stacking structure SK1. In an embodiment of the present invention, the plurality of insulating structures 107P surround the plurality of through-holes TV. In other words, the plurality of through-holes TV extend through the plurality of insulating structures 107P, as shown in FIG. 3J. The plurality of insulating structures 107P are surrounded by the first stacking structure SK1 retained in the peripheral region R2. The plurality of insulating structures 107P are not connected to each other and are separated from each other by the first stacking structure SK1. The plurality of insulating structures 107P are also separated from the insulating structures 107A, 107E, and 107G by the first stacking structure SK1.

2D , a plurality of insulating structures 107P extend through the first stacking structure SK1 in the peripheral region R2. The plurality of insulating structures 107P are respectively surrounded by a plurality of insulating layers 102 and a plurality of intermediate layers 104. The plurality of insulating structures 107P are separated from each other by the plurality of first insulating layers 102 and the plurality of intermediate layers 104 of the first stacking structure SK1.

1 , the shape of the insulating structure 107P can be a ring, a rectangle, a polygon or a combination thereof. For example, the insulating structure 107P1 of the insulating structure 107P is a ring, and the insulating structure 107P2 is a rectangle.

Referring to FIG. 1 , the insulating structure 107P1 is ring-shaped. The insulating structure 107P1 surrounds a portion of the first stacking structure SK1. Another portion of the first stacking structure SK1 surrounds the insulating structure 107P1. The ring shape can be a square ring, a rectangular ring, a circular ring, an elliptical ring, or a combination thereof. Referring to FIG. 2D , the inner sidewalls SW1 and the outer sidewalls SW2 of the plurality of insulating structures 107P1 are in contact with the plurality of insulating layers 102 and the plurality of intermediate layers 104 of the first stacking structure SK1, respectively.

Referring to FIG1 , the insulating structure 107P2 is a rectangle. The rectangle may be a square or a rectangle, as shown in FIG4A to FIG4N and FIG5A and FIG5B. Referring to FIG2D , the outer side walls SW of the plurality of insulating structures 107P2 are in contact with the plurality of insulating layers 102 and the plurality of intermediate layers 104.

2C , in some embodiments, a ratio of a width (ring width) W1 to a height H1 of the insulating structure 107P1 is less than 2, or a ratio of a width W2 to a height H1 of the insulating structure 107P2 is less than 2.

1 , in the ring-shaped insulating structure 107P1, multiple perforations TV1 can be arranged in order. For example, multiple perforations TV1a are arranged in a single ring, multiple perforations TV1b are arranged in a double ring, and multiple perforations TV1 are arranged in more rings. In the ring-shaped insulating structure 107P1, multiple perforations TV1 can also be arranged in disorder.

Referring to FIGS. 4A to 4N , in each rectangular insulating structure 107P2, there may be only a single perforation TV2 passing through (as shown in FIG. 4A ) or multiple perforations TV2 passing through (as shown in FIG. 4B to 4N ). Multiple perforations TV2 may be arranged in order, for example, in an array (as shown in FIG. 4B to 4N ). Multiple perforations TV2 may also be arranged in disorder (not shown).

Referring to FIG. 5A , a plurality of perforations TV may be distributed in the entire area of the insulating structure 107P. Referring to FIG. 5B , a plurality of perforations TV may be distributed in a local area of the insulating structure 107P, but not in another area. The number of perforations TV in FIG. 5A is the same as the number of perforations TV in FIG. 5B . The length L of the insulating structure 107P in the first direction D1 of FIG. 5A is different from the length L of the insulating structure 107P in the first direction D1 of FIG. 5B . The width W2 of the insulating structure 107P in the second direction D2 of FIG. 5A is the same as the width W2 of the insulating structure 107P in the second direction D2 of FIG. 5B . In other words, the same number of perforations TV may be disposed in different insulating structures 107P of different areas.

The plurality of perforations TV may be uniformly distributed in the entire region of the insulating structure 107P (as shown in FIG. 5A ), or uniformly distributed in a local region of the insulating structure 107P (as shown in FIG. 5B ). In some embodiments (not shown), the plurality of perforations TV may be non-uniformly distributed in the entire region of the insulating structure 107P, or non-uniformly distributed in a local region of the insulating structure 107P.

Referring to FIG1 , each insulating structure 107P in the peripheral region R2 is located around the plurality of through-holes TV and does not occupy too much volume. For example, referring to FIG2D , in some embodiments, the ratio of the width W1 to the height H1 of the plurality of insulating structures 107P is less than 2. Referring to FIG5A and FIG5B , the ratio of the sum of the plurality of diameters d1 of the plurality of through-holes TV2 along the second direction D2 to the width W2 of the insulating structure 107P along the second direction D2 is 0.006-0.15.

1, in an embodiment of the present invention, the plurality of through holes TV in the first stacked structure SK1 in the peripheral region R2 are formed in a plurality of insulating structures 107P rather than in a single block insulating structure. The method of forming the plurality of insulating structures 107P is shown in FIGS. 2A to 2D.

2A to 2D are cross-sectional schematic diagrams of a method for manufacturing a peripheral region of a memory device according to the cut line I-I' of FIG1.

2A , a plurality of insulating layers 102 and a plurality of intermediate layers 104 are alternately stacked on a substrate 100 along a direction D3 to form a first stack structure SK1. Other layers (not shown) may be included between the first stack structure SK1 and the substrate 100, such as a conductor layer, an insulating layer, a device layer, etc. The insulating layer 102 and the intermediate layer 104 are, for example, silicon oxide and silicon nitride, respectively.

A plurality of openings 105P1 and 105P2 are formed in the first stacking structure SK1. The opening 105P1 is, for example, an annular opening, and the opening 105P2 is, for example, a rectangular opening. The volumes of the openings 105P1 and 105P2 are controlled within a certain range to reduce the amount of insulating material subsequently filled into the openings 105P1 and 105P2. In an embodiment of the present invention, the width W1' of the opening 105P1 in the second direction D2 and the width W2' of the opening 105P2 in the second direction D2 are controlled within a certain range. In some embodiments, the ratio of the width W1' of the opening 105P1 to the height H1' of the first stacking structure SK1 is, for example, less than 2. The ratio of the width W2' of the opening 105P2 to the height H1' of the first stacking structure SK1 is, for example, less than 2. If the ratio is greater than 2, the amount of insulating material subsequently filled in the openings 105P1 and 105P2 will increase.

On the other hand, the lengths of the openings 105P1 and 105P2 in the first direction D1 can be relatively flexible and are not strictly limited. Referring to FIG. 5A and FIG. 5B , for example, the length L’ of the opening 105P2 in the first direction D1 can be shorter (as shown in FIG. 5A ) or longer (as shown in FIG. 5B ). This is because the thickness of the insulating material 107 (as shown in FIG. 2B ) subsequently filled in is related to the width W2’ of the opening 105P2 in the second direction D2, but has little to do with the length L’ of the opening 105P2 in the first direction D1. In other words, regardless of the length L’ of the opening 105P2, as long as the thickness of the insulating material 107 is greater than 1/2 of the width W2’, the opening 105P2 can be filled.

Referring to FIG. 2B , an insulating material 107 is then formed on the first stacking structure SK1. The insulating material 107 extends continuously on the first stacking structure SK1 and fills the openings 105P1 and 105P2. The insulating material 107 is, for example, silicon oxide. Since the first portion m1 of the first stacking structure SK1 is still left in the annular opening 105P1, the two rectangular openings 105P2 are separated by the second portion m2 of the first stacking structure SK1, and the third portion m3 of the first stacking structure SK1 is still left between the rectangular opening 105P2 and the annular opening 105P1, the amount of the insulating material 107 required can be reduced.

2C , a chemical mechanical polishing process or an etching back process is performed to remove the excess insulating material 107 on the first stacked structure SK1 to form insulating structures 107P1 and 107P2 at the openings 105P1 and 105P2. In some embodiments, the ratio of the width (ring width) W1 of the insulating structure 107P1 to the height H1 is less than 2. The ratio of the width W2 of the insulating structure 107P2 to the height H1 is less than 2.

Referring to FIG. 2D , a dielectric layer 128, a stop layer 129, and a dielectric layer 130 are formed on the first stack structure SK1. The dielectric layer 128, the stop layer 129, and the dielectric layer 130 are, for example, silicon oxide, silicon nitride, or silicon nitride. Afterwards, through holes TV1b and TV2 are formed in the insulating structures 107P1 and 107P2. The through holes TV1b and TV2 are formed by, for example, forming a plurality of through hole openings in the dielectric layer 128, the stop layer 129, the dielectric layer 130, and the insulating structures 107P1 and 107P2, and then filling the plurality of through hole openings with metal materials, and then performing a chemical mechanical polishing process or an etching back process. The metal material is, for example, tungsten.

1 , in the embodiment of the present invention, the first stacking structure SK1 is retained in the peripheral region R2. The through holes TV in the peripheral region R2 are isolated from each other by a plurality of insulating structures 107P. The plurality of insulating structures 107P are separated from each other and from the plurality of insulating structures 107A, 107E, 107G. The plurality of insulating structures 107P can be formed simultaneously when the plurality of insulating structures 107A, 107E, and 107G are formed.

3A to 3J are cross-sectional schematic diagrams of a method for manufacturing a memory device according to an embodiment of the present invention.

Referring to FIG. 3A , a substrate 10 is provided. The substrate 10 may be a semiconductor substrate, such as a silicon-containing substrate. A component layer 20 is formed on the substrate 10. The component layer 20 may include active components or passive components. The active components are, for example, transistors, diodes, etc. The passive components are, for example, capacitors, inductors, etc. The transistor may be an N-type metal oxide semiconductor (NMOS) transistor, a P-type metal oxide semiconductor (PMOS) transistor, or a complementary metal oxide semiconductor (CMOS) component.

3A , a first portion 30 a of an internal connection structure 30 is formed on the component layer 20. The first portion 30 a of the internal connection structure 30 may include multiple dielectric layers (not shown) and internal connections (not shown) formed in the multiple dielectric layers. The internal connections include multiple plugs (not shown) and multiple wires (not shown). The dielectric layer separates adjacent wires. The wires may be connected by plugs, and the wires may be connected to the component layer 20 by plugs. The first portion 30 a of the internal connection structure 30 may be formed by a single metal inlay, a dual metal inlay process, or any known method.

Referring to FIG. 3A , a first portion 32a of a bonding structure 32 (shown in FIG. 3J ) is formed on a first portion 30a of an inner connection structure 30. The first portion 32a of the bonding structure 32 includes a bonding layer 34a, a bonding plug 36a, and a bonding pad 38a. The bonding layer 34a is, for example, silicon oxide, silicon nitride, or a combination thereof. The bonding plug 36a and the bonding pad 38a are, for example, copper. The bonding pad 38a is connected to the topmost wire 31a of the first portion 30a of the inner connection structure 30 via the bonding plug 36a. The bonding pad 38a and the bonding plug 36a can be formed by single inlay or double inlay. The bonding pad 38a, the bonding plug 36a, and the bonding layer 34a can be planarized and coplanar by a chemical mechanical polishing process.

3A, another substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon-containing substrate. An insulating layer 101 and a stop structure 103 are formed on the substrate 100. The insulating layer 101 is, for example, silicon oxide. The stop structure 103 is formed on the insulating layer 101. The stop structure 103 may include a plurality of insulating layers 92 and a plurality of conductive layers 94 alternately stacked on each other. The insulating layer 92 is, for example, silicon oxide, and the conductive layer 94 is, for example, polycrystalline silicon.

3A , a lower portion LP of a stacked structure (or first stacked structure) SK1 is formed on the surface of the stop structure 103. The lower portion LP of the stacked structure SK1 includes a plurality of insulating layers 102 and a plurality of intermediate layers 104 alternately stacked with each other. In some embodiments, the material of the insulating layer 102 includes silicon oxide, and the material of the intermediate layer 104 includes silicon nitride. The intermediate layer 104 can be used as a sacrificial layer, which will be partially removed in a subsequent process.

Referring to FIG. 3A , a plurality of dummy columns DVC are then formed to extend through the lower LP of the stacked structure SK1. The plurality of dummy columns DVC can be formed into an opening (not shown) through a single-stage lithography and etching process or a multi-stage lithography and etching process. The opening extends through the lower LP of the stacked structure SK1 to the stop structure 103, and even to the insulating layer 101. Then, a filling material (or self-alignment material) is filled into the opening to form it. The profile of the sidewall of the opening formed by the multi-stage lithography and etching process is, for example, in the shape of a bamboo node.

3B , an upper portion UP of the stacked structure SK1 is formed on the substrate 100. The upper portion UP of the stacked structure SK1 includes a plurality of insulating layers 102 and a plurality of intermediate layers 104 stacked on each other. The materials of the insulating layers 102 and the intermediate layers 104 of the upper portion UP of the stacked structure SK1 are the same as the materials of the insulating layers 102 and the intermediate layers 104 of the lower portion LP of the stacked structure SK1. Thereafter, a hard mask layer HM is formed on the upper portion UP of the stacked structure SK1. The hard mask layer HM is, for example, polycrystalline silicon.

Referring to FIG. 3C , the hard mask layer HM is then patterned. The hard mask layer HM is then used as a mask to pattern the middle layer 104 and the insulating layer 102 of the stacking structure SK1 to form an opening 105A and a step structure SC in the memory surface area R1, and an opening 105P is formed in the peripheral area R2, and an opening 105E is formed at the end of the memory surface area R1. In some embodiments, the opening 105A and the step structure SC can be formed by a multi-stage patterning process, but the present invention is not limited thereto. The openings 105P and 105E are separated by a portion of the stacking structure SK1. The patterning process may include processes such as lithography, etching, and trimming.

3D and 3E , an insulating material 107 is formed on the stacked structure SK1 and fills the openings 105A, 105P, and 105E. The insulating material 107 is, for example, silicon oxide. A planarization process is then performed, such as a chemical mechanical polishing process, using the hard mask layer HM as a polishing stop layer to remove excess insulating material 107, so as to form insulating structures 107A, 107P, and 107E in the openings 105A, 105P, and 105E, respectively.

Referring to FIG. 3F , the hard mask layer HM is removed. Thereafter, a patterning process is performed to remove a portion of the stacked structure SK1 to form an opening (not shown) and expose the dummy column DVC. Next, the dummy column DVC exposed by the opening is removed to form one or more openings 106 extending through the stacked structure SK1. In one embodiment, the opening 106 may have slightly inclined side walls. In another embodiment, the opening 106 may have substantially vertical side walls (not shown). In one embodiment, the opening 106 is also referred to as a vertical channel (VC) hole. In one embodiment, the opening 106 can be formed by a single-stage lithography and etching process. In another embodiment, the opening 106 is formed by multiple-stage lithography and etching processes. The profile of the sidewall of the opening 106 formed by multiple stages of lithography and etching processes is, for example, a bamboo-node shape.

Referring to FIG. 3F , a charge storage structure 108 is then formed in the opening 106. The charge storage structure 108 contacts the insulating layer 102 and the intermediate layer 104. In one embodiment, the charge storage structure 108 is an oxide/nitride/oxide (ONO) composite layer. The charge storage structure 108 is, for example, a conformal layer formed on the sidewalls and bottom surface of the opening 106. A vertical channel column CP is then formed in the remaining space of the opening 106. The vertical channel column CP can be formed by the following method.

Continuing with reference to FIG. 3F , a channel layer 110 is formed on the inner sidewall and bottom surface of the charge storage structure 108. In one embodiment, the material of the channel layer 110 includes undoped polysilicon. Next, an insulating column (or core insulating column) 112 is formed on the inner surface of the channel layer 110. In one embodiment, the material of the insulating column 112 includes silicon oxide. Thereafter, a channel plug 114 is formed in the opening 106, and the channel plug 114 contacts the channel layer 110. The channel plug 114 extends from the top surface of the uppermost insulating layer 102 to a certain depth of the opening 106. In one embodiment, the material of the channel plug 114 includes a semiconductor material with doping, such as polysilicon with doping. The channel layer 110, the insulating column 112 and the channel plug 114 can be collectively referred to as a vertical channel column CP. The vertical channel column CP passes through the stacked structure SK1 and extends to the stop structure 103 and even to the insulating layer 101. The charge storage structure 108 surrounds the vertical outer surface of the vertical channel column CP.

Referring to FIG. 3G , a dielectric layer 128 is formed on the stacked structure SK1. The dielectric layer 128 is, for example, silicon oxide. Thereafter, a patterning process is performed to form one or more separation trenches 116. The separation trenches 116 extend through the dielectric layer 128 and the stacked structure SK1 to divide the stacked structure SK1 into a plurality of blocks (not shown). The separation trenches 116 may have wavy sidewalls, vertical sidewalls (not shown), or slightly inclined sidewalls (not shown).

Continuing with reference to FIG. 3G , a replacement process is performed to replace part of the middle layer 104 with the conductive layer 126. First, a selective etching process is performed so that the etchant contacts the middle layer 104 of the stacked structure SK1 on both sides through the separation trenches 116. Thereby, part of the middle layer 104 is removed to form a plurality of horizontal openings (not shown), leaving the middle layer 104 in the peripheral area R2. The selective etching process may be an isotropic etching, such as a wet etching process. The etchant used in the wet etching process may be, for example, hot phosphoric acid. Then, a conductive layer 126 is formed in the horizontal openings. The conductive layer 126 may serve as a gate layer. The conductive layer 126 includes, for example, a barrier layer and a metal layer. In one embodiment, the barrier layer is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The metal layer is made of tungsten (W). A portion of the intermediate layer 104 is replaced by the conductive layer 126, thereby forming a stacking structure (also referred to as a second stacking structure) SK2.

The stacking structure SK2 and the stacking structure SK1 together form a composite stacking structure CSK. The stacking structure SK1 includes a plurality of alternately stacked insulating layers 102 and a plurality of intermediate layers 104. The stacking structure SK2 includes a plurality of alternately stacked insulating layers 102 and a plurality of conductive layers 126. A plurality of vertical channel pillars CP extend through the stacking structure SK2.

Referring to Figure 3G, then, a separation wall SLIT is formed in the separation trench 116. The separation wall SLIT may include a dielectric material and a conductive material. The dielectric material is, for example, silicon nitride or a silicon oxide/silicon nitride/silicon oxide composite material. The conductive material is, for example, doped polysilicon. The conductive material of the separation wall SLIT is isolated by the dielectric material to avoid contact with the conductive layer 126. Thereafter, a stop layer 129 is formed on the dielectric layer 128 to cover the top surface of the separation wall SLIT. The stop layer 129 is, for example, silicon nitride. A dielectric layer 130 is formed on the stop layer 129. The dielectric layer 130 is, for example, silicon oxide.

Referring to FIG. 3G and FIG. 3H , multiple contact windows COA are then formed from the dielectric layer 130 to the insulating structure 107A to electrically connect the conductive layer 126 and the vertical channel pillars CP, respectively. In addition, multiple through holes TV are formed from the dielectric layer 130 to the insulating structure 107P. The contact window COA and the through hole TV may be formed by first forming a contact window hole and a through hole opening, and then forming a conductive material on the dielectric layer 130, and the conductive material is also filled into the contact window hole and the through hole opening. Afterwards, an etch back or chemical mechanical polishing process is performed to remove the conductive material on the dielectric layer 130.

Referring to FIG. 3I , a second portion 32 b of the interconnect structure 30 is formed above the substrate 100. The second portion 32 b of the interconnect structure 30 may include multiple dielectric layers (not shown) and interconnects (not shown) formed in the multiple dielectric layers. The interconnects include multiple plugs (not shown) and multiple wires (not shown), etc. The dielectric layer separates adjacent wires. The wires may be connected by plugs, and the wires may be connected to the contact window COA by the plugs. The second portion 30 b of the interconnect structure 30 may be formed by a single metal inlay, a dual metal inlay process, or any known method. The second portion 32 b of the interconnect structure 30 may include a local bit line LBL and a local source line LSL. The local bit line LBL and the local source line LSL may be electrically connected to the vertical channel pillar CP via the contact window COA.

3I , a second portion 32b of a bonding structure 32 (shown in FIG. 3J ) is formed on the second portion 30b of the interconnect structure 30. The second portion 32b of the bonding structure 32 includes a bonding layer 34b, a bonding plug 36b, and a bonding pad 38b. The bonding pad 38b is connected to the topmost wire 31b of the second portion 30b of the interconnect structure 30 via the bonding plug 36b. The materials and formation methods of the bonding layer 34b, the bonding plug 36b, and the bonding pad 38b may be the same or similar to the materials and formation methods of the bonding layer 34a, the bonding plug 36a, and the bonding pad 38a.

Referring to FIG. 3J , the substrate 100 is flipped. The step structure SC on the flipped substrate 100 becomes a reverse step structure RSC. The contact window COA is below the reverse step structure RSC. Next, referring to FIG. 3I and FIG. 3J , the second portion 32b of the bonding structure 32 is bonded to the first portion 32a of the bonding structure 32 to form the bonding structure 32. In the bonding structure 32, the bonding layer 34b is bonded to the bonding layer 34a, and the bonding pad 38b is bonded to the bonding pad 38a. The bonding layer 34b and the bonding layer 34a can be bonded by dielectric-to-dielectric. The bonding pad 38b and the bonding pad 38a can be bonded by metal-to-metal. The bonding structure 32 is located in the interconnect structure 30, between the first portion 32a and the second portion 32b of the interconnect structure 30. The bonding structure 32, the first portion 32a and the second portion 32b form the interconnect structure 30. Since the device layer 20 is, for example, a complementary metal oxide semiconductor device (CMOS), the device layer 20 is bonded to the memory array by bonding (for example, located below the stacking structure SK2 of FIG. 3J ), such a structure can also be referred to as a CMOS-Bonded-Array (CbA) structure.

3J , the substrate 100 is then removed to expose the insulating layer 101. The substrate 100 may be removed by grinding, polishing or etching.

Referring to FIG. 3J , a liner 44, a contact window 46, a wire 48, and a dielectric layer 50 of an internal connection structure 40 are formed on an insulating layer 101. The contact window 46 electrically connects the through hole TV and the wire 48. The contact window 46 is electrically isolated by the liner 44 and the conductive layer 94 of the stop structure 103. The method for forming the internal connection structure 40 is described as follows. First, a lithography and etching process is performed to form a contact window opening 43 in the insulating layer 101 and the stop structure 103. Then, a liner 44 and a contact window 46 are formed in the contact window opening 43. The formation method of the liner 44 is, for example, forming a dielectric material on the insulating layer 101 and in the contact window opening 43, and then performing anisotropic etching. The formation method of the contact window 46 is, for example, forming a conductive material on the insulating layer 101 and in the contact window opening 43, and then performing a chemical mechanical polishing process or etching back. The dielectric material is, for example, silicon nitride or a silicon oxide/silicon nitride/silicon oxide composite layer. The conductive material is, for example, doped polysilicon. Thereafter, a wire 48 and a dielectric layer 50 are formed on the insulating layer 101. The material of the wire 48 is, for example, copper or tungsten. The dielectric layer 50 can be a single layer or multiple layers. The material of the dielectric layer 50 can be silicon oxide, silicon oxynitride, silicon nitride or a combination thereof. The interconnect structure 40 can be electrically connected to the interconnect structure 30 via the through-hole TV. In addition to connecting the through-hole, the interconnect structure 30 can also be electrically connected to the vertical channel column CP or the conductive layer 126 via the contact window COA. At this point, the fabrication of the memory element SM2 is completed.

3J , the memory device SM2 is a CMOS-Bonded-Array (CbA) structure. However, the present invention is not limited thereto.

6 , in some other embodiments, the present invention can also be used in a structure where the device layer 20 is formed below the memory array. This structure can also be called a complementary metal oxide semiconductor device below the memory array (CMOS-Under-Array, CUA) structure.

6 , the stacking structure SK1 is formed above the interconnect structure 30 on the substrate 10. A device layer 20 is formed between the interconnect structure 30 below the stacking structure SK1 and the substrate 10. The step structure SC, the insulating structures 107A, 107E, 107P, the vertical channel pillars CP, the stacking structure SK2, the contact window COA and the through hole TV are formed by a method similar to the above embodiment.

Next, a dielectric layer 60, a contact window 46 connected to the through hole TV, a bit line (not shown), a source line (not shown), and an internal connection structure 40 are formed.

In summary, the stacked structure of the embodiment of the present invention is retained in the peripheral area. The perforations in the peripheral area are isolated from each other by multiple insulating structures. The multiple insulating structures are separated from each other. The multiple insulating structures are formed by removing a small portion of the stacked structure in the peripheral area and then backfilling a small amount of insulating material. Therefore, the deposition amount of insulating material can be reduced, and the time for grinding and removing excess insulating material can be reduced.

10, 100: substrate 20: component layer 30, 40: internal connection structure 30a, 32a: first part 30b, 32b: second part 31a: topmost wire 31b: topmost wire 32: bonding structure 34a, 34b: bonding layer 36a, 36b: bonding plug 38a, 38b: bonding pad 43: contact window opening 44: liner 46, COA: contact window 48: wire 50, 60, 128, 130: dielectric layer 92, 101, 102: insulation layer 94, 126: conductor layer 103: stop structure 104: Intermediate layer 105A, 105E, 105P, 105P1, 105P2, 106: Opening 107: Insulating material 107A, 107E, 107G, 107P, 107P1, 107P2: Insulating structure 108: Charge storage structure 110: Channel layer 112: Insulating column 114: Channel plug 116: Separation trench 129: Stop layer AR: Array area CP: Vertical channel column CSK: Composite stacking structure D1, D2, D3: Direction d1: Diameter DVC: Virtual column GR, GR1, GR2: Sealing ring H1, H1’: height HM: hard mask layer LBL: local bit line LP: lower part LSL: local source line MC: memory cell m1: first part m2: second part m3: third part R1: memory surface area R2: peripheral area R3: sealing ring area RSC: reverse staircase structure SC: staircase structure SCR: staircase area SK1: first stacking structure/stacking structure SK2: second stacking structure/stacking structure SLIT: partition wall SM1, SM2: memory element SW1: inner wall SW, SW2: outer wall TV, TV1, TV1a, TV1b, TV2: perforation UP: upper part W1, W1’, W2, W2’: width L, L’: length I-I’: tangent

FIG. 1 is a top view of a memory element according to an embodiment of the present invention. FIG. 2A to FIG. 2D are schematic cross-sectional views of a method for manufacturing a peripheral region of a memory element according to the tangent line I-I' of FIG. 1. FIG. 3A to FIG. 3J are schematic cross-sectional views of a method for manufacturing a memory element according to an embodiment of the present invention. FIG. 4A to FIG. 4N are top views of various perforations and insulating structures according to an embodiment of the present invention. FIG. 4O to FIG. 4P are top views of various sealing rings and insulating structures according to an embodiment of the present invention. FIG. 5A and FIG. 5B are top views of various perforations and insulating structures according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a memory element according to an embodiment of the present invention.

10: Base

107A, 107E, 107G, 107P, 107P1, 107P2: Insulation structure

GR1, GR2: Sealing ring

SK1: First stacking structure/stacked structure

SK2: Second stacking structure/stacking structure

CSK: composite stacking structure

TV, TV1, TV1a, TV1b, TV2: perforation

AR: Array Area

SCR: Step Area

MC: memory unit

SW1: Inner wall

SW2: Outer wall

SW: Outer wall

COA: Contact Window

I-I’: tangent line

SW: medial wall

R3: Sealed ring area

R2: Peripheral area

R1: Memory area

SM1: memory element

W1, W2: Width

L: Length

Claims (14)

A memory element comprises: a substrate including a memory surface area and a peripheral area; and a composite stacking structure located on the substrate in the memory surface area and the peripheral area, wherein the composite stacking structure comprises: a first stacking structure including a plurality of first insulating layers and a plurality of intermediate layers stacked alternately with each other and located on the substrate in the peripheral area; a plurality of first insulating structures separated from each other, extending through the first stacking structure in the peripheral area, and respectively surrounded by the plurality of first insulating layers and the plurality of intermediate layers; and a plurality of through holes extending through one of the plurality of first insulating structures. A memory element as described in claim 1, wherein the plurality of first insulating structures are separated from each other by the plurality of first insulating layers and the plurality of intermediate layers of the first stacking structure. A memory element as described in claim 1, wherein the shapes of the multiple first insulating structures include rectangles, and the outer side walls of the multiple first insulating structures are in contact with the multiple first insulating layers and the multiple intermediate layers. A memory element as described in claim 1, wherein the ratio of the width to the height of the plurality of first insulating structures is less than 2. A memory element as described in claim 1, wherein the ratio of the sum of the multiple diameters of the multiple through-holes along the first direction to the width of the corresponding first insulating structure along the first direction is 0.006-0.15. A memory element as described in claim 1, wherein the shapes of the multiple first insulating structures include rings, and the inner side walls and outer side walls of the multiple first insulating structures are in contact with the multiple first insulating layers and the multiple intermediate layers, respectively. A memory element as described in claim 1, wherein the plurality of first insulating structures are separated from each other by the first stacking structure. The memory element as described in claim 1, wherein the composite stacking structure further includes: a second stacking structure, including the plurality of first insulating layers and the plurality of conductive layers alternately stacked with each other, and located on the substrate of the memory surface area. A memory element as described in claim 8, wherein the second stacking structure is surrounded by the first stacking structure. The memory element as described in claim 8 further includes: a plurality of second insulating structures, separated from each other, extending through the second stacking structure in the step area of the memory surface area, and respectively surrounded by the plurality of second insulating structures and the plurality of conductive layers; and a plurality of contact windows, extending through one of the plurality of first insulating structures, and electrically connected to the plurality of conductive layers. The memory element as described in claim 8 further includes a plurality of third insulating structures separating the first stacking structure from the second stacking structure at the ends of the plurality of array regions of the memory plane region. The memory device as described in claim 11 further includes: a fourth insulating structure surrounding the first stacking structure; and a sealing ring extending through the fourth insulating structure. A memory element as described in claim 12, wherein the fourth insulating structure is separated from the plurality of third insulating structures by the first stacking structure. A memory element as described in claim 12, wherein the fourth insulating structure is separated from the plurality of first insulating structures by the first stacking structure.