TWI841201B - Semiconductor structure and method of forming the same - Google Patents

Abstract

The disclosure provides a semiconductor structure and a method of forming the same. A method of forming a semiconductor structure includes forming a dielectric stack over a conductive layer, wherein forming the dielectric stack includes forming a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer and a third support layer in sequence. A bottom electrode layer is formed in the dielectric stack, wherein the bottom electrode layer has a first critical dimension in the first support layer. The bottom electrode layer and the third support are etched to form a first hole exposing the second sacrificial layer. The second sacrificial layer is removed through the first hole. The second support layer is etched to form a second hole exposing the first sacrificial layer. The first sacrificial layer is removed through the second hole. The bottom electrode layer is trimmed such that the bottom electrode layer has a second critical dimension between the first support layer and the second support layer that is smaller than the first critical dimension.

Description

Semiconductor structure and method for forming the same

The present disclosure relates to a semiconductor structure and a method of forming the semiconductor structure.

Capacitors can be used in a variety of different semiconductor circuits. For example, capacitors can be used in dynamic random access memory (DRAM) memory circuits or any other type of memory circuit. DRAM memory circuits can be manufactured by replicating millions of identical circuit elements (called DRAM cells) on a single semiconductor wafer. A DRAM cell is an addressable location that can store bits of data (binary bits). In its common form, a DRAM cell can include two circuit components: a storage capacitor and an access field effect transistor.

However, existing capacitors face many problems due to process limitations. For example, if the critical size of the lower electrode layer of the capacitor is too large, the capacitor may short-circuit. Therefore, it is expected to improve the process of capacitors and develop improved semiconductor structures.

The present invention discloses a method for forming a semiconductor structure.

According to some embodiments of the present disclosure, a method for forming a semiconductor structure includes forming a dielectric stack on a conductive layer, wherein the dielectric stack includes a first supporting layer, a first sacrificial layer, a second supporting layer, a second sacrificial layer, and a third supporting layer formed in sequence. A lower electrode layer is formed in the dielectric stack, wherein the lower electrode layer has a first critical dimension in the first supporting layer. The lower electrode layer and the third supporting layer are etched to form a first hole and expose the second sacrificial layer. The second sacrificial layer is removed through the first hole. The second supporting layer is etched to form a second hole and expose the first sacrificial layer. The first sacrificial layer is removed through the second hole. The lower electrode layer is trimmed so that the lower electrode layer has a second critical dimension between the first supporting layer and the second supporting layer that is smaller than the first critical dimension.

In some embodiments of the present disclosure, trimming the lower electrode layer is performed by performing a wet etching process.

In some embodiments of the present disclosure, a wet etching process is performed using an alkaline etching solution.

In some embodiments of the present disclosure, the lower electrode layer is trimmed so that the lower electrode layer has a third critical dimension between the second supporting layer and the third supporting layer that is smaller than the first critical dimension.

In some embodiments of the present disclosure, the method of forming a semiconductor structure further includes forming a high-k dielectric layer along a sidewall of the lower electrode layer and forming an upper electrode layer along a sidewall of the high-k dielectric layer.

In some embodiments of the present disclosure, forming the first hole further includes etching the second sacrificial layer.

The technical aspect disclosed herein is a method of a semiconductor structure.

According to some embodiments of the present disclosure, a method for forming a semiconductor structure includes a first supporting layer, a second supporting layer, a third supporting layer, and a capacitor. The first supporting layer, the second supporting layer, and the third supporting layer are arranged from bottom to top, and the first supporting layer, the second supporting layer, and the third supporting layer are separated from each other. The capacitor contacts the sidewall of the first supporting layer, the sidewall of the second supporting layer, and the sidewall of the third supporting layer, wherein the capacitor includes a lower electrode layer extending from the first supporting layer to the third supporting layer, a high dielectric constant dielectric layer along the sidewall of the lower electrode layer, and an upper electrode layer along the sidewall of the high dielectric constant dielectric layer, wherein the lower electrode layer has a first critical dimension in the first supporting layer, and the lower electrode layer has a second critical dimension between the first supporting layer and the second supporting layer that is smaller than the first critical dimension.

In some embodiments of the present disclosure, the lower electrode layer has a third critical size between the second supporting layer and the third supporting layer that is smaller than the first critical size.

In some embodiments of the present disclosure, the lower electrode layer has a fourth critical dimension in the second supporting layer that is larger than the second critical dimension.

In some embodiments of the present disclosure, the lowest surface of the high-k dielectric layer contacts the surface of the lower electrode layer.

According to the above-mentioned embodiments of the present disclosure, the critical dimension of the lower electrode layer can be controlled or reduced by trimming the lower electrode layer (for example, the second critical dimension of the lower electrode layer between the first supporting layer and the second supporting layer is smaller than the first critical dimension in the first supporting layer), thereby avoiding capacitor short circuit.

It should be understood that both the foregoing general description and the following detailed description are exemplary only, and are intended to provide further explanation of the present disclosure.

The following will disclose multiple embodiments of the present disclosure with drawings. For the purpose of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not necessary and therefore should not be used to limit the present disclosure. In addition, in order to simplify the drawings, some commonly used structures and components will be depicted in the drawings in a simple schematic manner. In addition, in order to facilitate the reader's viewing, the size of each component in the drawings is not drawn according to the actual scale.

As used herein, "about", "approximately" or "substantially" shall generally refer to within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The numerical values given herein are approximate, meaning that if not explicitly stated, the meaning of the term "about", "approximately" or "substantially" can be inferred.

Additionally, for ease of description, spatially relative terms such as "under," "beneath," "below," "above," "upper," and the like may be used in some embodiments of the present disclosure to describe the relationship of one element or feature to another element(s) or feature(s) as depicted in the figures. Such spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. Elements may be otherwise positioned (rotated 90 degrees or in other orientations) and such spatially relative descriptors used in some embodiments of the present disclosure interpreted accordingly.

FIG. 1 to FIG. 11 are cross-sectional views of various intermediate stages of a method for forming a semiconductor structure according to some embodiments of the present disclosure. Referring to FIG. 1 , a dielectric stack DS is formed on a conductive layer 112. Specifically, a conductive layer 112 is first formed on a substrate 110, and then a dielectric stack DS is formed on the conductive layer 112. Forming the dielectric stack DS on the conductive layer 112 includes forming a first supporting layer 120 on the conductive layer 112, forming a first sacrificial layer 130 on the first supporting layer 120, forming a second supporting layer 140 on the first sacrificial layer 130, forming a second sacrificial layer 150 on the second supporting layer 140, and forming a third supporting layer 160 on the second sacrificial layer 150. In other words, the dielectric stack DS includes the first supporting layer 120, the first sacrificial layer 130, the second supporting layer 140, the second sacrificial layer 150, and the third supporting layer 160 formed in sequence.

In some embodiments, the conductive layer 112 contacts the first support layer 120 of the dielectric stack DS. The conductive layer 112 may include tungsten (W) or other suitable metals. In some embodiments, the substrate 110 includes an interconnect structure having contacts, transistors, or other similar components. Therefore, the capacitors (e.g., capacitors Ca in FIG. 10 and FIG. 11 ) subsequently formed in the dielectric stack DS are connected to other components (e.g., transistors) in the substrate 110.

In some embodiments, the first supporting layer 120, the second supporting layer 140, and the third supporting layer 160 are arranged from bottom to top and are separated from each other. In some embodiments, the first supporting layer 120, the second supporting layer 140, and the third supporting layer 160 are formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or similar deposition methods. The first supporting layer 120, the second supporting layer 140, and the third supporting layer 160 include nitride, such as silicon nitride. In some embodiments, the first sacrificial layer 130 and the second sacrificial layer 150 are formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition, or similar deposition methods. The first sacrificial layer 130 and the second sacrificial layer 150 include oxides. The first sacrificial layer 130 and the second sacrificial layer 150 can be made of different materials. When forming the first sacrificial layer 130, a dopant is doped into the first sacrificial layer 130, and the dopant includes boron, phosphorus, or a combination thereof. For example, the first sacrificial layer 130 is made of boro-phospho-silicate-glass (BPSG), which is silicon oxide doped with boron and phosphorus. In some embodiments, the second sacrificial layer 150 is made of silane (SiH ₄ ) oxide or other suitable oxide materials.

2 , the dielectric stack DS is etched to form an opening 170 in the dielectric stack DS. In other words, the opening 170 is formed in the first supporting layer 120, the first sacrificial layer 130, the second supporting layer 140, the second sacrificial layer 150, and the third supporting layer 160. In some embodiments, the opening 170 extends downward from the third supporting layer 160 to the conductive layer 112 and exposes the conductive layer 112. The opening 170 may expose the sidewall DS1 of the dielectric stack DS. In some embodiments, etching the dielectric stack DS to form the opening 170 is performed by performing a dry etching process. For example, dry etching gases such as hydrogen (H ₂ ) and nitrogen (N ₂ ) may be selected for the dry etching process.

2 and 3 , a conductive material is filled into the opening 170 to form a lower electrode layer 180 in the opening 170 and on the third supporting layer 160. The lower electrode layer 180 covers the top surface 161 of the third supporting layer 160, and the lower electrode layer 180 contacts the sidewall DS1 of the dielectric stack DS and the top surface of the conductive layer 112. In some embodiments, the lower electrode layer 180 is formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a similar deposition method.

In some embodiments, the lower electrode layer 180 has a first critical dimension W1 in the dielectric stack DS. In detail, as shown in FIG. 2 and FIG. 3 , the opening 170 has a first critical dimension (width) W1 in the dielectric stack DS in a direction extending parallel to the length of the substrate 110, and thus the lower electrode layer 180 also has a first critical dimension W1 in the dielectric stack DS. The lower electrode layer 180 has a first critical dimension W1 in the first supporting layer 120, the first sacrificial layer 130, the second supporting layer 140, the second sacrificial layer 150, and the third supporting layer 160. That is, the lower electrode layer 180 has substantially the same critical size in the first supporting layer 120, the first sacrificial layer 130, the second supporting layer 140, the second sacrificial layer 150, and the third supporting layer 160. It should be understood that the "critical size" of the lower electrode layer 180 disclosed herein can be interchangeably referred to as the width of the lower electrode layer 180. In some embodiments, the lower electrode layer 180 includes titanium nitride (TiN) or other suitable conductive materials.

Referring to FIG. 4 , the lower electrode layer 180 and the third supporting layer 160 are etched to form the first hole H1 and expose the second sacrificial layer 150. In some embodiments, forming the first hole H1 further includes etching a portion of the second sacrificial layer 150. As a result, the remaining second sacrificial layer 150 has a stepped profile (i.e., an exposed top surface and an exposed sidewall perpendicular to the exposed top surface). In some embodiments, forming the first hole H1 is performed by a dry etching process. The etching gas for forming the first hole H1 may include a gas composed of carbon (C) and fluorine (F), such as carbon tetrafluoride (CF ₄ ).

Referring to FIGS. 4 and 5 , the second sacrificial layer 150 of the dielectric stack DS is removed through the first hole H1. In some embodiments, an etching process is performed to remove the entire second sacrificial layer 150. For example, the second sacrificial layer 150 is removed by using a wet etching process, and the etching solution of the wet etching process includes a fluoride-based solution, such as hydrofluoric acid (HF). After the second sacrificial layer 150 is removed, a space S1 is formed between the second supporting layer 140 and the third supporting layer 160.

Referring to FIGS. 5 and 6 , the second supporting layer 140 is etched to form a second hole H2 in the second supporting layer 140 and expose the first sacrificial layer 130. In some embodiments, forming the second hole H2 further includes etching a portion of the first sacrificial layer 130. As a result, the remaining first sacrificial layer 130 has an inverted U-shaped profile (i.e., an exposed bottom surface and an exposed sidewall connected to the exposed bottom surface). In some embodiments, forming the second hole H2 is performed by a dry etching process. The etching gas for forming the second hole H2 may include a gas composed of carbon (C) and fluorine (F), such as carbon tetrafluoride (CF ₄ ).

In some embodiments, as shown in FIGS. 5 and 6 , after forming the second hole H2 in the second supporting layer 140, the portion of the lower electrode layer 180 located above the third supporting layer 160 is removed. As a result, the top surface 161 of the third supporting layer 160 is exposed, and the top surface 181 of the lower electrode layer 180 is substantially coplanar with the top surface 161 of the third supporting layer 160. In some embodiments, removing the portion of the lower electrode layer 180 located above the third supporting layer 160 is performed by a dry etching process. In some embodiments, removing the portion of the lower electrode layer 180 located above the third supporting layer 160 and forming the second hole H2 are performed by using a single dry etching process.

Referring to FIGS. 6 and 7 , the first sacrificial layer 130 of the dielectric stack DS is removed through the second hole H2. In some embodiments, an etching process is performed to remove the entire first sacrificial layer 130. For example, the first sacrificial layer 130 is removed by using a wet etching process, and the etching solution of the wet etching process includes a fluoride-based solution, such as hydrofluoric acid (HF). After removing the first sacrificial layer 130, a space S2 is formed between the second supporting layer 140 and the first supporting layer 120, and the space S1 and the space S2 are connected through the second hole H2 in the second supporting layer 140. The first supporting layer 120 , the second supporting layer 140 and the third supporting layer 160 are connected via the lower electrode layer 180 .

Referring to FIGS. 6 to 8 , after removing the first sacrificial layer 130, the lower electrode layer 180 is trimmed. In detail, the lower electrode layer 180 is trimmed to reduce the critical dimension (width) of the lower electrode layer 180 in the dielectric stack DS. A portion 183 of the lower electrode layer 180 between the first supporting layer 120 and the second supporting layer 140 has a second critical dimension W2, and the second critical dimension W2 is smaller than the first critical dimension W1 of a portion 182 of the lower electrode layer 180 in the first supporting layer 120. In this way, short circuiting of a capacitor (e.g., capacitor Ca of FIGS. 10 and 11 ) formed subsequently can be avoided.

In some embodiments, the lower electrode layer 180 is trimmed so that a portion 186 of the lower electrode layer 180 between the second supporting layer 140 and the third supporting layer 160 has a third critical dimension W3 that is smaller than the first critical dimension W1. In some embodiments, the third critical dimension W3 is substantially equal to the second critical dimension W2. In some other embodiments, the third critical dimension W3 is greater than the second critical dimension W2.

In some embodiments, a portion 185 of the lower electrode layer 180 in the second supporting layer 140 has a fourth critical dimension W4 greater than the second critical dimension W2. The fourth critical dimension W4 may be substantially equal to the first critical dimension W1. In some embodiments, a portion 187 of the lower electrode layer 180 contacting the third supporting layer 160 has a fifth critical dimension W5, wherein the fifth critical dimension W5 is not greater than (e.g., less than or substantially equal to) the second critical dimension W2 and/or the third critical dimension W3. In some embodiments, portion 189 of the lower electrode layer 180 has a minimum critical dimension W6, wherein portion 189 of the lower electrode layer 180 is located between portion 187 contacting the third supporting layer 160 and portion 186 above the second supporting layer 140.

As shown in FIG. 7 , before trimming the lower electrode layer 180, both portion 183 and portion 186 of the lower electrode layer 180 have a first critical size W1. In the step of FIG. 8 (i.e., trimming the lower electrode layer 180), the critical sizes of portion 183 and portion 186 of the lower electrode layer 180 are reduced. That is, portion 183 of the lower electrode layer 180 is reduced to have a second critical size W2 and portion 186 of the lower electrode layer 180 is reduced to have a third critical size W3. In addition, in some embodiments, the critical sizes of portion 187 and portion 189 of the lower electrode layer 180 are reduced. Thus, by trimming the lower electrode layer 180, the critical dimension of the lower electrode layer 180 can be reduced to avoid short circuit of the capacitor formed subsequently (e.g., capacitor Ca in FIG. 10 and FIG. 11). For example, the second critical dimension W2 and/or the third critical dimension W3 of the lower electrode layer 180 is in the range of about 19 nm to about 26 nm, and the first critical dimension of the lower electrode layer 180 is in the range of about 27 nm to about 30 nm.

In some embodiments, the lower electrode layer 180 is trimmed by performing a wet etching process. The wet etching process may use an alkaline etching solution. For example, the alkaline etching solution may include a combination of hydrogen hydroxide, hydrogen peroxide, and water (i.e., NH ₄ OH:H ₂ O ₂ :H 2 O, also known as APM), wherein the ratio of hydrogen hydroxide, hydrogen peroxide, and water may be 1:8:60. In some embodiments, the wet etching process for trimming the lower electrode layer 180 may be performed for a time ranging from about 15 seconds to about 30 seconds. If the wet etching process time is less than 15 seconds, the critical size of the lower electrode layer 180 may be too large, resulting in a short circuit of the capacitor formed subsequently; if the wet etching process time is greater than 30 seconds, the critical size of the lower electrode layer 180 may be too small, resulting in a too low capacitance value of the capacitor.

9 , after trimming the lower electrode layer 180, a high dielectric constant dielectric layer (high-k dielectric layer) 190 is formed. Specifically, the high dielectric constant dielectric layer 190 is formed along the sidewall 180S of the lower electrode layer 180. In addition, the high dielectric constant dielectric layer 190 may be formed along the sidewall, top and bottom surfaces of the second supporting layer 140, the sidewall, top and bottom surfaces of the third supporting layer 160, and the top surface of the first supporting layer 120. In some embodiments, the high-k dielectric layer 190 is conformally deposited along the sidewall 180S of the lower electrode layer 180, such as by atomic layer deposition, chemical vapor deposition, physical vapor deposition, or similar deposition methods. In some embodiments, the lowest surface 191 of the high-k dielectric layer 190 contacts the surface 180T of the lower electrode layer 180 in the first supporting layer 120 and the top surface of the first supporting layer 120. In other words, the lowest surface 191 of the high-k dielectric layer 190 at least partially overlaps with the surface 180T of the lower electrode layer 180 in the first supporting layer 120.

In some implementations, high-k dielectric layer 190 includes ferrite (HfO). In various examples, high-k dielectric layer 190 includes metal oxide (eg, _HfSiO2 , ZnO, _ZrO2 , _Ta2O5 , _Al2O3 , or _{the like} ), metal nitride, or a combination thereof.

Referring to FIG. 10 , after forming the high-k dielectric layer 190, an upper electrode layer 200 is formed along the sidewalls 193 of the high-k dielectric layer 190. The upper electrode layer 200 is located above the horizontal surface of the high-k dielectric layer 190. Thus, a capacitor Ca including the lower electrode layer 180, the high-k dielectric layer 190, and the upper electrode layer 200 is defined in the dielectric stack DS. Since the lower electrode layer 180 is trimmed before forming the high-k dielectric layer 190, the critical size of the lower electrode layer 180 can be reduced, thereby preventing the capacitor Ca from short-circuiting. In some embodiments, the top electrode layer 200 is conformally deposited along the sidewalls 193 of the high-k dielectric layer 190 by, for example, atomic layer deposition, chemical vapor deposition, physical vapor deposition, or the like.

The upper electrode layer 200 may include titanium nitride (TiN) or other suitable conductive materials. In some embodiments, the upper electrode layer 200 and the lower electrode layer 180 include the same material, such as TiN. In some embodiments, the upper electrode layer 200 and the lower electrode layer 180 include different materials, such as the lower electrode layer 180 includes TiSiN, and the upper electrode layer 200 includes TiN.

10 and 11, the semiconductor layer 210 is formed in the space S1 between the first supporting layer 120 and the second supporting layer 140, the space S2 between the second supporting layer 140 and the third supporting layer 160, the first hole H1 in the third supporting layer 160, and the second hole H2 in the second supporting layer 140. The semiconductor layer 210 can completely fill the space S1, the space S2, the first hole H1, and the second hole H2 of the dielectric stack DS. The semiconductor layer 210 can also contact and cover the upper electrode layer 200 above the third supporting layer 160.

In some embodiments, the semiconductor structure includes a plurality of supporting layers (i.e., a first supporting layer 120, a second supporting layer 140, and a third supporting layer 160) and a capacitor Ca. The first supporting layer 120, the second supporting layer 140, and the third supporting layer 160 are arranged from bottom to top, and the first supporting layer 120, the second supporting layer 140, and the third supporting layer 160 are separated from each other. In other words, the third supporting layer 160 is located on the second supporting layer 140, and the second supporting layer 140 is located on the first supporting layer 120. The capacitor Ca contacts the sidewall 123 of the first supporting layer 120 , the sidewall 143 of the second supporting layer 140 , and the sidewall 163 of the third supporting layer 160 . The capacitor Ca includes a lower electrode layer 180 extending from the first supporting layer 120 to the third supporting layer 160, a high dielectric constant dielectric layer 190 along a sidewall 180S of the lower electrode layer 180, and an upper electrode layer 200 along a sidewall 193 of the high dielectric constant dielectric layer 190, wherein the lower electrode layer 180 has a first critical dimension W1 in the first supporting layer 120, and the lower electrode layer 180 has a second critical dimension W2 smaller than the first critical dimension W1 between the first supporting layer 120 and the second supporting layer 140. It should be noted that the capacitor Ca in FIG. 11 is exemplary, and the capacitor Ca is not limited to the structure shown in FIG. For example, the capacitor Ca includes other layers.

In summary, the second critical size W2 of the lower electrode layer 180 of the capacitor Ca of the semiconductor structure disclosed herein between the first supporting layer 120 and the second supporting layer 140 is smaller than the first critical size W1 in the first supporting layer 120, thereby achieving the effect of reducing the critical size of the capacitor Ca, thereby preventing the capacitor Ca from short-circuiting.

Although the present disclosure has disclosed the implementation methods in detail as above, other implementation methods are also possible and are not intended to limit the present disclosure. Therefore, the spirit and scope of the attached patent application scope should not be limited to the description of the implementation methods of the present disclosure.

Anyone skilled in the art may make various changes or substitutions without departing from the spirit and scope of the present disclosure. Therefore, all such changes or substitutions should be included in the protection scope of the patent application attached to the present disclosure.

110: substrate 112: conductive layer 120: first support layer 123,143,163,180S,193,DS1: sidewalls 130: first sacrificial layer 140: second support layer 150: second sacrificial layer 160: third support layer 161,181: top surface 170: opening 180: lower electrode layer 180T: surface 182,183,185,186,187,189: part 190: high dielectric constant dielectric layer 191: lowest surface 200: upper electrode layer 210: semiconductor layer Ca: capacitor DS: Dielectric stack H1: First hole H2: Second hole S1, S2: Space W1: First critical size W2: Second critical size W3: Third critical size W4: Fourth critical size W5: Fifth critical size W6: Minimum critical size

In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more clearly understandable, the attached drawings are described as follows: Figures 1 to 11 show cross-sectional views of various intermediate stages of the method of forming a semiconductor structure according to some embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

110: Substrate

112: Conductive layer

120: The first support layer

123,143,163,180S,193: Side wall

140: Second support layer

160: The third support layer

180: Lower electrode layer

190: High dielectric constant dielectric layer

200: Upper electrode layer

210: Semiconductor layer

Ca:Capacitor

DS: Dielectric Stack

W1: First critical size

W2: Second critical size

Claims (10)

A method for forming a semiconductor structure, comprising: forming a dielectric stack on a conductive layer, wherein the dielectric stack comprises a first supporting layer, a first sacrificial layer, a second supporting layer, a second sacrificial layer and a third supporting layer formed in sequence; forming a lower electrode layer in the dielectric stack, wherein the lower electrode layer has a first critical dimension in the first supporting layer; etching the lower electrode layer and the third supporting layer to form a first hole and expose the second sacrificial layer; removing the second sacrificial layer through the first hole; etching the second supporting layer to form a second hole and expose the first sacrificial layer; Removing the first sacrificial layer through the second hole; and trimming the lower electrode layer so that the lower electrode layer has a second critical dimension between the first supporting layer and the second supporting layer that is smaller than the first critical dimension. The method as described in claim 1, wherein trimming the lower electrode layer is performed by performing a wet etching process. The method of claim 2, wherein the wet etching process is performed using an alkaline etching solution. The method as described in claim 1, wherein trimming the lower electrode layer further enables the lower electrode layer to have a third critical dimension between the second supporting layer and the third supporting layer that is smaller than the first critical dimension. The method as described in claim 1 further comprises: forming a high dielectric constant dielectric layer along a side wall of the lower electrode layer; and forming an upper electrode layer along a side wall of the high dielectric constant dielectric layer. The method of claim 1, wherein forming the first hole further comprises etching the second sacrificial layer. A semiconductor structure comprises: A first supporting layer, a second supporting layer and a third supporting layer, arranged from bottom to top, and the first supporting layer, the second supporting layer and the third supporting layer are separated from each other; and A capacitor contacts a side wall of the first supporting layer, a side wall of the second supporting layer, and a side wall of the third supporting layer, wherein the capacitor comprises a lower electrode layer extending from the first supporting layer to the third supporting layer, a high dielectric constant dielectric layer along a side wall of the lower electrode layer, and an upper electrode layer along a side wall of the high dielectric constant dielectric layer, wherein the lower electrode layer has a first critical dimension in the first supporting layer, and the lower electrode layer has a second critical dimension between the first supporting layer and the second supporting layer that is smaller than the first critical dimension. A semiconductor structure as described in claim 7, wherein the lower electrode layer has a third critical dimension between the second supporting layer and the third supporting layer that is smaller than the first critical dimension. A semiconductor structure as described in claim 7, wherein the lower electrode layer has a fourth critical dimension in the second supporting layer that is larger than the second critical dimension. A semiconductor structure as described in claim 7, wherein a lowest surface of the high-k dielectric layer contacts a surface of the lower electrode layer.