TWI758925B - Amplifying circuit - Google Patents

Abstract

The present disclosure provides an amplifying circuit, including: an input amplifying module having a first output terminal and a second output terminal; an output amplifying module having a first input terminal, a second input terminal and an output terminal; and an overshoot suppressing module electrically connected to the first output terminal and the second output terminal of the input amplifying module, the first input terminal, the second input terminal and the input terminal of the output amplifying module, the overshoot suppressing module is for controlling the voltage of the first output terminal and the second output terminal of the input amplifying module within a preset range according to the voltage of the output terminal of the output amplifying module and a bias voltage of a bias circuit. The overshoot suppressing module includes a bias circuit and a Wide-Swing clamp circuit.

Description

amplifying circuit

The present invention relates to the technical field of integrated circuits, and in particular, to an amplifier circuit.

As a common electronic device, operational amplifiers are widely used in various integrated circuits. Conventional operational amplifiers have outputs for outputting signals. Operational amplifiers can be applied to displays. The display defines a plurality of sub-pixels, and each sub-pixel needs to be applied with a target gray-scale voltage when displaying an image. When the target gray-scale voltage swing is large, an overshoot phenomenon often occurs, resulting in the overshoot of the output end exceeding the target. The gray-scale voltage, and the overshoot of the target gray-scale voltage makes the voltage settling time too long, which will make the display gray-scale error in the display when the operational amplifier is applied to a high-resolution display.

The clamp diode can be applied to solve the overshoot problem, but the leakage current in the steady state period after the clamp diode is turned on still needs to solve the large variation of the target voltage of the operational amplifier. Therefore, taking into account the overshoot problem in the transient period and the leakage problem in the steady state period become Technical problems to be solved urgently.

One aspect of the present invention provides an amplifying circuit, including: an input amplifying module having a first output end and a second output end; an output amplifying module having a first input end, a second input end and an output end; and an overshoot suppression module , the overshoot suppression module is electrically connected to the first output end and the second output end of the input amplifying module, the first input end, the second input end and the second output end of the output amplifying module the input terminal is used to control the transient voltage of the first output terminal and the second output terminal of the input amplifying module to be within a preset range according to the voltage of the output terminal of the output amplifying module; the overshoot suppression The module includes a stacked bias circuit and a Wide-Swing clamp circuit, the Wide-Swing clamp circuit is electrically connected to two ends of the bias circuit respectively, and the stacked bias circuit is used for receiving the bias voltage. voltage signal, and the Wide-Swing clamping circuit is used for controlling the overshoot suppression module to be in an on or open state according to the bias signal and the signal at the output end of the output amplifying module.

The above amplifying circuit is beneficial to suppress the voltage output by the first output terminal and the second output terminal of the input amplifying module within the preset range by the overshoot suppression module, and is beneficial to reduce the leakage current.

10: Amplifier circuit

20: Input amplifier module

SP: first output terminal

SN: The second output terminal

21: Non-inverting input terminal

22: Inverting input terminal

PD2: Node

30: Output amplifier module

31: The first input terminal

32: The second input terminal

AVO, AVOI: output terminal

M1: first transistor

M2: second transistor

40: Overshoot suppression module

41: The first suppression unit

42: Second Suppression Unit

N1: the first end

N2: second end

411: Stacked bias circuit

412: Wide-Swing Clamp Circuit

M3: The third transistor

M4: Fourth transistor

M5: Fifth transistor

M6: sixth transistor

BIAS: Bias signal

FIG. 1 is a schematic diagram of the circuit structure of the amplifier circuit.

FIG. 2 is a schematic diagram of a circuit structure of the first suppression unit and the second suppression unit.

FIG. 3 is a schematic diagram of another circuit structure of the first suppression unit and the second suppression unit.

FIG. 4 is a schematic diagram of a circuit structure of a first suppression unit in a plurality of embodiments.

FIG. 5 is a schematic diagram of the circuit structure of the input amplifying module.

FIG. 6 is a schematic diagram of a circuit structure of a second suppression unit in a plurality of embodiments.

Example 1

The amplifying circuit provided in this embodiment can be applied to various integrated circuits, for example, a driver of a display device.

Referring to FIG. 1 , the amplifier circuit 10 includes an input amplifier module 20 , an output amplifier module 30 , and an overshoot suppression module 40 electrically connected between the input amplifier module 20 and the output amplifier module 30 .

The input amplifying module 20 has a first output terminal SP and a second output terminal SN. The output amplifying module 30 has a first input terminal 31 , a second input terminal 32 and an output terminal AVO. The first output terminal SP of the input amplifying module 20 is electrically connected to the first input terminal 31 of the output amplifying module 30 ; the second output terminal SN of the input amplifying module 20 is electrically connected to the second input terminal 32 of the output amplifying module 30 . The overshoot suppression module 40 is electrically connected to the first output terminal SP, the second output terminal SN of the input amplifying module 20 and the output terminal AVO of the output amplifying module 30 respectively. The overshoot suppression module 40 is used for suppressing the signal values of the first output terminal SP and the second output terminal SN of the input amplifying module 20 . In this embodiment, the overshoot suppression module 40 is used to suppress the voltage values of the first output terminal SP and the second output terminal SN of the input amplifying module 20 .

The output amplifying module 30 includes a first transistor M1 and a second transistor M2. Both the first transistor M1 and the second transistor M2 are metal oxide semiconductor (MOS) field effect transistors. The first transistor M1 is a P-type MOS transistor, and the second transistor M2 is an N-type MOS transistor.

The gate of the first transistor M1 is used as the first input terminal 31 of the output amplifying module 30 for receiving the signal output by the first output terminal SP of the input amplifying module 20; the source of the first transistor M1 is used for receiving the system voltage Vdd. The gate of the second transistor M2 serves as the second input terminal 32 of the output amplifying module 30 for receiving the signal output by the second output terminal SN of the input amplifying module 20 ; the source of the second transistor M2 is grounded. The drain of the first transistor M1 is electrically connected to the drain of the second transistor M2 and serves as the output terminal AVO of the output amplifying module 30 .

In this embodiment, the input amplifying module 20 is an input amplifier, which further includes a non-inverting input terminal 21 and an inverting input terminal 22, and the inverting input terminal 22 is connected to the output terminal AVO in a negative feedback form. The signals output by the first output terminal SP and the second output terminal SN are controlled by the signal of the non-inverting input terminal 21 .

The input amplifying module 20 has a transient period and a steady period. During the transient period of the input amplifying module 20, the phenomenon that the voltage of the first output terminal SP is too low or the voltage of the second output terminal SN is too high may occur. Settling time of the voltage at terminal AVO. The amplifying circuit 10 in this embodiment is applied to a display. The longer the settling time is, the more likely the display grayscale is wrong in a high-resolution display, so the settling of the voltage at the output terminal AVO is shortened. Time is beneficial to improve the accuracy of displaying grayscale.

Define the period when the voltages of the first output terminal SP and the second output terminal SN are at the preset value as the steady-state period of the input amplifier module 20, and define the period when the voltages of the first output terminal SP and the second output terminal SN exceed the preset value. The period is the transient period of the input amplification module 20 . During the steady state period, the overshoot suppression module 40 is not turned on, and the signals output by the first output terminal SP and the second output terminal SN are respectively output to the first input terminal 31 and the second input terminal 32 of the output amplification module 30 , thereby Control the signal of the output terminal AVO of the output amplifying module 30 . In the transient period, if the overshoot exceeds the settling time of the target gray scale for a long time, the overshoot suppression module 40 is turned on, thereby suppressing the voltage output from the first output terminal SP and the second output terminal SN from being let down. The output terminal AVO voltage settling time becomes shorter.

In this embodiment, the overshoot suppression module 40 includes a first suppression unit 41 and a second suppression unit 42 that are electrically connected to each other. The first suppressing unit 41 is electrically connected to the first output terminal SP of the input amplifying module 20 , the second suppressing unit 42 is electrically connected to the second output terminal SN of the input amplifying module 20 , and the connection between the first suppressing unit 41 and the second suppressing unit 42 is The node is electrically connected to the output terminal AVO of the output amplifying module 30 . The first suppression unit 41 is used to suppress the voltage value of the first output terminal SP of the input amplifying module 20 , and the second suppression unit 42 is used to suppress the voltage value of the second output terminal SN of the input amplifying module 20 .

The circuit structures of the first suppression unit 41 and the second suppression unit 42 can both be as shown in FIG. 2 or FIG. 3 .

Please refer to FIG. 2 , the first suppression unit 41 has a first terminal N1 and a second terminal N2 . The first suppression unit 41 includes a wide-swing clamp circuit 412 that is electrically connected between the first end N1 and the second end N2, and also includes a stacked bias circuit 411 for controlling the first end N1 and the second end N2. A cut-in voltage of the suppression unit 41 . The stacked bias circuit 411 receives the bias signal BIAS. By adjusting the bias signal BIAS, the cut-in voltage of the first suppression unit 41 can be controlled, thereby controlling the clamping range of the entire first suppression unit 41 .

The clamping circuit 412 includes at least one Wide-Swing configuration transistor.

Please continue to refer to FIG. 2 , in this embodiment, the Wide-Swing clamping circuit 412 includes a Wide-Swing third transistor M3 which is an N-type transistor. One end of the stacked bias circuit 411 is connected close to the first end N1, and the other end is connected close to the drain of the third transistor M3. The source connection of the third transistor M3 is close to the second terminal N2 , and the gate connection is close to the first terminal N1 and the stacked bias circuit 411 .

Referring to FIG. 3 , in another embodiment, the connection mode of the Wide-Swing third transistor M3 and the stacked bias circuit 411 is different from the connection mode of the first suppression unit 41 in FIG. 2 . In the first suppression unit 41 shown in FIG. 3 , the source of the third transistor M3 is connected close to the first terminal N1 , and the stacked bias circuit 411 is connected between the drain of the third transistor M3 and the second terminal N2 During this time, the gate of the third transistor M3 is connected between the stacked bias circuit 411 and the second terminal N2.

The stacked bias circuit 411 includes at least one transistor. In the first suppression unit 41, the first terminal N1 is connected to the output terminal AVO of the output amplifying module 30 or to a circuit node inside the input amplifying module 20, and the second terminal N2 is connected to the first output terminal SP of the input amplifying module 20; In the second suppression unit 42 , the second terminal N2 is connected to the output terminal AVO of the output amplifier module 30 or to a circuit node inside the input amplifier module 20 , and the first terminal N1 is connected to the second output terminal SN of the input amplifier module 20 .

FIG. 4 shows different embodiments of the specific circuit structure of the first suppression unit 41 as shown in FIG. 2 and FIG. 3 in the form of a block diagram, but it is not limited thereto. The circuit structures and working principles of several of the embodiments are described below.

Please refer to (a) of FIG. 4 , the stacked bias circuit 411 includes a fourth transistor M4 . The source of the fourth transistor M4 is connected to the first terminal N1, the drain is connected to the drain of the third transistor M3 in the Wide-Swing configuration, and the gate is connected to an external node for receiving the bias signal BIAS. Wide-Swing configuration The source of the three transistor M3 is connected to the second terminal N2, and the gate is connected between the first terminal N1 and the source of the fourth transistor M4.

The fourth transistor M4 in the stacked configuration can adjust the cut-in voltage of the first suppression unit 41 by changing the magnitude of the bias signal BIAS. The first terminal N1 is connected to the output terminal AVO of the output amplifying module 30 , and the second terminal N2 is connected to the first output terminal SP of the input amplifying module 20 .

During the transient period of the input amplifying module 20, the point SP of the first output terminal is gradually drawn deep so that the driving current of the first transistor M1 of the output amplifying module 30 can charge the output terminal AVO. If the output terminal SP is too deep, the actual charging voltage of the output terminal AVO will overshoot and exceed the target gray-scale voltage, resulting in a longer settling time of the output terminal AVO voltage. When the overshoot voltage of the output terminal AVO is greater than the bias signal BIAS and exceeds the sum of a threshold voltage VTH of the fourth transistor M4 and the driving voltage VOV, the first suppression unit 41 starts to be turned on to allow the output terminal AVO to clamp the first output terminal SP The sum of one of the threshold voltage VTH and the driving voltage VOV of the third transistor M3 solves the problem that the first output terminal SP is prone to excessively deep swing when the output is large.

In this embodiment, the N-type third transistor M3 is used in the first suppression unit 41, because the substrate effect (Body Effect) of the display causes the threshold voltage VTH of the third transistor M3 to be relatively large, and it is not easy to be turned on in a steady state , which is beneficial to suppress leakage current.

Please refer to (c) of FIG. 4 , the stacked bias circuit 411 includes a fourth transistor M4 . In the Wide-Swing configuration, the source of the third transistor M3 is connected to the first terminal N1, the drain is connected to the source of the fourth transistor M4, the drain of the fourth transistor M4 is connected to the second terminal N2, and the gate is connected to an external node For receiving the bias signal BIAS, the gate of the third transistor M3 in the Wide-Swing configuration is connected between the second terminal N2 and the drain of the fourth transistor M4.

In the application of this embodiment, the fourth transistor M4 in the stacked configuration can adjust the cut-in voltage of the first suppression unit 41 by changing the magnitude of the bias signal BIAS. The first terminal N1 is connected to the output terminal AVO of the output amplifying module 30 , and the second terminal N2 is connected to the first output terminal SP of the input amplifying module 20 .

During the transient period of the input amplifier module 20, the overshoot voltage of the output terminal AVOI is greater than the bias signal BIAS and exceeds the sum of a threshold voltage VTH of the fourth transistor M4 and the driving voltage VOV, then the first suppression unit 41 starts to turn on to allow the output terminal AVO The first output terminal SP is clamped at the sum of a threshold voltage VTH of the third transistor M3 and the driving voltage VOV, so that the original problem that the output swing of the first output terminal SP is easy to be too deep can be solved.

In this embodiment, in order to solve the problem of AVO overshoot at the output end, the bias signal BIAS may be designed too deep, which may lead to the leakage of the clamp circuit during the steady state period, resulting in an increase in the variation of the OP output voltage. Therefore, in this embodiment, the magnitude of the leakage current and the output end The AVO overshoot problem requires a trade-off.

Please refer to (e) of FIG. 4 , the stacked bias circuit 411 includes a fourth transistor M4 and a fifth transistor M5. The source of the fifth transistor M5 is connected to the source of the fourth transistor M4, the drain is connected to the drain of the third transistor M3, and the gate is connected to the output terminal AVO.

The fourth transistor M4 and the fifth transistor M5 in the stacked configuration can adjust the cut-in voltage of the first suppression unit 41 by changing the magnitude of the bias signal BIAS. The first terminal N1 is connected to an internal circuit node PD2 of the input amplifying module 20 (see FIG. 5 ), and the second terminal N2 is connected to the first output terminal SP of the input amplifying module 20 .

During the transient period of the input amplifying module 20, the voltage of the output terminal AVO is higher than the sum of the threshold voltage VTH and the driving voltage VOV of the fourth transistor M4 and the fifth transistor M5 in the designed bias signal BIAS stacking configuration, then the first The suppression unit 41 starts to be turned on so that the node PD2 clamps the first output terminal SP at the sum of a threshold voltage VTH of the third transistor M3 and the driving voltage VOV, thus solving the original problem that SP is prone to excessively deep output swing.

Referring to FIG. 5, the first transistor M1 (the second transistor M2) is usually designed to have a higher aspect ratio than the sixth transistor M6, so the first output of the circuit node in the steady state period is The terminal SP (second output terminal SN) point is closer to the voltage source terminal than the node PD2 ( ND2 ), so the third transistor M3 turns off the Wide-Swing clamping circuit 412 during the steady state period, thereby effectively reducing the leakage current. In other embodiments of the present invention, the first terminal N1 may be connected to other nodes whose voltage is lower than the voltage of the first output terminal SP during the steady state period, and is not limited to the node PD2.

It should be understood that the first suppression unit 41 is not limited to include the stacked bias circuit 411 and the Wide-Swing clamp circuit 412 . In other embodiments, the first suppression unit 41 may further include other electronic components, and the working process of the stacking bias circuit 411 and the Wide-Swing clamping circuit 412 may not be affected. The other electronic components can be, for example, resistors, MOS transistors, and the like. Moreover, the other electronic components are represented by Block, and the Block can be electrically connected to any position as shown in FIGS. 2 and 3 . Alternatively, in another embodiment, the other electronic components can be directly integrated into the stacking bias circuit 411 .

The circuit structures of the first suppression unit 41 and the second suppression unit 42 are basically similar, and the main difference is that the types of transistors (P-type or N-type) are different. FIG. 6 shows several second suppression units 42 The specific implementation of the circuit structure. The circuit structure and working principle of the second suppression unit 42 will not be repeated here, and reference may be made to the above description of the first suppression unit 41 .

In the amplifying circuit 10 provided in this embodiment, the first suppression unit 41 and the second suppression unit 42 are provided to suppress the transient voltage values of the first output terminal SP and the second output terminal SN of the input amplifying module 20 respectively, which is beneficial to Controlling the first output terminal SP and the second output terminal SN within a preset range is beneficial to prevent the voltage of the first output terminal SP and the second output terminal SN from exceeding the preset range and allowing the output terminal AVO voltage to settle for a settling time It becomes shorter, which leads to display grayscale errors in high-resolution applications. In addition, proper selection of the embodiment can also reduce the amount of output voltage variation caused by leakage current.

Measure the leakage current of the amplifying circuit in a pair of ratios and the amplifying circuit 10 provided in the first and second embodiments respectively in the steady state period, see Table 1:

It can be seen from Table 1 that the amplifier circuits provided in the first and second embodiments can effectively reduce the leakage current of the amplifier circuit in the steady state period. Further, circuits (e) and (e) in FIG. 4 even reduce the leakage current to an infinite approach to zero.

In this embodiment, by setting the first terminal N1 and the second terminal N2 to be connected to different nodes of the circuit to control the voltages of the first terminal N1 and the second terminal N2, it is beneficial to control the first suppression unit 41 and the second suppression unit in the stable state. The open-circuit state is maintained during the state period, thereby effectively reducing the generation of leakage current, which is beneficial to improve the performance of the amplifier circuit 10 .

Those skilled in the art should realize that the above embodiments are only used to illustrate the present invention, but not to limit the present invention, as long as the above embodiments are appropriately made within the spirit and scope of the present invention Changes and changes all fall within the scope of the claimed invention.

41: The first suppression unit

N1: the first end

N2: second end

411: Stacked bias circuit

412: Wide-Swing Clamp Circuit

M3: The third transistor

Claims (10)

An amplifying circuit, which is improved by comprising: an input amplifying module having a first output end and a second output end; an output amplifying module having a first input end, a second input end and an output end; and an overshoot suppression module, The overshoot suppression module is electrically connected to the first output end and the second output end of the input amplifying module, the first input end, the second input end and the an output end, used for controlling the voltage of the first output end and the second output end of the input amplifying module to be within a preset range according to the voltage of the output end of the output amplifying module; the overshoot suppression module includes a stack A bias circuit and a Wide-Swing clamp circuit are connected, the Wide-Swing clamp circuit is electrically connected to two ends of the stacked bias circuit respectively, and the stacked bias circuit is used for receiving bias voltage signal, the Wide-Swing clamping circuit is used for controlling the overshoot suppression module to be in an on or open state according to the bias signal and the signal at the output end of the output amplifying module. The amplifier circuit according to claim 1, wherein the overshoot suppression module includes a first suppression unit and a second suppression unit that are electrically connected to each other, and the first suppression unit is connected to the first output end of the input amplifying module , the second suppression unit is connected to the second output end of the input amplifying module, and the node between the first suppression unit and the second suppression unit is connected to the output end of the output amplifying module; the first suppression unit The suppression unit includes the stacked bias circuit and the Wide-Swing clamp circuit, and the second suppression unit also includes the stacked bias circuit and the Wide-Swing clamp a bit circuit, the first suppression unit is configured to control the voltage of the first output end of the input amplifying module to be within the preset range according to the output end of the output amplifying module and the voltage of the stacked bias circuit and the second suppression unit is configured to control the voltage of the second output end of the input amplifying module to be within the preset range according to the output end of the output amplifying module and the voltage of the stacked bias circuit. The amplifying circuit according to claim 1, wherein the output amplifying module includes a first transistor and a second transistor; the drain of the first transistor is connected to the drain of the second transistor and is connected to The output terminal of the output amplifier module, the gate of the first transistor is connected to the first output terminal of the input amplifier module, and the gate of the second transistor is connected to the second output terminal of the input amplifier module. output. The amplifying circuit of claim 1, wherein the first suppression unit includes a first end and a second end, and the stacked bias circuit is connected between the first end and the second end ; The Wide-Swing clamping circuit includes at least a third transistor, and the source and drain of the third transistor are connected between the stacked bias circuit and the second end, and the first The gate of the three-transistor is connected between the stacked bias circuit and the first terminal. The amplifying circuit of claim 1, wherein the first suppression unit includes a first end and a second end, and the stacked bias circuit is connected between the first end and the second end ; The Wide-Swing clamping circuit includes at least a third transistor, the source and drain of the third transistor are connected between the stacked bias circuit and the first end, the The gate of the third transistor is connected between the bias circuit and the second terminal. The amplifier circuit according to claim 4 or 5, wherein the stacked bias circuit comprises at least a fourth transistor, and the source and drain of the fourth transistor are connected to the first terminal and the Between the second ends, the gate of the fourth transistor is used for receiving a bias signal. The amplifying circuit of claim 6, wherein the bias circuit further comprises a fifth transistor, and the source and drain of the fifth transistor are connected to the first terminal and the second terminal between the terminals, the gate of the fifth transistor is connected to the output terminal of the output amplifying circuit. The amplifying circuit according to claim 4 or 5, wherein the second end is a first output end of the input amplifying module, and the first end is an output end of the output amplifying module. The amplifying circuit according to claim 4 or 5, wherein the input amplifying module operates in a steady state period and a transient period; the second terminal is the first output terminal of the input amplifying module, and the first The terminal is a node in the input amplifying module. When the input amplifying module operates in the steady state, the voltage of the node is higher than the voltage of the second terminal. The amplifying circuit according to claim 1, wherein the input amplifying module is an input amplifier.

Images