TWI508049B - Source driver - Google Patents

Description

Source driver

This invention relates to a driver, and more particularly to a source driver.

With the advancement of optoelectronic and semiconductor components, flat panel displays such as liquid crystal displays (LCDs) have flourished in recent years. Liquid crystal displays have gradually become the mainstream of the market due to their many advantages, such as low power consumption, no radiation, and high space utilization. The source driver is a relatively important component in the liquid crystal display, which converts the display data for displaying the digits of the image to an analog driving voltage, and outputs the driving voltage to each pixel of the display panel.

Generally, the source driver includes a driving channel for converting display data into a driving voltage, and an output buffer for buffering the driving voltage and driving the driving voltage to drive the display panel through the driving voltage. Charge and discharge action. Among them, when the voltage level of the driving voltage is changed, the output buffer needs a reaction time to reflect the change of the voltage level. Therefore, the reaction time of the output buffer affects the reaction speed of the entire source driver, and as the display panel is oriented toward a large size, the response speed of the output buffer is improved. A focus of the source driver.

The present invention provides a source driver that can reduce the transient time required for the output buffer to buffer the driving voltage to increase the response speed of the output buffer.

The source driver of the present invention comprises a data channel, a first output buffer, a switching unit, a first clamping circuit and a second clamping circuit. The data channel receives a display material and provides a first driving voltage. The first output buffer is coupled to the data channel to buffer the first driving voltage. The switch unit is coupled to the first output buffer and the first data line, and receives a switch signal to provide the first driving voltage to the first data line according to the switch signal. The first clamping circuit is coupled to the first output buffer and receives the first driving voltage to provide a first clamping voltage to the first output buffer. The second clamping circuit is coupled to the first output buffer and receives the first driving voltage to provide a second clamping voltage to the first output buffer. The first output buffer clamps a control voltage of an output stage of the first output buffer according to the first clamping voltage and the second clamping voltage.

In an embodiment of the invention, the first clamping circuit and the second clamping circuit are coupled to the first data line to receive the first driving voltage.

In an embodiment of the invention, the first clamping circuit and the second clamping circuit are coupled to the data channel to receive the first driving voltage.

In an embodiment of the invention, the source driver further includes a second output buffer, a third clamping circuit, and a fourth clamping circuit. Second output buffer coupling The data channel is connected to buffer a second driving voltage provided by the data channel. The third clamping circuit is coupled to the second output buffer and receives the second driving voltage to provide a third clamping voltage to the second output buffer. The fourth clamping circuit is coupled to the second output buffer and receives the second driving voltage to provide a fourth clamping voltage to the second output buffer. The switch unit is further coupled to the second output buffer and the second data line, and the switch unit provides one of the first driving voltage and the first driving voltage to the first data line according to the switching signal and provides the first driving voltage and the first driving One of the voltages to the second data line. The second output buffer clamps a control voltage of an output stage of the second output buffer according to the third clamping voltage and the fourth clamping voltage.

In an embodiment of the invention, the first clamping circuit and the second clamping circuit are coupled to the data channel to receive the first driving voltage, and the third clamping circuit and the fourth clamping circuit are coupled to the data channel to receive the second driving voltage.

In an embodiment of the invention, the first clamping circuit and the third clamping circuit respectively comprise a first diode. The anode of the first diode receives the first driving voltage or the second driving voltage, and the cathode of the first diode provides a first clamping voltage or a third clamping voltage.

In an embodiment of the invention, the first clamping circuit and the third clamping circuit further comprise a first switch. The first switch receives the switch signal and is coupled between the anode of the first diode and the first driving voltage or the second driving voltage.

In an embodiment of the invention, the second clamping circuit and the fourth clamping circuit respectively comprise a second diode. The cathode of the second diode receives the first driving voltage or the second driving voltage, and the anode of the second diode provides the second clamping voltage or the fourth clamping voltage Voltage.

In an embodiment of the invention, the second clamping circuit and the fourth clamping circuit further comprise a second switch. The second switch receives the switch signal and is coupled between the anode of the second diode and the first driving voltage or the second driving voltage.

In an embodiment of the invention, the first clamping circuit and the second clamping circuit are coupled to the first data line and the second data line to receive the first driving voltage, and the third clamping circuit and the fourth clamping circuit are coupled to the first data. The line and the second data line receive the second driving voltage.

In an embodiment of the invention, the first clamping circuit and the third clamping circuit respectively comprise a first multiplexer and a third diode. The plurality of input ends of the first multiplexer are respectively coupled to the first data line and the second data line, and receive the switch signal. The anode of the third diode is coupled to the output of the first multiplexer to receive the first driving voltage or the second driving voltage, and the cathode of the third diode provides the first clamping voltage or the third clamping voltage.

In an embodiment of the invention, the second clamping circuit and the fourth clamping circuit respectively comprise a second multiplexer and a fourth diode. The plurality of input ends of the second multiplexer are respectively coupled to the first data line and the second data line, and receive the switch signal. The cathode of the fourth diode is coupled to the output of the second multiplexer to receive the first driving voltage or the second driving voltage, and the anode of the fourth diode provides the second clamping voltage or the fourth clamping voltage.

In an embodiment of the invention, the first output buffer and the second output buffer respectively comprise an operational amplifier, a first transistor and a second transistor. The operational amplifier has a first input terminal, a second input terminal, a first output terminal and a second output terminal, wherein the first input terminal receives the first driving voltage or the second driving power The second output end is coupled to the switch unit, and the first output end and the second output end respectively provide a control voltage. The first end of the first transistor receives a system voltage, the control end of the first transistor is coupled to the first output end, and the second end of the first transistor outputs the buffered first driving voltage or the second driving voltage. The first end of the first transistor is coupled to the second end of the first transistor, the control end of the second transistor is coupled to the second output, and the second end of the second transistor receives a ground voltage. The first transistor and the second transistor are output stages of the first output buffer or the second output buffer.

Based on the above, in the source driver of the embodiment of the present invention, the first clamping circuit and the second clamping circuit provide a first clamping voltage and a second clamping voltage according to the first driving voltage to clamp the output stage of the first output buffer. Control voltage. Thereby, the transient time required for the first output buffer to buffer the first driving voltage can be shortened to increase the reaction speed of the first output buffer.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧ display panel

100, 200, 300, 400, 500, 600, 700‧‧‧ source drivers

11, 13‧‧‧ data line

110, 510‧‧‧ data channel

120, 120a, 520‧‧‧ first output buffer

130, 130a, 130b, 430, 530, 630, 630a ‧ ‧ first clamp circuit

140, 140a, 140b, 440, 540, 640, 640a‧‧‧ second clamp circuit

150, 550‧‧‧ switch unit

560‧‧‧Second output buffer

570, 670, 670a‧‧‧ third clamp circuit

580, 680, 680a‧‧‧ fourth clamp circuit

D1, D2, D11~D14‧‧‧ diode

E1, E2‧‧‧ input

M1‧‧‧first transistor

M2‧‧‧second transistor

MX1~MX4‧‧‧Multiplexer

O1, O2‧‧‧ output

OP1‧‧‧Operational Amplifier

PD1, PD2‧‧‧ Display data

SW1‧‧‧ switch

SW2‧‧‧ first switch

SW3‧‧‧Second switch

SWa, SWb‧‧‧ switch signal

VCP1, VCP11‧‧‧ first clamping voltage

VCP2, VCP12‧‧‧ second clamping voltage

VCP13‧‧‧ first clamping voltage

VCP14‧‧‧Second clamp voltage

VCT1, VCT2‧‧‧ control voltage

VD1, VD11‧‧‧ first drive voltage

VD12‧‧‧second drive voltage

VDD‧‧‧ system voltage

1 is a circuit diagram of a source driver in accordance with a first embodiment of the present invention.

2 is a circuit diagram of a source driver in accordance with a second embodiment of the present invention.

3 is a circuit diagram of a source driver in accordance with a third embodiment of the present invention.

4 is a circuit diagram of a source driver in accordance with a fourth embodiment of the present invention.

Figure 5 is a circuit diagram of a source driver in accordance with a fifth embodiment of the present invention.

Figure 6 is a circuit diagram of a source driver in accordance with a sixth embodiment of the present invention.

Figure 7 is a circuit diagram of a source driver in accordance with a seventh embodiment of the present invention.

1 is a circuit diagram of a source driver in accordance with a first embodiment of the present invention. Referring to FIG. 1 , in the embodiment, the source driver 100 is coupled to the display panel 10 to provide a driving voltage (eg, VD1 ) to the data lines (eg, 11, 13 ) of the display panel 10 . The source driver 100 includes a data channel 110, a first output buffer 120, a first clamping circuit 130, a second clamping circuit 140, and a switching unit 150.

The data channel 110 receives the display material PD1 and correspondingly supplies the first driving voltage VD1. The first output buffer 120 is coupled to the data channel 110 to buffer the first driving voltage VD1. The switch unit 150 includes, for example, a switch SW1, wherein one end of the switch SW1 of the switch unit 150 is coupled to the output end of the first output buffer 120 to receive the first driving voltage VD1, and the other end of the switch SW1 of the switch unit 150 is coupled to the display. A data line of the panel 10 (such as 11 or 13, corresponding to the first data line). The switch SW1 of the switching unit 150 receives the switching signal SWa to provide the first driving voltage VD1 to the data line (such as 11 or 13) according to the switching signal SWa.

The first clamping circuit 130 is coupled to the first output buffer 120 and coupled to the other end of the data line (equivalent to being coupled to the first data line) to receive the first driving voltage VD1. After receiving the first driving voltage VD1, the first clamping circuit 130 provides the first clamping voltage VCP1 to the first output buffer 120 according to the first driving voltage VD1. The second clamping circuit 140 is coupled to the first output buffer 120, and The other end of the data line is coupled to the switch SW1 (equivalent to being coupled to the first data line) to receive the first driving voltage VD1. The second clamping circuit 140 receives the first driving voltage VD1 and provides a second clamping voltage VCP2 to the first output buffer 120.

After receiving the first clamping voltage VCP1 and the second clamping voltage VCP2, the first output buffer 120 clamps the control voltage of the output stage of the first output buffer 120 according to the first clamping voltage VCP1 and the second clamping voltage VCP2 (the As will be described later, the voltage of the output terminal of the first output buffer 120 is prevented from oscillating when approaching the first driving voltage VD1, so that the first output buffer 120 is required to buffer the first driving voltage VD1. The time will be shorter, and the reaction speed of the first output buffer 120 can be increased.

2 is a circuit diagram of a source driver in accordance with a second embodiment of the present invention. Referring to FIGS. 1 and 2, the source driver 200 is substantially the same as the source driver 100, and is different in the first output buffer 120a, the first clamp circuit 130a, and the second clamp circuit 140a. The first output buffer 120a includes an operational amplifier OP1, a first transistor M1, and a second transistor M2, wherein the same or similar elements use the same or similar reference numerals. Moreover, the first transistor M1 is exemplified by a P-type transistor, the second transistor M2 is exemplified by an N-type transistor, and the first transistor M1 and the second transistor M2 are the first output buffer 120a. The output stage.

The operational amplifier OP1 has a positive input terminal (corresponding to the first input terminal), a negative input terminal (corresponding to the second input terminal), a first output terminal and a second output terminal. The positive input terminal of the operational amplifier OP1 is coupled to the data channel 110 to receive the first driving voltage VD1, and the switch SW1 coupled to the negative output terminal of the switching unit 150 is coupled to the first output buffer 120a. One end is used to feedback the voltage of the output end of the first output buffer 120a, and the first output end and the second output end respectively provide the control voltages VCT1 and VCT2.

The source (corresponding to the first end) of the first transistor M1 receives the system voltage VDD, and the gate (corresponding control end) of the first transistor M1 is coupled to the first output end of the operational amplifier OP1 to receive the control voltage VCT1, first The drain of the transistor M1 (corresponding to the second end) is equivalent to the output of the first output buffer 120a for outputting the corresponding first driving voltage VD1 to change its output voltage, that is, outputting the buffered first driving voltage VD1. The drain of the second transistor M2 (corresponding to the first end) is coupled to the drain of the first transistor M1, and the gate of the second transistor M2 (corresponding to the control terminal) is coupled to the second output of the operational amplifier OP1 for receiving The control voltage VCT2, the source of the second transistor M2 (corresponding to the second end) receives the ground voltage.

The first clamping circuit 130a includes a diode D1 (corresponding to the first diode). The anode of the diode D1 is coupled to the other end of the switch SW1 to receive the first driving voltage VD1, and the cathode of the diode D1 is coupled to the gate of the first transistor M1 to provide the first clamping voltage VCP1 to the first transistor. M1. The second clamping circuit 140a includes a diode D2 (corresponding to the second diode). The cathode of the diode D2 is coupled to the other end of the switch SW1 to receive the first driving voltage VD1, and the anode of the diode D2 is coupled to the gate of the second transistor M2 to provide the second clamping voltage VCP2.

According to the above, when the voltage level of the first driving voltage VD1 changes from low to high, the operational amplifier OP1 provides a low voltage level control voltage VCT1 to turn on the first transistor M1, but the second transistor M2 will remain substantially unchanged. Turn on. Then, when the voltage of the drain of the first transistor M1 approaches the first driving voltage VD1, the low battery It takes a period of recovery time for the control voltage VCT1 of the voltage level to return to the original voltage level (such as the high voltage level), so the voltage of the drain of the first transistor M1 may overshoot the voltage, but via The first clamping circuit 130a provides a first clamping voltage VCP1 whose voltage level is close to the first driving voltage VD1, and can accelerate the recovery speed of the control voltage VCT1 to suppress the phenomenon of voltage overshoot.

On the other hand, when the voltage level of the first driving voltage VD1 changes from high to low, the operational amplifier OP1 provides a high voltage level control voltage VCT2 to turn on the second transistor M2, but the first transistor M1 will roughly Keep not conducting. Then, when the voltage of the drain of the second transistor M2 approaches the first driving voltage VD1, the return of the high voltage level control voltage VCT2 to the original voltage level (such as the low voltage level) also requires a recovery time, so The voltage of the drain of the second transistor M2 may be undershooted, but the second clamp voltage VCP2 whose voltage level is close to the first driving voltage VD1 is supplied via the second clamp circuit 140a, and the control voltage VCT2 can be accelerated. The speed of recovery to suppress the phenomenon of voltage undershoot.

3 is a circuit diagram of a source driver in accordance with a third embodiment of the present invention. Referring to FIGS. 2 and 3, the source driver 300 is substantially the same as the source driver 200, except for the first clamp circuit 130b and the second clamp circuit 140b. The first clamping circuit 130b further includes a first switch SW2, and the second clamping circuit 140b further includes a second switch SW3. The first switch SW2 receives the switch signal SWa and is coupled between the anode of the diode D1 and the other end of the switch SW1 (equivalent to the first driving voltage VD1). The second switch SW3 receives the switch signal SWa and is coupled between the cathode of the diode D2 and the other end of the switch SW1 (equivalent to the first driving voltage VD1).

In general, the first drive voltage VD1 that is steady state is supplied to the data line (eg, 11, 13) of the display panel 10 via the switch SW1, that is, the first output buffer 120a is provided when the switch SW1 is turned on. The voltage level of the driving voltage VD1 does not change. On the other hand, the first clamping circuit 130b and the second clamping circuit 140b are mainly operated when the first driving voltage VD1 is in a transient state, that is, the first switch SW2 and the second switch SW3 are turned on the voltage level of the first driving voltage VD1. When changing. Therefore, when the switch SW1 is turned on, the first switch SW2 and the second switch SW3 can be made non-conductive; when the switch SW1 is not turned on, the first switch SW2 and the second switch SW3 can be turned on. In other words, although the switch SW1, the first switch SW2, and the second switch SW3 are also controlled by the switch signal SWa, the on state of the switch SW1 is opposite to the on state of the first switch SW2 and the second switch SW3.

4 is a circuit diagram of a source driver in accordance with a fourth embodiment of the present invention. Referring to FIGS. 1 and 4, the source driver 400 is substantially identical to the source driver 100, except for the first clamp circuit 430 and the second clamp circuit 440, wherein the same or similar elements are given the same or similar reference numerals. The first clamping circuit 430 and the second clamping circuit 440 are both coupled to the data channel 110 to receive the first driving voltage VD1, and the first clamping voltage VCP1 and the second clamping voltage VCP2 are respectively provided according to the first driving voltage VD1. The first clamping circuit 430 and the second clamping circuit 440 can refer to the first clamping circuit 130a and the second clamping circuit 140a shown in FIG. 2, respectively, or can refer to the first clamping circuit 130b and the second clamping circuit shown in FIG. 3, respectively. 140b, but the embodiment of the present invention is not limited thereto.

FIG. 5 is a circuit diagram of a source driver according to a fifth embodiment of the present invention. Figure. Referring to FIG. 5 , in the embodiment, the source driver 500 is coupled to the display panel 10 to provide driving voltages (eg, VD11, VD12) to the data lines (eg, 11, 13) of the display panel 10. The source driver 500 includes a data channel 510, a first output buffer 520, a first clamp circuit 530, a second clamp circuit 540, a switch unit 550, a second output buffer 560, a third clamp circuit 570, and a fourth clamp circuit 580. .

The data channel 510 receives the display material PD2 and correspondingly provides the first driving voltage VD11 and the second driving voltage VD12. The first output buffer 520 is coupled to the data channel 510 to buffer the first driving voltage VD11. The second output buffer 560 is coupled to the data channel 510 to buffer the second driving voltage VD12. The first output buffer 520 and the second output buffer 560 can refer to the first output buffer 120a shown in FIG. 2.

The input end E1 of the switch unit 550 is coupled to the output end of the first output buffer 520 to receive the first driving voltage VD11, and the input end E2 of the switch unit 550 is coupled to the output end of the second output buffer 560 to receive the second driving voltage. VD12, and the switch unit 550 is controlled by the switch signal SWb to couple the input terminal E1 to one of the output terminals O1 and O2, and is controlled by the switch signal SWb to couple the input terminal E2 to the output terminals O1 and O2. another.

It is assumed that the output terminal O1 of the switch unit 550 is coupled to the data line 13 of the display panel 10 (corresponding to the first data line), and the output end O2 of the switch unit 550 is coupled to the data line 11 of the display panel 10 (corresponding to the second data line). . When the input terminal E1 of the switch unit 550 is coupled to the output terminal O1, the input terminal E2 of the switch unit 550 is coupled to the output terminal O2, and the first driving voltage VD11 provided by the first output buffer 520 is Provided to the data line 13 via the switching unit 550, the second driving voltage VD12 provided by the second output buffer 560 is supplied to the data line 11 via the switching unit 550. When the input terminal E1 of the switch unit 550 is coupled to the output terminal O2, the input terminal E2 of the switch unit 550 is coupled to the output terminal O1, and the first driving voltage VD11 provided by the first output buffer 520 is provided to the switch unit 550 via the switch unit 550. The second driving voltage VD12 supplied from the data line 11 and the second output buffer 560 is supplied to the data line 13 via the switching unit 550.

The first clamping circuit 530 is coupled to the first output buffer 520 and coupled to the data channel 510 to receive the first driving voltage VD11. After receiving the first driving voltage VD11, the first clamping circuit 530 provides the first clamping voltage VCP11 to the first output buffer 520 according to the first driving voltage VD11. The second clamping circuit 540 is coupled to the first output buffer 520 and coupled to the data channel 510 to receive the first driving voltage VD11. The second clamping circuit 540 receives the first driving voltage VD11 and provides a second clamping voltage VCP12 to the first output buffer 520.

The third clamping circuit 570 is coupled to the second output buffer 560 and coupled to the data channel 510 to receive the second driving voltage VD12. After receiving the second driving voltage VD12, the third clamping circuit 570 provides the third clamping voltage VCP13 to the second output buffer 560 according to the second driving voltage VD12. The fourth clamping circuit 580 is coupled to the second output buffer 560 and coupled to the data channel 510 to receive the second driving voltage VD12. The fourth clamping circuit 580 receives a second driving voltage VD12 to provide a fourth clamping voltage VCP14 to the second output buffer 560.

Receiving the first clamping voltage VCP11 and the second clamping voltage VCP12 Thereafter, the first output buffer 520 clamps the control voltage of the output stage of the first output buffer 520 according to the first clamping voltage VCP11 and the second clamping voltage VCP12 (refer to the teaching of the first output buffer 120a shown in FIG. 2) In order to avoid oscillation of the voltage at the output of the first output buffer 520 as it approaches the first driving voltage VD11. After receiving the third clamping voltage VCP13 and the fourth clamping voltage VCP14, the second output buffer 560 clamps the voltage of the control voltage of the output stage of the second output buffer 560 according to the third clamping voltage VCP13 and the fourth clamping voltage VCP14. The range (refer to the teaching of the first output buffer 120a shown in FIG. 2) prevents the voltage at the output of the second output buffer 560 from oscillating as it approaches the second driving voltage VD12. Therefore, the reaction speed of the first output buffer 520 in buffering the first driving voltage VD11 can be increased, and the reaction speed of the second output buffer 560 in buffering the second driving voltage VD12 can be increased.

Figure 6 is a circuit diagram of a source driver in accordance with a sixth embodiment of the present invention. Referring to FIG. 5 and FIG. 6, the source driver 600 is substantially the same as the source driver 500, and is different in the first clamp circuit 630, the second clamp circuit 640, the third clamp circuit 670, and the fourth clamp circuit 680, wherein the same Or similar elements use the same or similar reference numerals. The first clamping circuit 630 and the second clamping circuit 640 are coupled to the output terminals O1 and O2 of the switching unit 550 (equivalent to the data coupled to the output terminals O1 and O2) to receive the first transmission via the switching unit 550. A driving voltage VD11. The third clamping circuit 670 and the fourth clamping circuit 680 are coupled to the output terminals O1 and O2 of the switching unit 550 to receive the second driving voltage VD12 transmitted via the switching unit 550.

Further, when the input end E1 of the switch unit 550 is coupled to the output end At O1, the input terminal E2 of the switching unit 550 is coupled to the output terminal O2. At this time, the first clamping circuit 630 and the second clamping circuit 640 receive the first driving voltage VD11 outputted from the output terminal O1 of the switching unit 550 to provide the first clamping voltage VCP11 and the second clamping voltage VCP12, and the third clamping circuit 670 and The fourth clamping circuit 680 receives the second driving voltage VD12 outputted from the output terminal O2 of the switching unit 550 to provide a third clamping voltage VCP13 and a fourth clamping voltage VCP14. When the input terminal E1 of the switch unit 550 is coupled to the output terminal O2, the input terminal E2 of the switch unit 550 is coupled to the output terminal O1. At this time, the first clamping circuit 630 and the second clamping circuit 640 receive the first driving voltage VD11 outputted from the output terminal O2 of the switching unit 550 to provide the first clamping voltage VCP11 and the second clamping voltage VCP12, and the third clamping circuit 670 and The fourth clamping circuit 680 receives the second driving voltage VD12 outputted from the output terminal O1 of the switching unit 550 to provide a third clamping voltage VCP13 and a fourth clamping voltage VCP14.

Figure 7 is a circuit diagram of a source driver in accordance with a seventh embodiment of the present invention. Referring to FIGS. 6 and 7, the source driver 700 is substantially the same as the source driver 600, except for the first clamp circuit 630a, the second clamp circuit 640a, the third clamp circuit 670a, and the fourth clamp circuit 680a.

The first clamping circuit 630a includes a diode D11 (corresponding to a third diode) and a multiplexer MX1 (corresponding to the first multiplexer). The plurality of input ends of the multiplexer MX1 are respectively coupled to the output terminals O1 and O2 of the switch unit 550, and receive the switch signal SWb. The anode of the diode D11 is coupled to the output of the multiplexer MX1, and the cathode of the diode D11 provides the first clamp voltage VCP11. The second clamping circuit 640a includes a diode D12 (corresponding to a fourth diode) and a multiplexer MX2 (corresponding to a second multiplexer). Multiplexer The plurality of input ends of the MX2 are respectively coupled to the output terminals O1 and O2 of the switch unit 550, and receive the switch signal SWb. The cathode of the diode D12 is coupled to the output of the multiplexer MX2, and the anode of the diode D12 provides the second clamping voltage VCP12.

The third clamp circuit 670a includes a diode D13 (corresponding to the third diode) and a multiplexer MX3 (corresponding to the first multiplexer). The plurality of input ends of the multiplexer MX3 are respectively coupled to the output terminals O1 and O2 of the switch unit 550, and receive the switch signal SWb. The anode of the diode D13 is coupled to the output of the multiplexer MX3, and the cathode of the diode D13 provides a third clamp voltage VCP13. The fourth clamping circuit 680a includes a diode D14 (corresponding to the fourth diode) and a multiplexer MX2 (corresponding to the second multiplexer). The plurality of input ends of the multiplexer MX4 are respectively coupled to the output terminals O1 and O2 of the switch unit 550, and receive the switch signal SWb. The cathode of the diode D14 is coupled to the output of the multiplexer MX4, and the anode of the diode D14 provides the second clamping voltage VCP14.

According to the above, when the switch unit 550 is controlled by the switch signal SWb to couple the input terminal E1 to the output terminal O1 and the input terminal E2 to the output terminal O2, the multiplexers MX1 and MX2 are controlled by the switch signal SWb to switch. The output terminal O1 of the unit 550 is coupled to the anode of the diode D11 and the cathode of the diode D12, and the multiplexers MX3 and MX4 are controlled by the switch signal SWb to couple the output terminal O2 of the switch unit 550 to the diode. The anode of D13 and the cathode of diode D14. When the switch unit 550 is controlled by the switch signal SWb to couple the input terminal E1 to the output terminal O2 and the input terminal E2 to the output terminal O1, the multiplexers MX1 and MX2 are controlled by the switch signal SWb to the switch unit 550. The output terminal O2 is coupled to the anode of the diode D11 and the cathode of the diode D12, and the multiplexers MX3 and MX4 are controlled by the switching signal SWb to be turned on. The output terminal O1 of the off unit 550 is coupled to the anode of the diode D13 and the cathode of the diode D14.

In the embodiment of the present invention, the diodes (such as D1, D2, D11~D14) may be actual diodes, or the diodes (such as D1, D2, D11~D14) may be connected into two. A MOS transistor in the form of a polar body, but the implementation of the present invention is not limited thereto.

In summary, in the source driver of the embodiment of the present invention, the clamping circuit provides a clamping voltage according to the driving voltage to clamp the control voltage of the output stage of the output buffer. Thereby, the transient time required for the output buffer to buffer the driving voltage can be shortened to increase the reaction speed of the output buffer.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧ display panel

100‧‧‧Source Driver

11, 13‧‧‧ data line

110‧‧‧data channel

120‧‧‧First output buffer

130‧‧‧First clamp circuit

140‧‧‧Second clamp circuit

150‧‧‧Switch unit

PD1‧‧‧Display data

SW1‧‧‧ switch

SWa‧‧‧ switch signal

VCP1‧‧‧ first clamping voltage

VCP2‧‧‧Second clamp voltage

VD1‧‧‧first drive voltage

Claims (13)

A source driver includes: a data channel that receives a display data and provides a first driving voltage; a first output buffer coupled to the data channel to buffer the first driving voltage; a switching unit coupled The first output buffer and a first data line receive a switching signal to provide the first driving voltage to the first data line according to the switching signal; a first clamping circuit coupled to the first output buffer And receiving the first driving voltage to provide a first clamping voltage to the first output buffer according to the first driving voltage; and a second clamping circuit coupled to the first output buffer, and receiving the a first driving voltage to provide a second clamping voltage to the first output buffer according to the first driving voltage; wherein the first output buffer clamps the first according to the first clamping voltage and the second clamping voltage A control voltage of an output stage of the output buffer. The source driver of claim 1, wherein the first clamping circuit and the second clamping circuit are coupled to the first data line to receive the first driving voltage. The source driver of claim 1, wherein the first clamping circuit and the second clamping circuit are coupled to the data channel to receive the first driving voltage. The source driver of claim 1, further comprising: a second output buffer coupled to the data channel to buffer a second driving voltage provided by the data channel; a third clamping circuit coupled Connecting the second output buffer, and receiving the second driving voltage to provide a third clamping voltage to the second output buffer; and a fourth clamping circuit coupled to the second output buffer and receiving the a second driving voltage to provide a fourth clamping voltage to the second output buffer; wherein the switching unit is further coupled to the second output buffer and a second data line, the switching unit provides the One of the first driving voltage and the first driving voltage to the first data line and providing the other of the first driving voltage and the first driving voltage to the second data line, the second output buffer according to the The third clamping voltage and the fourth clamping voltage clamp a control voltage of an output stage of the second output buffer. The source driver of claim 4, wherein the first clamping circuit and the second clamping circuit are coupled to the data channel to receive the first driving voltage, the third clamping circuit and the fourth clamping circuit The data channel is coupled to receive the second driving voltage. The source driver of claim 5, wherein the first clamping circuit and the third clamping circuit respectively comprise: a first diode, the anode of the first diode receiving the first driving voltage Or the second driving voltage, the cathode of the first diode provides the first clamping voltage or the third clamping voltage. The source driver of claim 6, wherein the first clamping circuit and the third clamping circuit further comprise: a first switch, receiving the switching signal, and coupled to the first diode The anode is between the first driving voltage or the second driving voltage. The source driver of claim 5, wherein the second clamping circuit and the fourth clamping circuit respectively comprise: a second diode, the cathode of the second diode receiving the first driving voltage Or the second driving voltage, the anode of the second diode provides the second clamping voltage or the fourth clamping voltage. The source driver of claim 8, wherein the second clamp circuit and the fourth clamp circuit further comprise: a second switch, receiving the switch signal, and coupled to the second diode The cathode is between the first driving voltage or the second driving voltage. The source driver of the fourth aspect of the invention, wherein the first clamp circuit and the second clamp circuit are coupled to the first data line and the second data line to receive the first driving voltage, the third The clamping circuit and the fourth clamping circuit are coupled to the first data line and the second data line to receive the second driving voltage. The source driver of claim 10, wherein the first clamp circuit and the third clamp circuit respectively comprise: a first multiplexer, wherein the plurality of input ends of the first multiplexer are respectively coupled The first data line and the second data line, and receiving the switch signal; and a third diode, the anode of the third diode is coupled to the input of the first multiplexer The output terminal receives the first driving voltage or the second driving voltage, and the cathode of the third diode provides the first clamping voltage or the third clamping voltage. The source driver of claim 10, wherein the second clamp circuit and the fourth clamp circuit respectively comprise: a second multiplexer, wherein the plurality of input ends of the second multiplexer are respectively coupled The first data line and the second data line receive the switch signal; and a fourth diode, the cathode of the fourth diode is coupled to the output of the second multiplexer to receive the first The driving voltage or the second driving voltage, the anode of the fourth diode provides the second clamping voltage or the fourth clamping voltage. The source driver of claim 4, wherein the first output buffer and the second output buffer respectively comprise: an operational amplifier having a first input, a second input, and a first An output terminal and a second output terminal, the first input terminal receives the first driving voltage or the second driving voltage, the second input end is coupled to the switching unit, the first output end and a second output end Providing the control voltage respectively; a first transistor, the first end of the first transistor receiving a system voltage, and the control end of the first transistor is coupled to the first output end of the operational amplifier, the first The second end of the crystal outputs the buffered first driving voltage or the second driving voltage; and a second transistor, the first end of the second transistor is coupled to the second end of the first transistor, a control end of the second transistor is coupled to the second output end of the operational amplifier, and a second end of the second transistor receives a ground voltage; The first transistor and the second transistor are the output stages of the first output buffer or the second output buffer.