TWI750351B - Camera - Google Patents

Abstract

[Subject] To provide a photographing device capable of suppressing dark current. [Solution] An imaging device including a semiconductor substrate and a plurality of pixels, wherein the semiconductor substrate has a first diffusion region containing impurities of a first conductivity type, and a second diffusion region containing impurities of the first conductivity type; the plurality of Each pixel has a photoelectric conversion part that converts light into electric charge, and a first transistor; the first transistor includes a source electrode, a drain electrode and a gate electrode, and will store at least a part of the electric charge. The diffusion area is included as one of the source electrode and the drain electrode, and the second diffusion area is included as the other one of the source electrode and the drain electrode; the first conductive area in the first diffusion area is included The concentration of the impurity type is smaller than the concentration of the impurity of the first conductivity type in the second diffusion region; when viewed from the direction perpendicular to the semiconductor substrate, the area of the first diffusion region is smaller than that of the second diffusion region. Small area.

Description

camera

The present disclosure relates to photographing devices.

CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used in digital cameras and the like. It is well known that such image sensors have photodiodes formed on a semiconductor substrate.

On the other hand, there has been proposed a structure in which a photoelectric conversion portion having a photoelectric conversion layer is arranged above a semiconductor substrate (for example, Patent Documents 1 and 2). An imaging device having such a configuration is sometimes referred to as a multi-layer imaging device. In a multilayer imaging device, charges generated by photoelectric conversion are accumulated in a charge accumulation area (called "FD: floating diffusion"). A signal corresponding to the amount of charge accumulated in the charge accumulation area is read through a CCD circuit or a CMOS circuit formed on a semiconductor substrate. Prior art documents Patent documents

Patent Document 1: International Publication No. 2014/002330 Patent Document 2: International Publication No. 2012/147302

PROBLEMS TO BE SOLVED BY THE INVENTION In a multilayer imaging device, there is a possibility that the obtained image may be degraded due to leakage current (hereinafter, sometimes referred to as "dark current") from or to the charge accumulation area. It would be beneficial if such leakage current could be reduced.

means of solving problems

An imaging device related to an aspect of the present disclosure includes a semiconductor substrate having a first diffusion region including impurities of a first conductivity type and a second diffusion region including impurities of the first conductivity type, and a plurality of pixels. field; the plurality of pixels respectively have a photoelectric conversion part that converts light into electric charge, and a first transistor; the first transistor includes a source electrode, a drain electrode and a gate electrode, and will store at least a part of the electric charge The first diffusion area is included as one of the source and the drain, and the second diffusion area is included as the other of the source and the drain; in the first diffusion area The concentration of the impurity of the first conductivity type is smaller than the concentration of the impurity of the first conductivity type in the second diffusion region; when viewed from the direction perpendicular to the semiconductor substrate, the area of the first diffusion region is smaller than that of the first diffusion region. 2 The area of the diffusion field is small.

General or specific aspects can also be implemented as elements, devices, modules, systems or methods. In addition, general or specific aspects can also be implemented by any combination of elements, devices, modules, systems and methods.

The additional effects and advantages of the disclosed embodiments will be apparent from the description and drawings. Effects and/or advantages are provided by various embodiments or features disclosed in the description and drawings, and it is not necessary to use all of them in order to obtain one or more of them. Invention effect

According to the present disclosure, a photographing device capable of suppressing dark current can be provided.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A summary of one aspect of the present disclosure is as follows.

[Item 1] An imaging device comprising a semiconductor substrate and a plurality of pixels, the semiconductor substrate having a first diffusion domain containing an impurity of a first conductivity type, and a second diffusion domain comprising an impurity of the first conductivity type; the plurality of Each pixel has a photoelectric conversion part that converts light into electric charge, and a first transistor; the first transistor includes a source electrode, a drain electrode and a gate electrode, and stores at least a part of the electric charge. The diffusion area is included as one of the source electrode and the drain electrode, and the second diffusion area is included as the other one of the source electrode and the drain electrode; the first conductive area in the first diffusion area The concentration of the impurity type is smaller than the concentration of the impurity of the first conductivity type in the second diffusion region; when viewed from the direction perpendicular to the semiconductor substrate, the area of the first diffusion region is smaller than that of the second diffusion region. Small area.

In this way, the impurity concentration of the first conductivity type contained in the first diffusion region is smaller than the impurity concentration of the other diffusion regions containing the first conductivity type impurity in the pixel. Thereby, since the bonding density|concentration of the junction part of a 1st diffusion area|region and a semiconductor substrate is small, the leakage current in a 1st diffusion area|region is reduced.

Furthermore, the area of the depletion layer formed at the junction between the first diffusion region and the semiconductor substrate, especially the depletion layer on the surface of the semiconductor substrate, can be reduced. Since crystal defects become larger in the vicinity of the surface of the semiconductor substrate, if a depletion layer is formed there, the leakage current becomes larger. Therefore, the leakage current can be reduced by reducing the area of the depletion layer on the surface of the semiconductor substrate. [Item 2] The photographing device of item 1, wherein the semiconductor substrate further has a third diffusion region including impurities of the first conductivity type; the plurality of pixels respectively have a source electrode and a drain electrode with the third diffusion region as the source electrode and the drain electrode. One of the second transistors is included; the concentration of the impurity of the first conductivity type in the first diffusion region is smaller than the concentration of the impurity of the first conductivity type in the third diffusion region. [Item 3] The imaging device according to Item 1 or 2, wherein the plurality of pixels each have a third transistor including the first diffusion region as one of a source and a drain. [Item 4] The imaging device of item 1, wherein the area of the first diffusion region is an area of a portion of the first diffusion region that does not overlap the gate electrode when viewed from a direction perpendicular to the semiconductor substrate ; The area of the second diffusion area is an area of a portion of the second diffusion area that does not overlap with the gate electrode when viewed from a direction perpendicular to the semiconductor substrate.

[Item 5] The imaging device according to any one of Items 1 to 4, wherein the plurality of pixels respectively have a first plug connected to the first portion of the first diffusion area, and a first plug connected to the second The second plug connected to the second part of the diffusion area; when viewed from a direction perpendicular to the semiconductor substrate, the distance between the first part and the gate electrode is smaller than the distance between the second part and the gate electrode.

Thereby, since the distance from the 1st plug of the 1st diffusion area to the gate electrode of the 1st transistor is short, the rise of the resistance value of the 1st diffusion area can be reduced.

[Item 6] The imaging device according to any one of items 1 to 5, wherein the semiconductor substrate has a fourth diffusion area, and the fourth diffusion area includes impurities of a second conductivity type different from the first conductivity type; the plurality of Each pixel has transistors other than the first transistor, and the fourth diffusion area is included as a separate area separating the first transistor from the other transistors; the fourth diffusion area is included in the above-mentioned The surface of the semiconductor substrate is not in contact with the aforementioned first diffusion area.

In this way, on the surface of the semiconductor substrate where leakage current is most likely to occur, the first diffusion region containing impurities of the first conductivity type and the separation region containing impurities of the second conductivity type different from the first conductivity type are not in contact with each other. , so the leakage current of the junction on the surface of the semiconductor substrate can be reduced.

[Item 7] The imaging device according to any one of Items 1 to 6, wherein the semiconductor substrate includes impurities of a second conductivity type different from the first conductivity type; and impurities of the first conductivity type included in the first diffusion region The concentration of the impurity is 1×10 ¹⁶ atoms/cm ³ or more and 5×10 ¹⁶ atoms/cm ³ or less; the concentration of the impurity of the second conductivity type contained in the portion of the semiconductor substrate adjacent to the first diffusion region is 1 ×10 ¹⁶ atoms/cm ³ or more and 5×10 ¹⁶ atoms/cm ³ or less.

In this way, by reducing the concentrations of the impurities of the first conductivity type and the second conductivity type, it is possible to suppress the increase in the electric field strength at the junction between the first diffusion region and the semiconductor substrate, and to reduce the leakage current.

[Item 8] The imaging device according to any one of Items 1 to 7, wherein the first diffusion area is circular when viewed from a direction perpendicular to the semiconductor substrate.

Thereby, since the area of the first diffusion region on the surface of the semiconductor substrate is small, the area of the depletion layer formed at the junction on the surface of the semiconductor substrate can be reduced. Thereby, the leakage current can be reduced. [Item 9] An imaging device comprising a semiconductor substrate and a plurality of pixels, the semiconductor substrate having a first diffusion domain containing impurities of a first conductivity type, and a second diffusion domain comprising impurities of the first conductivity type; the plurality of Each pixel has: a photoelectric conversion part that converts light into electric charge; a first transistor including source, drain and gate electrodes, and uses the first diffusion area where at least a part of the electric charge is accumulated as the source electrode and one of the aforesaid drain electrodes, including the aforesaid second diffusion area as the other of the aforesaid source and the aforesaid drain electrodes; a first plug connected to the first part of the first diffusion area; The second plug is connected to the second portion of the second diffusion region; the concentration of the impurity of the first conductivity type in the first diffusion region is smaller than the concentration of the impurity of the first conductivity type in the second diffusion region ; When viewed from a direction perpendicular to the semiconductor substrate, the distance between the first portion and the gate electrode is smaller than the distance between the second portion and the gate electrode.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Incidentally, the embodiments described below are only general or specific examples. Numerical values, shapes, materials, constituent elements, arrangement and connection form of constituent elements, steps, order of steps, etc. shown in the following embodiments are examples, and are not intended to limit the present disclosure. Various aspects described in this specification can be combined with each other as long as there is no conflict. In addition, among the components of the following embodiment, the component which is not described in the independent claim which shows the highest concept is demonstrated as an arbitrary component. In each drawing, components having substantially the same function are shown by common reference numerals, and overlapping descriptions may be omitted or simplified in some cases.

In addition, various elements shown in the drawings are only schematic representations for understanding the present disclosure, and size ratios and appearances may be different from actual ones.

Incidentally, in this manual, the light-receiving side of the imaging device is referred to as "upper side", and the opposite side of the light-receiving side is referred to as "lower side". The same applies to the "upper surface" and "lower surface" of each member, and the surface facing the light-receiving side of the imaging device is referred to as the "upper surface", and the surface opposite to the light-receiving side is referred to as the "lower surface". Incidentally, the terms "above", "below", "above" and "below" are only used to designate the mutual arrangement of components, and are not intended to limit the posture when using the camera.

(Embodiment) Fig. 1 is a configuration diagram of an imaging device according to this embodiment. As shown in FIG. 1 , an imaging device 100A according to this embodiment includes a plurality of pixels 10A and peripheral circuits 40 formed on a semiconductor substrate 60 . Each pixel 10A has the photoelectric conversion portion 12 disposed above the semiconductor substrate 60 . That is, the imaging device 100A of the multilayer type will be described as an example of the imaging device related to the present disclosure.

In the example shown in FIG. 1, the pixels 10A are arranged in a matrix of m columns and n rows. Here, m and n are integers of 2 or more. The pixels 10A are, for example, arranged in two dimensions on the semiconductor substrate 60 , thereby forming the imaging region R1 . As described above, each pixel 10A has the photoelectric conversion portion 12 disposed above the semiconductor substrate 60 . Therefore, the imaging area R1 is defined as the area covered by the photoelectric conversion portion 12 in the semiconductor substrate 60 . Incidentally, although the photoelectric conversion parts 12 of the pixels 10A are shown as being spatially separated from each other in FIG. 1 for convenience of description, the photoelectric conversion parts 12 of a plurality of pixels 10A may be arranged on the semiconductor substrate without being separated from each other. 60 on.

The number and arrangement of the pixels 10A are not limited to the illustrated example. For example, the number of pixels 10A included in the photographing device 100A may also be one. Although in this example, the center of each pixel 10A is located on the grid point of the square grid, the arrangement of the pixel 10A may not be the same. For example, the plurality of pixels 10A may also be arranged such that each center is located on a grid point of a triangular grid, a hexagonal grid, or the like. If the pixels 10A are arranged in one dimension, the imaging device 100A can be used as a linear sensor.

1 , the peripheral circuit 40 includes a vertical scanning circuit (also referred to as a “column scanning circuit”) 46 and a horizontal signal reading circuit (also referred to as a “row scanning circuit”) 48 . The vertical scanning circuit 46 is connected to the address signal line 34 provided corresponding to each column of the plurality of pixels 10A. The horizontal signal readout circuit 48 is connected to the vertical signal lines 35 corresponding to each row of the plurality of pixels 10A. As shown schematically in FIG. 1 , these circuits are arranged in the peripheral area R2 outside the photographing area R1 . The peripheral circuit 40 may further include a signal processing circuit, an output circuit, a control circuit, a power supply for supplying a predetermined voltage to each pixel 10A, and the like. A part of the peripheral circuit 40 may be arranged on a different substrate than the semiconductor substrate 60 on which the pixel 10A is formed.

FIG. 2 is a diagram showing the circuit configuration of the imaging device 100A according to the embodiment. In order to avoid the complexity of the picture, FIG. 2 shows four pixels 10A arranged in two rows and two columns among the plurality of pixels 10A shown in FIG. 1 .

The photoelectric conversion portion 12 of each pixel 10A is subjected to incident light to generate positive and negative charges (typically, hole-electron pairs). The photoelectric conversion portion 12 of each pixel 10A is connected to the accumulation control line 39, and when the imaging device 100A operates, the accumulation control line 39 is applied with a predetermined voltage. By applying a predetermined voltage to the accumulation control line 39, the electric charge of one of the positive and negative electric charges generated by photoelectric conversion can be selectively accumulated in the electric charge accumulation area. The following example shows the case where the positive charge among the positive and negative charges generated by photoelectric conversion is used as the signal charge.

Each pixel 10A includes a signal detection circuit 14 electrically connected to the photoelectric conversion unit 12 . In the structure shown as an example in FIG. 2 , the signal detection circuit 14 includes an amplifier transistor 22 (also called a “read transistor”) and a reset transistor 26 . In this example, the signal detection circuit 14 further includes an address transistor (also referred to as a "column select transistor") 24 . As described in detail later with reference to the drawings, the amplifier transistor 22 , the reset transistor 26 and the address transistor 24 of the signal detection circuit 14 are typically field effect transistors formed on the semiconductor substrate 60 supporting the photoelectric conversion portion 12 (FET: Field Effect Transistor). Hereinafter, unless otherwise mentioned, an N-channel MOS (Metal Oxide Semiconductor) transistor is used as an example of the transistor. Incidentally, which of the two diffusion layers of the FET corresponds to the source and the drain is determined by the polarity of the FET and the level of the potential at that time. Therefore, which one is the source and the drain varies with the operating state of the FET.

As shown schematically in FIG. 2 , the gate of the amplifier transistor 22 is electrically connected to the photoelectric conversion part 12 . The charges generated by the photoelectric conversion unit 12 are accumulated in the charge accumulation node (also referred to as “Floating Diffusion node”) ND connected between the photoelectric conversion unit 12 and the amplifier transistor 22 . Incidentally, the charge accumulation node ND refers to a wire that electrically connects the charge accumulation area, the gate of the amplifier transistor 22 , and the lower electrode of the photoelectric conversion unit 12 , and the charge accumulation area.

The drain of the amplifier transistor 22 is connected to a power supply line (also called a source-follower power supply) 32 that supplies a predetermined power supply voltage VDD (eg, about 3.3V) to each pixel 10A when the photographing device 100A operates. In other words, the amplifier transistor 22 outputs a signal voltage corresponding to the amount of the signal charge generated by the photoelectric conversion unit 12 . The source of the amplifier transistor 22 is connected to the drain of the address transistor 24 .

The source of the address transistor 24 is connected to the vertical signal line 35 . As shown in the figure, the vertical signal lines 35 are arranged according to the rows of the plurality of pixels 10A, and the vertical signal lines 35 are respectively connected with the load circuit 42 and the column signal processing circuit (also called “column signal accumulation circuit”) 44. The load circuit 42 forms a source follower circuit together with the booster transistor 22 .

The gate of the address transistor 24 is connected to the address signal line 34 . The address signal lines 34 are arranged according to each row of the plurality of pixels 10A. The address signal line 34 is connected to the vertical scanning circuit 46 , and the vertical scanning circuit 46 applies a column selection signal to the address signal line 34 to control the on and off of the address transistor 24 . Thereby, the column to be read is scanned in the vertical direction (row direction), and the column to be read is selected. The vertical scanning circuit 46 controls the on and off of the address transistor 24 through the address signal line 34 , thereby the output of the amplifier transistor 22 of the selected pixel 10A can be read by the corresponding vertical signal line 35 . The arrangement of the address transistor 24 is not limited to the example shown in FIG. 2 , and may be between the drain of the amplifier transistor 22 and the power supply wiring 32 .

The signal voltages from the pixels 10A output to the vertical signal lines 35 through the address transistors 24 are input to the plurality of column signal processing circuits 44 corresponding to the vertical signal lines 35 and disposed in the rows of the plurality of pixels 10A. The corresponding column signal processing circuit 44 . The column signal processing circuit 44 and the load circuit 42 may be part of the peripheral circuit 40 described above.

The column signal processing circuit 44 performs noise suppression signal processing represented by correlated double sampling and analog-to-digital conversion (AD conversion). The column signal processing circuit 44 is connected to the horizontal signal reading circuit 48 . The horizontal signal reading circuit 48 sequentially reads the signals from the plurality of column signal processing circuits 44 to the horizontal common communication signal line 49 .

In the configuration shown as an example in FIG. 2 , the signal detection circuit 14 includes a reset transistor 26 whose drain is connected to the charge accumulation node ND. The gate of the reset transistor 26 is connected to the reset signal line 36 connected to the vertical scanning circuit 46 . The reset signal lines 36 are provided in the same manner as the address signal lines 34 for each row of the plurality of pixels 10A. The vertical scanning circuit 46 can select the pixel 10A to be reset in units of columns by applying the column selection signal to the address signal line 34 . In addition, the vertical scan circuit 46 can make the reset transistors in the selected row by applying the reset signal that controls the on and off of the reset transistor 26 to the gate of the reset transistor 26 through the reset signal line 36 . 26 on. As the reset transistor 26 is turned on, the potential of the charge accumulation node ND is reset.

In this example, the source of the reset transistor 26 is connected to one of the feedback lines 53 provided for each row of the plurality of pixels 10A. That is, in this example, the voltage of the feedback line 53 is supplied to the charge storage node ND as the reset voltage for initializing the charge of the photoelectric conversion portion 12 . Here, the above-mentioned feedback line 53 is connected to the output terminal of one of the inverse amplifiers corresponding to the inverse amplifiers 50 provided according to the rows of the plurality of pixels 10A. The reverse amplifier 50 may be part of the peripheral circuit 40 described above.

Focus on one of the rows of the plurality of pixels 10A. As shown in the figure, the reverse input terminal of the reverse amplifier 50 is connected to the vertical signal line 35 of the row. In addition, the output terminal of the reverse amplifier 50 and the one or more pixels 10A belonging to the row are connected through the feedback line 53 . When the photographing device 100A operates, the non-inverting input terminal of the inverting amplifier 50 is supplied with a predetermined voltage Vref (for example, a positive voltage near 1V or 1V). By selecting one of the more than one pixels 10A belonging to the row, the address transistor 24 and the reset transistor 26 can be turned on to form a feedback path that negatively feedbacks the output of the pixel 10A. Due to the formation of the feedback path, the voltage of the vertical signal line 35 converges toward the input voltage Vref for the non-inverting input terminal of the inverting amplifier 50 . In other words, due to the formation of the feedback path, the voltage of the charge accumulation node ND and the voltage of the vertical signal line 35 are reset to a voltage like Vref. As for the voltage Vref, a voltage of any magnitude within the range of a power supply voltage (eg, 3.3V) and a ground voltage (0V) can be used. The flyback amplifier 50 may also be referred to as a feedback amplifier. In this way, the photographing apparatus 100A has the feedback circuit 16 including the reverse amplifier 50 in a part of the feedback path.

It is well known that thermal noise known as kTC noise occurs as transistors are turned on or off. The noise that occurs as the reset transistor is turned on or off is called reset noise. The reset noise generated by turning off the reset transistor after resetting the potential of the charge accumulation area remains in the charge accumulation area before the signal charge is accumulated. However, the reset noise that occurs as the reset transistor is turned off can be reduced by utilizing feedback. In International Publication No. 2012/147302, the details of suppressing reset noise by using feedback are described. For reference, the disclosure content of International Publication No. 2012/147302 is incorporated into this specification in its entirety.

In the configuration illustrated in FIG. 2 , due to the formation of the feedback path, the AC component of the thermal noise is fed back to the source of the reset transistor 26 . In the configuration exemplified in FIG. 2, since the feedback path is formed until just before the reset transistor 26 is turned off, it is possible to reduce the reset noise that occurs when the reset transistor 26 is turned off.

FIG. 3 is a plan view showing the layout in the pixel 10A of the embodiment. FIG. 4 is a schematic cross-sectional view showing the device configuration of the pixel 10A. FIG. 3 schematically shows each element (amplifier transistor 22, address transistor 24, and reset transistor 26) formed on the semiconductor substrate 60 when the pixel 10A shown in FIG. 4 is viewed from a direction perpendicular to the semiconductor substrate 60. etc.) configuration. Here, the amplifier transistor 22 and the address transistor 24 are linearly arranged along the up-down direction of the paper surface.

FIG. 4 is a schematic cross-sectional view of the device structure of the pixel 10A according to the embodiment. FIG. 4 is a cross-sectional view when the pixel 10A is cut along the line A-A in FIG. 3 and expanded in the direction of the arrow.

Incidentally, in FIGS. 3 and 4 , the first diffusion region 67n which is an n-type impurity region is the drain region of the reset transistor 26 and is a charge accumulation region (FD).

As shown in FIGS. 3 and 4 , the pixel 10A of the imaging device 100A according to this embodiment has a first transistor (here, the reset transistor 26 ). The first transistor is located in the semiconductor substrate, contains impurities of the first conductivity type (hereinafter referred to as n-type), and uses the first diffusion region 67n where the photoelectric charges converted by the photoelectric conversion section 12 are stored as the source and the first diffusion region 67n. One of the drain electrodes is included, and the second diffusion region 68an, which is an n-type impurity region including n-type impurities, is included as the other of the source electrode and the drain electrode. In the present embodiment, the concentration of the n-type impurity in the first diffusion region 67n is smaller than the concentration of the n-type impurity in the second diffusion region 68an.

Furthermore, the pixel 10A has a second transistor (here, the amplifier transistor 22 or the address transistor 24) that is different from the reset transistor 26. The second transistor is located in the semiconductor substrate 60 and will include an n-type transistor. The third impurity diffusion region (hereinafter, referred to as the other n-type impurity regions 68bn, 68cn, and 68dn) is included as a source or a drain. At this time, the n-type impurity concentration of the first diffusion region 67n may be smaller than the n-type impurity concentration of the other n-type impurity regions 68bn, 68cn, and 68dn (hereinafter referred to as 68bn to 68dn). In this case, the concentration of the n-type impurity in the first diffusion region 67n may be at least 1/10 of the concentration of the n-type impurities in the second diffusion region 68an and the other n-type impurity regions 68bn to 68dn, or may be smaller than 1 /15 small. As a result, since the bonding concentration at the bonding portion between the first diffusion region 67n and the semiconductor substrate 60 is small, the electric field strength at the bonding portion can be reduced. Therefore, the leakage current from the first diffusion region 67n, which is itself a charge accumulation region, or to the first diffusion region 67n is reduced.

In addition, the imaging device 100A according to the present embodiment may be such that the semiconductor substrate 60 contains impurities of the second conductivity type (hereinafter referred to as p-type), the concentration of the n-type impurities contained in the first diffusion region 67n, and the semiconductor The concentration of the p-type impurity contained in the portion of the substrate 60 adjacent to the first diffusion region 67n is 1×10 ¹⁶ atoms/cm ³ or more and 5×10 ¹⁶ atoms/cm ³ or less. Thereby, the bonding concentration between the first diffusion region 67n and the semiconductor substrate 60 is small, and the increase of the electric field intensity at the bonding portion can be suppressed. Therefore, the leakage current at the junction can be reduced.

As schematically shown in FIG. 4 , the pixel 10A roughly includes a semiconductor substrate 60 , a photoelectric conversion portion 12 disposed above the semiconductor substrate 60 , and a wiring structure 80 . The wiring structure 80 is arranged in the interlayer insulating layer 90, and has a structure for electrically connecting the amplifier transistor 22 formed on the semiconductor substrate 60 and the photoelectric conversion portion 12, wherein the interlayer insulating layer 90 is formed on the photoelectric conversion portion 12 and the semiconductor. between the substrates 60 . Here, the interlayer insulating layer 90 has a laminated structure including four insulating layers of insulating layers 90a, 90b, 90c, and 90d (hereinafter, referred to as 90a to 90d.), and the wiring structure 80 has wiring layers 80a, 80b, 80c, and 80d (hereinafter referred to as 80a to 80d.) 4-layer wiring layers, and plugs pa1, pa2, pb, pc, and pd arranged between the wiring layers. In addition, the wiring layer 80a includes contact plugs cp1, cp2, cp3, cp4, cp5, cp6, and cp7 (hereinafter referred to as cp1 to cp7). Incidentally, as a matter of course, the number of insulating layers in the interlayer insulating layer 90 and the number of wiring layers in the wiring structure 80 are not limited to this example, and can be arbitrarily set.

The photoelectric conversion part 12 is arranged on the interlayer insulating layer 90 . The photoelectric conversion portion 12 includes a pixel electrode 12a formed on the interlayer insulating layer 90, a transparent electrode 12c facing the pixel electrode 12a, and a photoelectric conversion layer 12b disposed between the electrodes. The photoelectric conversion layer 12b of the photoelectric conversion portion 12 is formed of an organic material or an inorganic material such as amorphous silicon, receives incident light through the transparent electrode 12c, and generates positive and negative charges by photoelectric conversion. The photoelectric conversion layer 12b is typically formed across the plurality of pixels 10A. In addition, the photoelectric conversion layer 12b may include a layer composed of an organic material and a layer composed of an inorganic material.

The transparent electrode 12c is formed of a transparent conductive material such as ITO, and is disposed on the light-receiving surface side of the photoelectric conversion layer 12b. Like the photoelectric conversion layer 12b, the transparent electrode 12c is typically formed across the plurality of pixels 10A. Although the illustration is omitted in FIG. 4 , the transparent electrode 12c is connected to the above-described accumulation control line 39 . When the photographing device 100A operates, the potential of the transparent electrode 12c can be different from that of the pixel electrode 12a by controlling the potential of the accumulation control line 39, so that the signal charge generated by the photoelectric conversion can be collected by the pixel electrode 12a. For example, the potential of the accumulation control line 39 is controlled such that the potential of the transparent electrode 12c is higher than the potential of the pixel electrode 12a. Specifically, for example, a positive voltage of about 10V is applied to the accumulation control line 39 . Thereby, the holes in the hole-electron pair generated in the photoelectric conversion layer 12b can be collected by the pixel electrode 12a. The signal charges collected by the pixel electrode 12a are accumulated in the first diffusion region 67n through the wiring structure 80 .

The pixel electrode 12a is an electrode formed of metals such as aluminum and copper, metal nitrides, or polysilicon to which conductivity is imparted by doping impurities. The pixel electrode 12a is spatially separated from the pixel electrode 12a of the other adjacent pixel 10A, thereby being electrically separated from the pixel electrode 12a of the other pixel 10A.

The semiconductor substrate 60 includes a support substrate 61 and one or more semiconductor layers formed on the support substrate 61 . Here, the support substrate 61 is shown by taking a p-type silicon (Si) substrate as an example. In this example, the semiconductor substrate 60 has a p-type semiconductor layer 61p on a support substrate 61, an n-type semiconductor layer 62n on the p-type semiconductor layer 61p, a p-type semiconductor layer 63p on the n-type semiconductor layer 62n, and a p-type semiconductor p-type semiconductor layer 65p on layer 63p. The p-type semiconductor layer 63p is formed across the entire surface of the support substrate 61 . The p-type semiconductor layer 65p has a p-type impurity region 66p having a lower impurity concentration than the p-type semiconductor layer 65p, a first diffusion region 67n, a second diffusion region 68an and an n-type impurity region 68bn formed in the p-type impurity region 66p ~68dn, component separation area 69.

The semiconductor layers of the p-type semiconductor layer 61p, the n-type semiconductor layer 62n, the p-type semiconductor layer 63p, and the p-type semiconductor layer 65p are typically formed by implanting impurity ions into the semiconductor layers formed by epitaxial growth. The impurity concentrations of the p-type semiconductor layer 63p and the p-type semiconductor layer 65p are approximately the same as each other, and are higher than the impurity concentration of the p-type semiconductor layer 61p. The n-type semiconductor layer 62n disposed between the p-type semiconductor layer 61p and the p-type semiconductor layer 63p is a first diffusion area that suppresses minority carriers from the support substrate 61 or the peripheral circuit 40 and is a charge accumulation area that accumulates signal charges 67n inflow situation. During the operation of the imaging device 100A, the potential of the n-type semiconductor layer 62n is controlled through a well contact (not shown) provided outside the imaging region R1 (refer to FIG. 1 ).

In addition, in this example, the semiconductor substrate 60 has a p-type region 64 provided between the p-type semiconductor layer 63p and the support substrate 61 by penetrating the p-type semiconductor layer 61p and the n-type semiconductor layer 62n. The p-type region 64 has a higher impurity concentration than the p-type semiconductor layer 63p and the p-type semiconductor layer 65p, and is electrically connected to the p-type semiconductor layer 63p and the support substrate 61 . During the operation of the imaging device 100A, the potentials of the p-type semiconductor layer 63p and the support substrate 61 are controlled through a substrate contact (not shown) provided outside the imaging area R1. The p-type semiconductor layer 65p is disposed in contact with the p-type semiconductor layer 63p, whereby the potential of the p-type semiconductor layer 65p can be controlled through the p-type semiconductor layer 63p during the operation of the imaging device 100A.

The amplifier transistor 22 , the address transistor 24 , and the reset transistor 26 are formed on the semiconductor substrate 60 . The reset transistor 26 includes a first diffusion region 67n, a second diffusion region 68an, an insulating layer 70 formed on the semiconductor substrate 60, and a gate electrode 26e on the insulating layer 70. The first diffusion region 67n and the second diffusion region 68an function as a drain region and a source region of the reset transistor 26, respectively. The first diffusion region 67n functions as a charge storage region that temporarily stores the signal charge generated by the photoelectric conversion unit 12 .

The amplifier transistor 22 includes n-type impurity domains 68bn and 68cn, a portion of the insulating layer 70 , and a gate electrode 22e on the insulating layer 70 . The n-type impurity regions 68bn and 68cn function as the drain region and the source region of the amplifier transistor 22, respectively.

An element isolation region 69 is arranged between the n-type impurity region 68bn and the first diffusion region 67n. The element separation area 69 is, for example, a p-type impurity diffusion area. The boost transistor 22 and the reset transistor 26 are electrically separated by the element separation area 69 .

As schematically shown in FIG. 4 , the first diffusion region 67n is formed in the p-type impurity region 66p, whereby the first diffusion region 67n and the element isolation region 69 are arranged so as not to contact each other. For example, when a p-type impurity layer is used as the element isolation region 69, if the first diffusion region 67n is in contact with the element isolation region 69, both the p-type impurity concentration and the n-type impurity concentration in the junction are changed. high. Therefore, leakage current due to the high junction concentration tends to occur around the junction between the first diffusion region 67n and the element isolation region 69 . In other words, by arranging the first diffusion region 67n and the element isolation region 69 so as not to contact each other, even if a high-concentration p-type impurity layer is used in the element isolation region 69, the increase in the pn junction concentration can be suppressed. Suppress leakage current. In addition, although there is a method of using STI (Shallow Trench Isolation) as the element isolation region 69, in this case, in order to reduce the leakage current due to crystal defects in the sidewall portion of the STI, it is preferable to separate the first diffusion region 67n from the STI. arranged without touching each other.

A component separation area 69 is also disposed between the adjacent pixels 10A, and the signal detection circuits 14 are electrically separated therebetween. Here, the element separation area 69 is provided around the group of the amplifier transistor 22 and the address transistor 24 and around the reset transistor 26 .

The address transistor 24 includes n-type impurity domains 68cn and 68dn, a portion of the insulating layer 70 , and a gate electrode 24e on the insulating layer 70 . In this example, the address transistor 24 is electrically connected to the amplifier transistor 22 by sharing the n-type impurity domain 68cn with the amplifier transistor 22 . The n-type impurity field 68cn functions as the drain field of the address transistor 24 , and the n-type impurity field 68dn functions as the source field of the address transistor 24 .

In this example, the insulating layer 72 is provided so as to cover the gate electrode 26e of the reset transistor 26, the gate electrode 22e of the amplifier transistor 22, and the gate electrode 24e of the address transistor 24. The insulating layer 72 is, for example, a silicon oxide film. In this example, the insulating layer 71 is further interposed between the insulating layer 72 and the gate electrode 26e, the gate electrode 22e, and the gate electrode 24e. The insulating layer 71 is, for example, a silicon oxide film. The insulating layer 71 may have a laminated structure including a plurality of insulating layers. Similarly, the above-mentioned insulating layer 72 may have a laminated structure including a plurality of insulating layers.

The laminated structure of the insulating layer 72 and the insulating layer 71 has a plurality of contact holes. Here, contact holes h1 to h7 are formed in the insulating layer 72 and the insulating layer 71 . The contact holes h1 to h4 are formed at positions overlapping the first diffusion region 67n, the second diffusion region 68an, and the other n-type impurity regions 68bn and 68dn, respectively. Contact plugs cp1 to cp4 are arranged at the positions of the contact holes h1 to h4, respectively. The contact holes h5 to h7 are formed at positions overlapping with the gate electrode 26e, the gate electrode 22e, and the gate electrode 24e, respectively. Contact plugs cp5 to cp7 are arranged at the positions of the contact holes h5 to h7, respectively.

In the configuration shown as an example in FIG. 4, the wiring layer 80a is a layer having contact plugs cp1-cp7, typically a polysilicon layer doped with n-type impurities. Among the wiring layers included in the wiring structure 80 , the wiring layer 80 a is arranged closest to the semiconductor substrate 60 . The wiring layer 80b and the plugs pa1 and pa2 are arranged in the insulating layer 90a. The plug pa1 connects the contact plug cp1 to the wiring layer 80b, and the plug pa2 connects the contact plug cp6 to the wiring layer 80b. That is, the first diffusion region 67n and the gate electrode 22e of the amplifier transistor 22 are electrically connected to each other through the contact plugs cp1, cp6, the plugs pa1, pa2, and the wiring layer 80b.

The wiring layer 80b is disposed in the insulating layer 90a, and may include the above-mentioned vertical signal lines 35, address signal lines 34, power supply lines 32, reset signal lines 36, and feedback lines 53. The vertical signal line 35, the address signal line 34, the power supply line 32, the reset signal line 36, and the feedback line 53 are connected to the n-type impurity area 68dn and the gate electrode 24e through the contact plugs cp4, cp7, cp3, cp5, and cp2, respectively. , the n-type impurity region 68bn, the gate electrode 26e, and the second diffusion region 68an are connected.

The plug pb arranged in the insulating layer 90b connects the wiring layer 80b and the wiring layer 80c. Similarly, the plug pc arranged in the insulating layer 90c connects the wiring layer 80c and the wiring layer 80d. The plug pd disposed in the insulating layer 90d connects the wiring layer 80d to the pixel electrode 12a of the photoelectric conversion portion 12 . The wiring layers 80b to 80d, and the plugs pa1, pa2, and pb to pd are typically formed of metals such as copper or tungsten, metal nitrides, or metal compounds such as metal oxides.

The plugs pa1 , pa2 , pb to pd , the wiring layers 80 b to 80 d , and the contact plugs cp1 and cp6 electrically connect the photoelectric conversion unit 12 and the signal detection circuit 14 formed on the semiconductor substrate 60 . The plugs pa1, pa2, pb~pd, the wiring layers 80b~80d, the contact plugs cp1, cp6, the pixel electrode 12a of the photoelectric conversion part 12, the gate electrode 22e of the amplifier transistor 22, and the first diffusion area 67n are The signal charges (here, holes) generated by the photoelectric conversion unit 12 are accumulated.

Here, attention is paid to the n-type impurity region formed in the semiconductor substrate 60 . In the n-type impurity region formed in the semiconductor substrate 60, the first diffusion region 67n is arranged in the p-type impurity region 66p formed in the p-type semiconductor layer 65p as a p-well. The first diffusion region 67 n is formed near the surface of the semiconductor substrate 60 , and at least a part thereof is located on the surface of the semiconductor substrate 60 . The junction capacitance formed by the pn junction between the p-type impurity region 66p and the first diffusion region 67n functions as a capacitance for storing at least a part of the signal charge, and constitutes a part of the charge accumulation region.

In the configuration shown as an example in FIG. 4, the first diffusion area 67n includes a first area 67a and a second area 67b. The impurity concentration of the first region 67a of the first diffusion region 67n is lower than that of the second diffusion region 68an and the other n-type impurity regions 68bn to 68dn. The second region 67b in the first diffusion region 67n is formed in the first region 67a and has a higher impurity concentration than the first region 67a. In addition, the contact hole h1 is located on the second area 67b, and the contact plug cp1 is connected to the second area 67b through the contact hole h1.

As described above, the p-type semiconductor layer 65p is disposed adjacent to the p-type semiconductor layer 63p, whereby the potential of the p-type semiconductor layer 65p can be controlled through the p-type semiconductor layer 63p during the operation of the imaging device 100A. By adopting such a structure, around the contact plug cp1 electrically connected to the photoelectric conversion portion 12 and the portion in contact with the semiconductor substrate 60 (here, the second area 67b of the first diffusion area 67n), Regions with relatively low impurity concentrations (here, the first region 67a of the first diffusion region 67n and the p-type impurity region 66p) are arranged. It is not necessary to form the second area 67b in the first diffusion area 67n. However, by making the impurity concentration of the second region 67b which is the connecting portion of the contact plug cp1 and the semiconductor substrate 60 high, the suppression of the depletion layer from spreading around the connecting portion of the contact plug cp1 and the semiconductor substrate 60 can be obtained. (depletion) effect. In this way, by suppressing depletion around the portion where the contact plug cp1 is in contact with the semiconductor substrate 60 , crystal defects of the semiconductor substrate 60 (which may also be referred to as the interface between the contact plug cp1 and the semiconductor substrate 60 ) can be suppressed. interface state) leakage current. In addition, by connecting the contact plug cp1 to the second region 67b having a higher impurity concentration, the effect of reducing the contact resistance can be obtained.

In addition, in this example, the second domain 67b of the first diffusion domain 67n and the p-type impurity domain 66p are separated by a first domain 67a having a lower impurity concentration than the second domain 67b, the second domain 67b of the first diffusion domain 67n and The first region 67a is also interposed between the p-type semiconductor layers 65p. By arranging the first region 67a with a relatively low impurity concentration around the second region 67b, the electric field strength formed by the pn junction between the first diffusion region 67n and the p-type semiconductor layer 65p or the p-type impurity region 66p can be reduced. By relaxing the electric field strength, the leakage current due to the electric field formed by the pn junction is suppressed.

As schematically shown in FIG. 3 , the pixel 10A has: the reset transistor 26, and has the first diffusion area 67n and the second diffusion area 68an as source and drain electrodes; a separation area (hereinafter, referred to as an element separation area 69) .), the other transistors (here, the amplifier transistor 22 and the address transistor 24) possessed by the pixel 10A are separated from each other. The element isolation region 69 contains, for example, impurities of the second conductivity type (hereinafter referred to as p-type) different from the n-type. At this time, the first diffusion region 67n and the element isolation region 69 formed around the first diffusion region 67n are arranged on the surface of the semiconductor substrate 60 so as not to contact each other.

Specifically, the first diffusion region 67n is formed in the p-type impurity region 66p having an impurity concentration lower than that of the p-type semiconductor layer 65p. A depletion layer region is formed between the first diffusion region 67n and the p-type impurity region 66p. Generally, the density of crystal defects in the vicinity of the surface of the semiconductor substrate 60 is higher than that in the interior of the semiconductor substrate 60 . Therefore, the leakage current ratio of the depletion layer region formed at the junction (pn junction) that joins the first diffusion region 67n and the p-type impurity region 66p to the depletion layer region formed at the junction near the surface of the semiconductor substrate 60 The leakage current in the region of the depletion layer formed at the pn junction inside the semiconductor substrate 60 is large.

In addition, if the area of the depletion layer region (hereinafter referred to as the interface depletion layer) formed at the junction on the surface of the semiconductor substrate 60 increases, the leakage current tends to increase. Therefore, it is preferable to minimize the area of the interface depletion layer exposed on the surface of the semiconductor substrate 60 . In order to make the area of the interface depletion layer small, the area of the first diffusion region 67n may be smaller than that of the second diffusion region 68an when viewed from the direction perpendicular to the semiconductor substrate 60 . For example, when viewed from the direction perpendicular to the semiconductor substrate 60, the area of the first diffusion area 67n may be less than 1/2 of the area of the second diffusion area 68an. In addition, in this case, the width in the channel width direction of the first diffusion region 67n may be equal to or less than 1/2 of the width in the channel width direction of the second diffusion region 68an. Incidentally, the first diffusion area 67n and the second diffusion area 68an may have the same size as one of the width in the channel width direction and the length in the channel length direction. In addition, the same applies to the other n-type impurity regions 68bn to 68dn in the pixel 10A, and the area of the first diffusion region 67n when viewed from the direction perpendicular to the semiconductor substrate 60 may be larger than that of the other n-type impurity regions 68bn to 68dn. formed in a small area.

In addition, the areas of the first diffusion region 67n and the second diffusion region 68an may also be the same as those of the reset transistor 26 in the first diffusion region 67n and the second diffusion region 68an when viewed from a direction perpendicular to the semiconductor substrate. The area of the portion where the gate electrodes 26e overlap. Similarly, the area of the other n-type impurity regions 68bn to 68dn can also be viewed from the direction perpendicular to the semiconductor substrate 60 , which is different from the gate of the amplifier transistor 22 in the other n-type impurity regions 68bn to 68dn. The area of the portion where the electrode 22e and the gate electrode 24e of the address transistor 24 overlap. The portion overlapping the gate electrodes 22e, 24e, 26e of the transistors when viewed from the direction perpendicular to the semiconductor substrate 60 is more difficult to sustain damage during manufacture than the portion not overlapping the gate electrodes 22e, 24e, 26e . As for the damage during manufacture, for example, it is caused by the plasma treatment used in the dry etching process and the ashing treatment when the photoresist is peeled off. As a result, leakage current is less likely to occur in the portions overlapping with the gate electrodes 22e, 24e, and 26e. Therefore, in order to reduce the area of the interface depletion layer, regarding the first diffusion region 67n and the other n-type impurity regions 68bn to 68dn, only the influence of the area of the portion not overlapping with the gate electrode may be considered.

In addition, by making the area of the first diffusion region 67n smaller, the distance between the contact hole h1 formed in the first diffusion region 67n and the gate electrode 26e is, for example, greater than that of the contact hole h2 formed in the second diffusion region 68an The distance from the gate electrode 26e is small. That is, when viewed from the direction perpendicular to the semiconductor substrate 60, the distance between the connection portion of the contact plug cp1 and the first diffusion area 67n and the gate electrode 26e is smaller than the connection between the contact plug cp2 and the second diffusion area 68an. Part, the distance from the gate electrode 26e is small. As described above, the first diffusion region 67n has a low impurity concentration and therefore has a higher resistance value than the second diffusion region 68an. Therefore, by reducing the distance between the contact hole h1 and the gate electrode 26e, the current path in the first diffusion region 67n can be shortened, thereby reducing the resistance value in the first diffusion region 67n. Incidentally, the same applies to the other n-type impurity regions 68bn and 68dn, and the distance between the contact hole h1 formed in the first diffusion region 67n and the gate electrode 26e may be greater than that formed in the n-type impurity regions 68bn and 68dn. The distances between the contact holes h3 and h4 and the gate electrodes 22e and 24e are small. That is, when viewed from the direction perpendicular to the semiconductor substrate 60, the distance between the contact plug cp1 and the first diffusion area 67n and the distance from the gate electrode 26e may be smaller than that between the contact plug cp3 and the n-type impurity area. The connecting portion of 68bn has a small distance from the gate electrode 22e. In addition, when viewed from the direction perpendicular to the semiconductor substrate 60, the distance between the contact plug cp1 and the first diffusion region 67n, and the distance from the gate electrode 26e, may be greater than that between the contact plug cp4 and the n-type impurity region 68dn The distance between the connecting portion and the gate electrode 24e is small.

(Modification 1) FIG. 5 is a diagram showing a circuit configuration of an imaging device 100B according to a modification 1 of the present embodiment. The main difference between the pixel 10B shown in FIG. 5 and the pixel 10A shown in FIG. 2 is that the anti-burn transistor 28 is formed on the semiconductor substrate 60 . Hereinafter, the difference from the embodiment will be mainly described, and the common point will be omitted in detail.

As shown in FIG. 5 , the charge accumulation node ND is electrically connected to the drain electrode of the reset transistor 26 , the gate electrode of the amplifier transistor 22 , the lower electrode of the photoelectric conversion portion 12 , and the source electrode and the gate electrode of the anti-burning transistor 28 . connect. Here, the drain of the reset transistor 26 is the first diffusion region 67n which is the charge accumulation region. The source of the anti-burn transistor 28 is connected to the VDD wiring or the power line 41 dedicated to the anti-burn transistor 28 . Here, if too much light enters the photoelectric conversion film 12b, the potential of the first diffusion region 67n may exceed VDD. By setting the threshold voltage of the anti-burnout transistor 28 to be turned on when the potential of the first diffusion region 67n is equal to VDD, excess electric charges can be drained from the first diffusion region 67n toward the power supply line 41 . As a result, failures such as burnout can be prevented.

FIG. 6 is a plan view showing the layout in the pixel 10B of Modification 1 of the present embodiment. As shown in FIG. 6 , the pixel 10B of this modification further has a third transistor (here, the burn-out transistor 28 ) different from the first transistor (here, the reset transistor 26 ). The anti-burnout transistor 28 includes a gate electrode 28e, a source field and a drain field. Here, the first diffusion region 67n functions as the drain region of the burn-in prevention transistor 28 . Incidentally, the first diffusion region 67n also functions as the drain region of the reset transistor 26 . In this way, in the above-mentioned two transistors, the first diffusion region 67n is shared as a drain region. The n-type impurity region 68en functions as a source region of the anti-burnout transistor 28 .

Here, the concentration of the n-type impurity in the first diffusion region 67n may be lower than the concentration of the n-type impurity in the n-type impurity region 68en. Accordingly, the concentration of the n-type impurities in the first diffusion region 67n is smaller than the concentration of the n-type impurities in the other n-type impurity regions 68bn to 68ec in the pixel 10B. As a result, since the bonding concentration between the first diffusion region 67n and the semiconductor substrate 60 is small, the leakage current can be reduced.

FIG. 7 is a schematic cross-sectional view of a device structure of a pixel of the present modification. As shown in FIG. 7 , the gate electrode 28 e of the anti-burnout transistor 28 is formed on the semiconductor substrate 60 via the gate insulating film 70 . The n-type impurity region 68en is formed on the surface of the semiconductor substrate 60 .

When too much light is incident on the photoelectric conversion film 12b, the potential of the first diffusion region 67n rises to the same extent as the bias voltage applied to the transparent electrode 12c. If such an overvoltage is applied to the first diffusion region 67n, the first diffusion region 67n may be damaged, or the gate insulating film 70 of the amplifier transistor 22 may be damaged. As a result, failures such as burnout occur.

On the other hand, according to this modification, dark current can be suppressed, and failure of each transistor due to overvoltage can be prevented even in the case of excessive light incidence.

(Modification 2) FIG. 8 is a plan view showing the layout in the pixel 10C of the imaging device 100C according to the modification 2 of the present embodiment. The present modification is different from the pixel 10A in that the first diffusion area (FD) 67 n is circular when viewed from the direction perpendicular to the semiconductor substrate 60 . Hereinafter, the difference from the embodiment will be mainly described, and the common point will be omitted in detail.

In this modification, as described above, when viewed from the direction perpendicular to the semiconductor substrate 60, the first diffusion region (FD) 67n is circular. As a result, the area of the first diffusion region 67n on the surface of the semiconductor substrate 60 is smaller than when the first diffusion region 67n is formed into a rectangular shape. Therefore, on the surface of the semiconductor substrate 60, the area of the interface depletion layer formed at the junction between the first diffusion region 67n and the semiconductor substrate 60 is small. Thereby, the leakage current in the junction can be reduced.

Incidentally, although this modification does not have the burn-in prevention transistor 28 like the imaging device 100A of the embodiment, the burn-in prevention transistor 28 may be provided as in the imaging device 100B of the modification 1. Thereby, even if excessive light is incident on the photoelectric conversion portion 12, failure of each transistor due to overvoltage can be prevented. (Modification 3) FIG. 9 is a diagram showing a circuit configuration of a pixel 10D of an imaging device 100D according to a modification 3 of the present embodiment. FIG. 10 is a plan view showing the layout in the pixel 10D of the present modification. Although the imaging device exemplified in the above embodiment and modification has a photoelectric conversion portion using a photoelectric conversion film, the imaging device exemplified in this modification uses a photodiode as the photoelectric conversion portion. As shown in FIGS. 9 and 10 , the pixel 10D of this modification has the photodiode 13 and the transfer transistor 27 . The photodiode 13 has an n-type impurity region 68fn and a pinning layer (not shown) positioned over the n-type impurity region 68fn. The pinned layer is the p-type impurity domain. The photodiode 13 photoelectrically converts the light received during the exposure time to generate electric charges. After the predetermined exposure time is over, a transmission signal for turning on the transmission transistor 27 is applied to the gate of the transmission transistor 27 through the transmission signal line 37 . Thereby, the transfer transistor 27 is turned on, and the charges generated by the photodiode 13 are transferred to the charge storage node ND. The amplifier transistor 22 outputs a signal corresponding to the charge transferred to the charge accumulation node ND to the vertical signal line 35 (not shown). The signal output to the vertical signal line 35 is supplied to an AD conversion unit (not shown) for AD conversion. As shown in FIG. 10 , the transfer transistor 27 includes a first diffusion region 67n and an n-type impurity region 68fn as a source and a drain. In addition, the transfer transistor 27 includes a gate electrode 27e. The transfer transistor 27 is shared with the reset transistor 26 by using the first diffusion region 67n as one of a source and a drain. In addition, as shown in FIG. 9 , the charge accumulation node ND is electrically connected to the drain of the reset transistor 26 , the gate of the amplifier transistor 22 , and the source of the transfer transistor 27 . Here, the drain of the reset transistor 26 in FIG. 10 is the first diffusion area 67n which is the charge accumulation area. In this modification, the pixel 10D includes the first transistor (here, the reset transistor 26 ), as in the above-described embodiment and modification. The first transistor is located in the semiconductor substrate, contains n-type impurities, and includes the first diffusion region 67n where the photocharge converted by the photodiode 13 is stored as one of the source and the drain, The second diffusion region 68an, which is an n-type impurity region including n-type impurities, is included as the other of the source and the drain. At this time, the concentration of the n-type impurity in the first diffusion region 67n is smaller than the concentration of the n-type impurity in the second diffusion region 68an. Thereby, since the junction concentration at the junction between the first diffusion region 67n and the semiconductor substrate is small, the leakage current in the first diffusion region 67n is reduced. Furthermore, the pixel 10D has a second transistor (here, the amplifier transistor 22 ) that is different from the reset transistor 26 . The second transistor is located in the semiconductor substrate 60 and contains a third diffusion region of n-type impurities. (hereinafter referred to as the other n-type impurity regions 68bn and 68cn.) It is included as a source or a drain. At this time, the concentration of the n-type impurity in the first diffusion region 67n may be lower than the concentration of the n-type impurity in the other n-type impurity regions 68bn and 68cn. In this case, the concentration of the n-type impurity in the first diffusion region 67n may be at least 1/10 of the concentration of the n-type impurity in the second diffusion region 68an and the other n-type impurity regions 68bn and 68cn, or may be smaller than 1 /15 small. As a result, since the bonding concentration at the bonding portion between the first diffusion region 67n and the semiconductor substrate 60 is small, the electric field strength at the bonding portion can be reduced. Therefore, the leakage current from the first diffusion region 67n, which is itself a charge accumulation region, or to the first diffusion region 67n is reduced. In addition, the imaging device 100D according to the present modification may be such that the semiconductor substrate 60 includes p-type impurities, the concentration of n-type impurities included in the first diffusion region 67n, and the concentration of the n-type impurity included in the first diffusion region 67n in the semiconductor substrate 60 may be adjacent to the first diffusion region 67n. The concentration of the p-type impurity contained in this part is 1×10 ¹⁶ atoms/cm ³ or more and 5×10 ¹⁶ atoms/cm ³ or less. Thereby, the bonding concentration between the first diffusion region 67n and the semiconductor substrate 60 is small, and the increase of the electric field intensity at the bonding portion can be suppressed. Therefore, the leakage current at the junction can be reduced. In addition, if the area of the depletion layer region (hereinafter referred to as the interface depletion layer) formed at the junction on the surface of the semiconductor substrate 60 increases, the leakage current tends to increase. Therefore, it is preferable to minimize the area of the interface depletion layer exposed on the surface of the semiconductor substrate 60 . In order to make the area of the interface depletion layer small, the area of the first diffusion region 67n may be smaller than that of the second diffusion region 68an when viewed from the direction perpendicular to the semiconductor substrate 60 . For example, when viewed from the direction perpendicular to the semiconductor substrate 60, the area of the first diffusion area 67n may be less than 1/2 of the area of the second diffusion area 68an. In addition, in this case, the width in the channel width direction of the first diffusion region 67n may be equal to or less than 1/2 of the width in the channel width direction of the second diffusion region 68an. Incidentally, the first diffusion area 67n and the second diffusion area 68an may have the same size as one of the width in the channel width direction and the length in the channel length direction. In addition, the same applies to the other n-type impurity regions 68bn and 68cn in the pixel 10D, and the area of the first diffusion region 67n when viewed from the direction perpendicular to the semiconductor substrate 60 may be larger than that of the other n-type impurity regions 68bn and 68cn. formed in a small area. In addition, the areas of the first diffusion region 67n and the second diffusion region 68an may also be the same as those of the reset transistor 26 in the first diffusion region 67n and the second diffusion region 68an when viewed from a direction perpendicular to the semiconductor substrate. The area of the portion where the gate electrodes 26e overlap. Similarly, the areas of the other n-type impurity regions 68bn and 68cn may also be those of the other n-type impurity regions 68bn and 68cn when viewed from the direction perpendicular to the semiconductor substrate 60 , which do not correspond to the gates of the amplifier transistor 22 . The area of the portion where the electrodes 22e overlap. The portions overlapping the gate electrodes 22e and 26e of the transistors when viewed from a direction perpendicular to the semiconductor substrate 60 are more difficult to sustain damage during manufacture than the portions not overlapping the gate electrodes 22e and 26e. As for the damage during manufacture, for example, it is caused by the plasma treatment used in the dry etching process and the ashing treatment when the photoresist is peeled off. As a result, leakage current is less likely to occur in the portions overlapping with the gate electrodes 22e and 26e. Therefore, in order to reduce the area of the interface depletion layer, the first diffusion region 67n and the other n-type impurity regions 68bn and 68cn may only consider the influence of the area of the portion that does not overlap with the gate electrode. In addition, by making the area of the first diffusion region 67n smaller, the distance between the contact hole h1 formed in the first diffusion region 67n and the gate electrode 26e is, for example, greater than that of the contact hole h2 formed in the second diffusion region 68an The distance from the gate electrode 26e is small. As described above, the first diffusion region 67n has a low impurity concentration and therefore has a higher resistance value than the second diffusion region 68an. Therefore, since the distance between the contact hole h1 and the gate electrode 26e is small, the current path in the first diffusion region 67n can be shortened, thereby reducing the resistance value in the first diffusion region 67n. Incidentally, the same applies to the other n-type impurity regions 68bn and 68cn, and the distance between the contact hole h1 formed in the first diffusion region 67n and the gate electrode 26e may be greater than that formed in the n-type impurity regions 68bn and 68cn. The distances between the contact holes h3 and h9 and the gate electrode 22e are small.

Although the imaging device related to the present disclosure has been described above based on the embodiments and modifications, the present disclosure is not limited to these embodiments and modifications. As long as it does not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art are also included in the scope of the present disclosure by adding various modifications to the embodiments and modifications, and other forms constructed by combining some of the constituent elements of the embodiments and modifications. .

In addition, according to the embodiment and the modification of the present disclosure, the influence of the leakage current can be reduced, so that a photographing apparatus capable of photographing with high image quality can be provided. Incidentally, the amplifying transistor 22 , the address transistor 24 , the reset transistor 26 , and the anti-burning transistor 28 may be N-channel MOS or P-channel MOS, respectively. When each transistor is a P-channel MOS, the impurity of the first conductivity type is a p-type impurity, and the impurity of the second conductivity type is an n-type impurity. It is not necessary to unify all the transistors as either N-channel MOS or P-channel MOS. When the transistors in the pixel are N-channel MOS respectively and use electrons as signal charges, the configurations of the source and drain electrodes of the transistors can also be interchanged. Industrial availability

According to the present disclosure, it is possible to provide a photographing apparatus capable of suppressing the influence of dark current and photographing with high image quality. The photographing device of the present disclosure is useful for, for example, an image sensor, a digital camera, and the like. The imaging device of the present disclosure can be used for a medical camera, a robot camera, a surveillance camera, a camera mounted on a vehicle, and the like.

10A, 10B, 10C, 10D‧‧‧Pixel 12‧‧‧Photoelectric conversion part 12a‧‧‧Pixel electrode 12b‧‧‧Photoelectric conversion layer 12c‧‧‧Transparent electrode 13‧‧‧Photodiode 14‧‧‧Signal Detection circuit 16‧‧‧Feedback circuit 22‧‧‧Amplifying transistors 22e, 24e, 26e, 27e, 28e‧‧‧Gate electrode 24‧‧‧Address transistor 26‧‧‧Reset transistor 27‧‧‧ Transmission Transistor 28‧‧‧Anti-burning Transistor 32‧‧‧Power Wiring 34‧‧‧Address Signal Line 35‧‧‧Vertical Signal Line 36‧‧‧Reset Signal Line 37‧‧‧Transmission Signal Line 39‧‧ ‧Accumulation control line 40‧‧‧Peripheral circuit 41‧‧‧Power supply line 42‧‧‧Load circuit 44‧‧‧Column signal processing circuit 46‧‧‧Vertical scanning circuit 48‧‧‧Horizontal signal reading circuit 49‧‧‧ Horizontal common signal line 50‧‧‧Reverse amplifier 53‧‧‧Feedback line 60‧‧‧Semiconductor substrate 61‧‧‧Support substrate 61p, 63p, 65p‧‧‧p type semiconductor layer 62n‧‧‧n type semiconductor layer 64‧‧‧p-type domain 66p‧‧‧p-type impurity domain 67a•••First domain 67b••• Second domain 67n•••First diffusion domain 68an••• Second diffusion domain 68bn, 68cn, 68dn , 68en, 68fn‧‧‧N-type impurity area 69‧‧‧Component isolation area 70, 71, 72, 90a, 90b, 90c, 90d‧‧‧Insulating layer 80‧‧‧Wiring structure 80a, 80b, 80c, 80d‧ ‧‧Wiring layer 90‧‧‧Interlayer insulating layers 100A, 100B, 100C, 100D‧‧‧Camera device ND‧‧‧Charge accumulation node R1‧‧‧Photography area R2‧‧‧Peripheral area cp1, cp2, cp3, cp4, cp5, cp6, cp7, cp8‧‧‧contact plug h1, h2, h3, h4, h5, h6, h7, h8, h9‧‧‧contact hole pa1, pa2, pb, pc, pd‧‧‧plug

Fig. 1 . . . a configuration diagram of an imaging device according to an embodiment. Fig. 2 . . . is a diagram showing the circuit configuration of the imaging device according to the embodiment. Figure 3 . . . A plan view showing the layout within the pixel of the embodiment. 4 : is a schematic cross-sectional view of the device structure of the pixel of the embodiment. Fig. 5 . . . is a diagram showing a circuit configuration of an imaging device according to Modification 1 of the embodiment. Fig. 6 . . . is a plan view showing a layout in a pixel of Modification 1 of the embodiment. 7 : is a schematic cross-sectional view of a device structure of a pixel according to Modification 1 of the embodiment. Fig. 8 . . . is a plan view showing a layout in a pixel of Modification 2 of the embodiment. Fig. 9 . . . is a diagram showing a circuit configuration of a pixel according to Modification 3 of the embodiment. Fig. 10 . . . is a plan view showing a layout in a pixel of Modification 3 of the embodiment.

10A‧‧‧pixels

12‧‧‧Photoelectric Conversion Department

12a‧‧‧Pixel electrode

12b‧‧‧Photoelectric conversion layer

12c‧‧‧Transparent electrode

22‧‧‧Amplifier transistor

22e, 24e, 26e‧‧‧Gate electrode

24‧‧‧Address Transistor

26‧‧‧Reset Transistor

60‧‧‧Semiconductor substrate

61‧‧‧Support substrate

61p, 63p, 65p‧‧‧p type semiconductor layer

62n‧‧‧n-type semiconductor layer

64‧‧‧p-type field

66p‧‧‧p-type impurity field

67a‧‧‧Field 1

67b‧‧‧Second field

67n‧‧‧First Diffusion Field

68an‧‧‧Second Diffusion Field

68bn, 68cn, 68dn‧‧‧n-type impurities

69‧‧‧Component separation

70, 71, 72, 90a, 90b, 90c, 90d‧‧‧Insulation layer

80‧‧‧Wiring structure

80a, 80b, 80c, 80d‧‧‧Wiring Layer

90‧‧‧Interlayer insulating layer

cp1, cp2, cp3, cp4, cp5, cp6, cp7‧‧‧contact plug

h1, h2, h3, h4, h5, h6, h7‧‧‧contact holes

pa1, pa2, pb, pc, pd‧‧‧plug

Claims (10)

An imaging device comprising a semiconductor substrate including a first diffusion region containing an impurity of a first conductivity type and a second diffusion region including an impurity of the first conductivity type, and a plurality of pixels, each of the plurality of pixels includes a a photoelectric conversion part that converts light into electric charges; and a first transistor including a source electrode, a drain electrode and a gate electrode, and the first diffusion area is included as one of the source electrode and the drain electrode, and the The second diffusion region is included as the other of the source electrode and the drain electrode, wherein the first diffusion region accumulates at least a part of the electric charge, and the first diffusion region of the impurity of the first conductivity type is included in the first diffusion region. The concentration is smaller than the concentration of the impurity of the first conductivity type in the second diffusion region. When viewed from the direction perpendicular to the semiconductor substrate, the area of the first diffusion region is smaller than the area of the second diffusion region. . The imaging device of claim 1, wherein the semiconductor substrate further includes a third diffusion domain containing impurities of the first conductivity type, and each of the plurality of pixels includes a second transistor, and the second transistor treats the third diffusion domain as an impurity. The concentration of the impurity of the first conductivity type included in one of the source electrode and the drain electrode in the first diffusion region is smaller than the concentration of the impurity of the first conductivity type in the third diffusion region. The imaging device of claim 1, wherein each of the plurality of pixels includes a third transistor, and the third transistor includes the first diffusion region as one of a source and a drain. The imaging device of claim 1, wherein the area of the first diffusion region is the area of the portion of the first diffusion region that does not overlap with the gate electrode when viewed from a direction perpendicular to the semiconductor substrate, and the second diffusion region The area of the diffusion area is an area of a portion of the second diffusion area that does not overlap with the gate electrode when viewed from a direction perpendicular to the semiconductor substrate. The imaging device of claim 1, wherein each of the plurality of pixels comprises: a first plug connected to the first part of the first diffusion field; and a second plug connected to the second part of the second diffusion field , when viewed from a direction perpendicular to the semiconductor substrate, the distance between the first portion and the gate electrode is smaller than the distance between the second portion and the gate electrode. The imaging device of claim 1, wherein the semiconductor substrate includes a fourth diffusion domain, the fourth diffusion domain includes an impurity of a second conductivity type different from the first conductivity type, and each of the plurality of pixels includes an impurity other than the first transistor For other transistors, the above-mentioned fourth diffusion area is included as a separate area for separating the above-mentioned first transistor from the above-mentioned other transistors, and the above-mentioned fourth diffusion area is on the surface of the above-mentioned semiconductor substrate and is not related to the above-mentioned first Diffusion field contacts. The imaging device of claim 1, wherein the semiconductor substrate contains impurities of a second conductivity type different from the first conductivity type, and the concentration of the impurities of the first conductivity type included in the first diffusion ^{region is 1×10 16} atoms/ cm ³ or ^{more, 5 × 10 16 atoms / cm} 3 or less, the concentration of the second conductivity type of the impurity abutment of the semiconductor substrate and the first diffusion field included in the portion of a 1 × 10 ¹⁶ atoms / cm ³ or more, 5 ×10 ¹⁶ atoms/cm ³ or less. The imaging device of claim 1, wherein when viewed from a direction perpendicular to the semiconductor substrate, the first diffusion area is circular. The imaging device of claim 1, wherein the semiconductor substrate includes a semiconductor layer, the semiconductor layer includes an impurity of a second conductivity type different from the first conductivity type, and the bottom surface of the first diffusion region is in contact with the semiconductor layer. An imaging device comprising a semiconductor substrate and a plurality of pixels, the semiconductor substrate comprising a first diffusion region containing impurities of a first conductivity type, and a second diffusion region containing impurities of the first conductivity type, the plurality of pixels each comprising: The photoelectric conversion part converts light into electric charge; the first transistor includes a source electrode, a drain electrode and a gate electrode, and the first diffusion area is included as one of the source electrode and the drain electrode, and the The second diffusion area is included as the other of the source electrode and the drain electrode, wherein the first diffusion area stores at least a part of the electric charge; the first plug is connected to the first part of the first diffusion area ; and a second plug, connected to the second portion of the second diffusion region, in which the concentration of impurities of the first conductivity type in the first diffusion region is greater than The concentration of the impurity of the first conductivity type in the second diffusion region is small, and when viewed from a direction perpendicular to the semiconductor substrate, the distance between the first portion and the gate electrode is smaller than that between the second portion and the gate electrode. The distance between electrodes should be small.

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