CN109300924A - camera - Google Patents

Abstract

An object is to provide an imaging device capable of suppressing dark current. The imaging device includes: a semiconductor substrate including a first diffusion region containing an impurity of a first conductivity type and a second diffusion region containing an impurity of the first conductivity type; and a plurality of pixels; each of the plurality of pixels includes a photoelectric conversion portion, converting light into electric charge; and a first transistor including a source electrode, a drain electrode and a gate electrode, including the first diffusion region storing at least a part of the electric charge as one of the source electrode and the drain electrode, including the second diffusion region The diffusion region serves as the other of the source electrode and the drain electrode; the concentration of the impurity of the first conductivity type in the first diffusion region is smaller than the concentration of the impurity of the first conductivity type in the second diffusion region; The area of the first diffusion region is smaller than the area of the second diffusion region when viewed in a direction perpendicular to the semiconductor substrate.

Description

Photographic device

Technical field

This disclosure relates to photographic device.

Background technique

CCD (Charge Coupled Device: charge-coupled device) image is widely used in digital camera etc. Sensor and CMOS (Complementary Metal Oxide Semiconductor: complementary metal oxide semiconductor) figure As sensor.As is known, these imaging sensors have the photodiode formed on a semiconductor substrate.

On the other hand, the structure by the photoelectric conversion department configuration with photoelectric conversion layer in the top of semiconductor substrate is proposed Make (such as patent document 1,2).The photographic device having configuration which is sometimes referred to as the photographic device of laminated type.It is being laminated In the photographic device of type, charge accumulation region (referred to as " FD: floating diffusion ") is arrived by accumulation by the charge that light-to-current inversion generates In.CCD circuit of the signal corresponding with the quantity of electric charge being accumulated in charge accumulation region on semiconductor substrate or Cmos circuit is read.

Patent document 1: International Publication No. 2014/002330

Patent document 2: International Publication No. 2012/147302

Summary of the invention

In the photographic device of laminated type, sometimes because of leakage from charge accumulation region or towards charge accumulation region Electric current (having the case where referred to as " dark current " below) and deteriorated in obtained image.If such electric leakage can be reduced Stream is then beneficial.

The photographic device of a technical solution in relation to the disclosure has: semiconductor substrate, including containing the miscellaneous of the 1st conductivity type 2nd diffusion zone of the 1st diffusion zone and the impurity containing the 1st conductivity type of matter；With multiple pixels；Above-mentioned multiple pixel difference Include: photoelectric conversion department, light is transformed to charge；With the 1st transistor, including source electrode, drain electrode and gate electrode, and including store At least part of above-mentioned 1st diffusion zone of the above-mentioned charge of product is including above-mentioned as above-mentioned source electrode and a side of above-mentioned drain electrode 2nd diffusion zone is as above-mentioned source electrode and another party of above-mentioned drain electrode；The impurity of the 1st conductivity type in above-mentioned 1st diffusion zone Concentration it is lower than the concentration of the impurity of the 1st conductivity type in above-mentioned 2nd diffusion zone；When from vertical with above-mentioned semiconductor substrate When direction is observed, the area of above-mentioned 2nd diffusion zone of area ratio of above-mentioned 1st diffusion zone is small.

Inclusive or specific technical solution can be realized by element, equipment, module, system or method.In addition, inclusive Or specific technical solution can be realized by the arbitrary combination of element, equipment, module, system and method.

The additional effect and advantage of disclosed embodiment can become apparent according to specification and attached drawing.Effect and/ Or advantage is provided respectively as the various embodiments disclosed in specification and attached drawing or feature, is not intended to obtain it 1 or more and need whole.

According to the disclosure, it is capable of providing a kind of photographic device for being able to suppress dark current.

Detailed description of the invention

Fig. 1 is the structure chart of the photographic device in relation to embodiment.

Fig. 2 is the figure for indicating the circuit structure of the photographic device in relation to embodiment.

Fig. 3 is the plan view of the layout in the pixel for indicate embodiment.

Fig. 4 is the summary sectional view of the equipment construction of the pixel of embodiment.

Fig. 5 is the figure for indicating the circuit structure of photographic device of the variation 1 in relation to embodiment.

Fig. 6 is the plan view of the layout in the pixel for the variation 1 for indicating embodiment.

Fig. 7 is the summary sectional view of the equipment construction of the pixel of the variation 1 of embodiment.

Fig. 8 is the plan view of the layout in the pixel for the variation 2 for indicating embodiment.

Fig. 9 is the figure for indicating the circuit structure of the pixel of variation 3 of embodiment.

Figure 10 is the plan view of the layout in the pixel for the variation 3 for indicating embodiment.

Specific embodiment

The summary of one technical solution of the disclosure is following such.

[project 1]

A kind of photographic device, has: semiconductor substrate, the 1st diffusion zone including the impurity containing the 1st conductivity type and contains There is the 2nd diffusion zone of the impurity of the 1st conductivity type；With multiple pixels；Above-mentioned multiple pixels respectively include: photoelectric conversion department, it will Light is transformed to charge；With the 1st transistor, including source electrode, drain electrode and gate electrode, and at least one including accumulating above-mentioned charge Partial above-mentioned 1st diffusion zone is as above-mentioned source electrode and a side of above-mentioned drain electrode, including above-mentioned 2nd diffusion zone is as above-mentioned Another party of source electrode and above-mentioned drain electrode；The concentration of the impurity of the 1st conductivity type in above-mentioned 1st diffusion zone is than above-mentioned 2nd diffusion The concentration of the impurity of the 1st conductivity type in region is low；When from the direction vertical with above-mentioned semiconductor substrate, the above-mentioned 1st The area of above-mentioned 2nd diffusion zone of the area ratio of diffusion zone is small.

It is led in this way, the impurity concentration of the 1st conductivity type contained in the 1st diffusion zone contains the 1st than the others in pixel The impurity concentration of the diffusion zone of the impurity of electric type is low.Engagement at the joint portion of 1st diffusion zone and semiconductor substrate as a result, Concentration becomes smaller, so the leakage current in the 1st diffusion zone is reduced.

In turn, the depletion layer formed at the joint portion of the 1st diffusion zone and semiconductor substrate can be made, particularly partly led The area of the depletion layer on the surface of structure base board becomes smaller.Since crystal defect becomes larger near the surface of semiconductor substrate, so if Depletion layer is formed herein, then leakage current becomes larger.Thus, the area of the depletion layer on surface by making semiconductor substrate becomes It is small, leakage current can be reduced.

[project 2]

Photographic device as described in project 1, above-mentioned semiconductor substrate further include the 3rd expansion of the impurity containing the 1st conductivity type Dissipate region；Above-mentioned multiple pixels are separately included including above-mentioned 3rd diffusion zone as source electrode and the 2nd crystal of a side of drain electrode Pipe；The concentration of the impurity of the 1st conductivity type in above-mentioned 1st diffusion zone is more miscellaneous than the 1st conductivity type in above-mentioned 3rd diffusion zone The concentration of matter is low.

[project 3]

Photographic device as described in project 1 or 2, above-mentioned multiple pixels are separately included including above-mentioned 1st diffusion zone conduct The 3rd transistor of one side of source electrode and drain electrode.

[project 4]

Photographic device as described in project 1, the above-mentioned area of above-mentioned 1st diffusion zone, be when from it is above-mentioned semiconductor-based The area of not with above-mentioned gate electrode Chong Die part of plate vertical direction when observing in above-mentioned 1st diffusion zone；Above-mentioned 2nd The above-mentioned area of diffusion zone is when from from the direction vertical with above-mentioned semiconductor substrate in above-mentioned 2nd diffusion zone The not area of the part Chong Die with above-mentioned gate electrode.

[project 5]

Photographic device as described in any one of project 1~4, above-mentioned multiple pixels respectively include: the 1st plug is connected to The part 1 of above-mentioned 1st diffusion zone；With the 2nd plug, it is connected to the part 2 of above-mentioned 2nd diffusion zone；When from it is above-mentioned Semiconductor substrate it is vertical direction observation when, above-mentioned part 1 at a distance from above-mentioned gate electrode than above-mentioned part 2 with it is above-mentioned The distance of gate electrode is small.

It shortens as a result, from the distance of the gate electrode of the 1st plug to the 1st transistor of the 1st diffusion zone, so can subtract The rising of the resistance value of small 1st diffusion zone.

[project 6]

Photographic device as described in any one of project 1~5, above-mentioned semiconductor substrate include containing with the 1st conductivity type not 4th diffusion zone of the impurity of the 2nd same conductivity type；Above-mentioned multiple pixels further include respectively it other than above-mentioned 1st transistor His transistor, and including above-mentioned 4th diffusion zone as by the separation of above-mentioned 1st transistor and other above-mentioned transistors separateds Region；Above-mentioned 4th diffusion zone does not contact in the surface of above-mentioned semiconductor substrate with above-mentioned 1st diffusion zone.

In this way, due in the surface of semiconductor substrate for being easiest to occur leakage current, the impurity containing the 1st conductivity type 1st diffusion zone is not contacted with the separated region of the impurity containing the 2nd conductivity type different with the 1st conductivity type, so can subtract Leakage current at the joint portion of small semiconductor substrate surface.

[project 7]

Photographic device as described in any one of project 1~6, above-mentioned semiconductor substrate contain different from the 1st conductivity type The impurity of 2nd conductivity type；The concentration of the impurity of the 1st conductivity type contained in above-mentioned 1st diffusion zone is 1 × 10¹⁶atoms/cm³ Above and 5 × 10¹⁶atoms/cm³Below；Contain in the part adjacent with above-mentioned 1st diffusion zone in above-mentioned semiconductor substrate The concentration of impurity of the 2nd conductivity type be 1 × 10¹⁶atoms/cm³Above and 5 × 10¹⁶atoms/cm³Below.

In this way, the concentration of the impurity by making the 1st conductivity type and the 2nd conductivity type becomes smaller, be able to suppress the 1st diffusion zone with The rising of electric field strength at the joint portion of semiconductor substrate can reduce leakage current.

[project 8]

Photographic device as described in any one of project 1~7, when from the direction vertical with above-mentioned semiconductor substrate When, above-mentioned 1st diffusion zone is round.

The area of the 1st diffusion zone in the surface of semiconductor substrate becomes smaller as a result, so can make in semiconductor substrate Surface joint portion at the area of depletion layer that is formed become smaller.Thereby, it is possible to reduce leakage current.

[project 9]

A kind of photographic device, has: semiconductor substrate, the 1st diffusion zone including the impurity containing the 1st conductivity type and contains There is the 2nd diffusion zone of the impurity of the 1st conductivity type；With multiple pixels；Above-mentioned multiple pixels respectively include: photoelectric conversion department, it will Light is transformed to charge；1st transistor, including source electrode, drain electrode and gate electrode, and at least one including accumulating above-mentioned charge Above-mentioned 1st diffusion zone divided is as above-mentioned source electrode and a side of above-mentioned drain electrode, including above-mentioned 2nd diffusion zone is as above-mentioned source Another party of pole and above-mentioned drain electrode；1st plug is connected to the part 1 of above-mentioned 1st diffusion zone；With the 2nd plug, it is connected to The part 2 of above-mentioned 2nd diffusion zone；The concentration of the impurity of the 1st conductivity type in above-mentioned 1st diffusion zone expands than the above-mentioned 2nd The concentration for dissipating the impurity of the 1st conductivity type in region is low；When from the direction vertical with above-mentioned semiconductor substrate, above-mentioned 1 part is smaller at a distance from above-mentioned gate electrode than above-mentioned part 2 at a distance from above-mentioned gate electrode.

Hereinafter, embodiment of the present disclosure is described in detail with reference to accompanying drawings.In addition, embodiments described below all indicates Inclusive or specific example.The numerical value that indicates in the following embodiments, shape, material, constituent element, constituent element Configuration and connection form, step, the sequence of step etc. are an examples, are not intended to limit the disclosure.Illustrate in the present specification Various technical solutions as long as conflicting as long as can be combined with each other.In addition, the constituent element of the following embodiments and the accompanying drawings In, there is no the constituent element recorded in the independent claims for indicating upper concept, be set as arbitrary constituent element and It is illustrated.In the various figures, substantially constituent element with the same function is indicated with common label, sometimes by duplicate theory Bright omission is simple.

In addition, the various elements indicated in figure are only the understanding for the disclosure and show schematically that size is when Appearance etc. may be different from material object.

In addition, in the present specification, if the sensitive side of photographic device is " top ", if with sensitive side opposite side be " under Side ".Similarly about " upper surface " of each component, " lower surface ", the face opposed with the sensitive side of photographic device is set as " upper table Face " will be set as " lower surface " with the face of sensitive side opposite side to being placed in.In addition, " top ", " lower section ", " upper surface " and " following table The term in face " etc. only uses for the mutual configuration between specified parts, is not intended to limit photographic device Posture when use.

(embodiment)

Fig. 1 is the structure chart of the photographic device in relation to present embodiment.As shown in Figure 1, the camera shooting in relation to present embodiment Device 100A has multiple pixel 10A and the peripheral circuit 40 being formed on semiconductor substrate 60.Each pixel 10A includes that configuration exists The photoelectric conversion department 12 of the top of semiconductor substrate 60.That is, an example as the photographic device in relation to the disclosure, to laminated type Photographic device 100A is illustrated.

In the example depicted in figure 1, pixel 10A is configured as the rectangular of m row n column.Here, m, n be 2 or more it is whole Number.Pixel 10A forms imaging area R1 for example, by being two-dimensionally arranged on semiconductor substrate 60.As described above, each picture Plain 10A includes the photoelectric conversion department 12 for the top configured in semiconductor substrate 60.Therefore, imaging area R1 is defined as semiconductor The region covered by photoelectric conversion department 12 in substrate 60.In addition, in Fig. 1, by the photoelectric conversion department 12 of each pixel 10A from making Illustrate to become easy viewpoint and be spatially separated from each other and indicate, but the photoelectric conversion department 12 of multiple pixel 10A can be mutual Not interval and configure on semiconductor substrate 60.

The quantity of pixel 10A and configuration are not limited to example illustrated.For example, the pixel for including in photographic device 100A The quantity of 10A is also possible to 1.In this embodiment, the center of each pixel 10A is located in the grid point of square lattice, but pixel 10A Configuration can not also be in this way.For example, it is also possible to be located at the side in the grid point of triangular lattice, hexagonal lattice etc. with each center Formula configures multiple pixel 10A.If pixel 10A one-dimensionally arranged, photographic device 100A also can use as row sensing Device.

In the structure illustrated by Fig. 1, peripheral circuit 40 includes vertical scanning circuit (also referred to as " line-scan circuit ") 46 And horizontal signal reading circuit (also referred to as " column scan circuit ") 48.Vertical scanning circuit 46 has and corresponds to multiple pixels Each row of 10A and the connection of address signal line 34 being arranged.Horizontal signal reading circuit 48 has and corresponds to multiple pixel 10A Each vertical signal line 35 for arranging and being arranged connection.As showed schematically in Fig. 1, these circuits are configured in imaging region In the neighboring area R2 in the outside of domain R1.Peripheral circuit 40 can also further include signal processing circuit, output circuit, control circuit And the power supply etc. of defined voltage is supplied to each pixel 10A.A part of peripheral circuit 40 can also be configured in and be formed with On the different other substrates of the semiconductor substrate 60 of pixel 10A.

Fig. 2 is the figure for indicating the circuit structure of the photographic device 100A in relation to embodiment.In Fig. 2, in order to avoid figure Show and complicate, illustrates 4 pixel 10A in multiple pixel 10A shown in FIG. 1, with the column arrangement of 2 rows 2.

The photoelectric conversion department 12 of each pixel 10A by light incidence and generate just and negative charge (typically hole- Electronics to).The photoelectric conversion department 12 of each pixel 10A has the connection with accumulation control line 39, in the movement of photographic device 100A When, defined voltage is applied to accumulation control line 39.It, can will be by by the way that defined voltage to be applied on accumulation control line 39 The charge for the side just and in negative charge that light-to-current inversion generates selectively is accumulated in charge accumulation region.Hereinafter, example Show using the positive charge just and in negative charge generated by light-to-current inversion as the case where signal charge.

Each pixel 10A includes the signal deteching circuit 14 being connected electrically on photoelectric conversion department 12.The structure illustrated by Fig. 2 In, signal deteching circuit 14 includes amplifying transistor 22 (also referred to as " reading transistor ") and reset transistor 26.In this embodiment, Signal deteching circuit 14 further includes address transistor (also referred to as " row selecting transistor ") 24.As below referring to attached drawing in detail Bright such, amplifying transistor 22, reset transistor 26 and the address transistor 24 of signal deteching circuit 14 are typically supporting The field effect transistor (FET:Field Effect Transistor) formed on the semiconductor substrate 60 of photoelectric conversion department 12. Hereinafter, illustrating to use N-channel MOS (Metal Oxide Semiconductor) as transistor as long as no special negative The example of transistor.In addition, which of 2 diffusion layers of FET correspond to source electrode and drain electrode, by the polarity of FET and the time point Current potential height determine.Therefore, which is that source electrode and drain electrode may be changed according to the action state of FET.

As showing schematically in Fig. 2, the grid of amplifying transistor 22 is connected electrically on photoelectric conversion department 12.By The charge that photoelectric conversion department 12 generates is accumulated to the charge accumulation being connected between photoelectric conversion department 12 and amplifying transistor 22 In charge accumulation region on node (also referred to as " floating diffusion nodes ") ND.In addition, so-called charge accumulation node ND, refer to by The wiring of the lower electrode electrical connection in charge accumulation region, the grid of amplifying transistor 22 and photoelectric conversion department 12 and charge accumulation Region.

The drain electrode of amplifying transistor 22 is connected in the movement of photographic device 100A to as defined in each pixel 10A supply On the power-supply wiring (also referred to as source follower power source) 32 of supply voltage VDD (such as 3.3V or so).In other words, amplify crystal Pipe 22 exports signal voltage corresponding with the amount of signal charge generated by photoelectric conversion department 12.The source electrode quilt of amplifying transistor 22 It is connected in the drain electrode of address transistor 24.

Vertical signal line 35 is connected on the source electrode of address transistor 24.As illustrated, vertical signal line 35 is pressed According to each column setting of multiple pixel 10A, on each of vertical signal line 35, it is connected to load circuit 42 and column signal Processing circuit (also referred to as " row signal accumulates circuit ") 44.Load circuit 42 and amplifying transistor 22 are formed together source follower Circuit.

Address signal line 34 is connected on the grid of address transistor 24.Address signal line 34 is by according to multiple pixels Each row of 10A is arranged.Address signal line 34 is connected on vertical scanning circuit 46, and vertical scanning circuit 46 will control address The row selection signal of transistor 24 unlatched and closed is applied on address signal line 34.The row of object is read as a result, by along vertical Histogram is scanned to (column direction), and selection reads the row of object.Vertical scanning circuit 46 is by controlling ground via address signal line 34 Location transistor 24 unlatches and closes, can be by the output of the amplifying transistor 22 of selected pixel 10A to corresponding vertical Signal wire 35 is read.The configuration of address transistor 24 is not limited to example shown in Fig. 2, is also possible in amplifying transistor 22 Drain electrode and power-supply wiring 32 between.

It is output to signal voltage in vertical signal line 35, from pixel 10A via address transistor 24, by right It should be in vertical signal line 35 and according to corresponding in multiple column signal processing circuits 44 of each column of multiple pixel 10A setting Column signal processing circuit 44 inputs.Column signal processing circuit 44 and load circuit 42 can be one of above-mentioned peripheral circuit 40 Point.

Column signal processing circuit 44 is carried out using correlated-double-sampling as the processing of the noise suppression signal of representative and analog to digital Convert (AD transformation) etc..Column signal processing circuit 44 is connected on horizontal signal reading circuit 48.Horizontal signal reading circuit 48 sequential read out signal from multiple column signal processing circuits 44 to the shared signal wire 49 of level.

In the structure illustrated by Fig. 2, signal deteching circuit 14 includes that drain electrode is connected on charge accumulation node ND Reset transistor 26.On the grid of reset transistor 26, it is connected to the reset letter being connect with vertical scanning circuit 46 Number line 36.Reseting signal line 36 and address signal line 34 are equally by each row setting according to multiple pixel 10A.Vertical scanning electricity Road 46 can be selected as the pixel 10A of the object of reset by applying row selection signal to address signal line 34 with row unit. In addition, vertical scanning circuit 46 passes through the reset signal unlatched and closed that will control reset transistor 26 via reseting signal line 36 apply to the grid of reset transistor 26, can open the reset transistor 26 of selected row.Pass through reset transistor 26 are turned on, and the current potential of charge accumulation node ND is reset.

In this embodiment, the source electrode of reset transistor 26 is connected the feedback of each column setting according to multiple pixel 10A On 1 in line 53.That is, in this embodiment, as by the resetting voltage of the charge initialization of photoelectric conversion department 12, feedback line 53 Voltage is supplied to charge accumulation node ND.Here, above-mentioned feedback line 53 is connected each column according to multiple pixel 10A On corresponding 1 output terminal in the reversal amplifier 50 of setting.Reversal amplifier 50 can be above-mentioned peripheral circuit 40 A part.

1 be conceived in the column of multiple pixel 10A.As illustrated, the inversing input terminal quilt of reversal amplifier 50 It is connected on the vertical signal line 35 of the column.In addition, the output terminal of reversal amplifier 50 and the picture for belonging to 1 of the column or more Plain 10A is connected via feedback line 53.In the movement of photographic device 100A, to the non-inverting input terminal of reversal amplifier 50 Voltage Vref (such as positive voltage near 1V or 1V) as defined in supplying.Pass through 1 or more pixel 10A for selecting to belong to the column In 1, address transistor 24 and reset transistor 26 are opened, so as to form the output negative-feedback for making pixel 10A Feedback path.By the formation of feedback path, the voltage of vertical signal line 35 converges on the non-inverted to reversal amplifier 50 The input voltage Vref of input terminal.In other words, by the formation of feedback path, the voltage of charge accumulation node ND is reset to The voltage of vertical signal line 35 becomes voltage as Vref.As voltage Vref, supply voltage (such as 3.3V) can be used And the voltage of the arbitrary size in the range of ground voltage (0V).Reversal amplifier 50 can also be referred to as feedback amplifier. In this way, photographic device 100A has the feed circuit 16 in a part of feedback path comprising reversal amplifier 50.

As is known, the thermal noise for being referred to as kTC noise occurs for opening or closing with transistor.With reset Opening or closing for transistor and the noise that occurs is referred to as reset noise.After the reset of the current potential in charge accumulation region, lead to The reset noise closing reset transistor and occurring is crossed to remain in the charge accumulation region before the accumulation of signal charge.But It is that the reset noise occurred with the closing of reset transistor can be by being reduced using feedback.Utilize the reset of feedback The details of the inhibition of noise is illustrated in International Publication No. 2012/147302.In order to refer to, help in the present specification With No. 2012/147302 complete disclosure of International Publication No..

In the structure illustrated by Fig. 2, by the formation of feedback path, it is brilliant that the alternating component of thermal noise is fed back to reset The source electrode of body pipe 26.In the structure illustrated by Fig. 2, due to all forming feedback road until reset transistor 26 will close Diameter, so can reduce the reset noise occurred with the closing of reset transistor 26.

Fig. 3 is the plan view of the layout in the pixel 10A for indicate embodiment.Fig. 4 is the general of the equipment construction of pixel 10A Slightly sectional view.Shape when Fig. 3 is showed schematically pixel 10A shown in Fig. 4 from the direction vertical with semiconductor substrate 60 At the configuration of each element (amplifying transistor 22, address transistor 24 and reset transistor 26 etc.) on semiconductor substrate 60. Here, amplifying transistor 22 and address transistor 24 are along the up and down direction of paper linearly to configure.

Fig. 4 is the summary sectional view of the equipment construction of the pixel 10A of embodiment.Fig. 4 is will along the line A-A in Fig. 3 Pixel 10A cutting, to arrow direction expansion in the case where sectional view.

In addition, the 1st diffusion zone 67n as p-type impurity region is the drain electrode of reset transistor 26 in Fig. 3 and Fig. 4 Region is charge accumulation region (FD).

As shown in Figures 3 and 4, the pixel 10A in the photographic device 100A in relation to present embodiment has the 1st transistor (being reset transistor 26 here).1st transistor is located in semiconductor substrate, miscellaneous comprising the 1st conductivity type (hereinafter referred to as N-shaped) Matter, including accumulating the 1st diffusion zone 67n by the transformed optical charge of photoelectric conversion department 12 as source electrode and a side of drain electrode, Including the 2nd diffusion zone 68an as the p-type impurity region for containing p-type impurity as source electrode and another party of drain electrode.At this In embodiment, the concentration of the p-type impurity of the 1st diffusion zone 67n is smaller than the concentration of the p-type impurity of the 2nd diffusion zone 68an.

In turn, it (is amplifying transistor 22 or ground here that pixel 10A, which has 2nd transistor different from reset transistor 26, Location transistor 24), the 2nd transistor is located in semiconductor substrate 60, including the 3rd diffusion zone containing p-type impurity (hereinafter, claiming Make other p-type impurities region 68bn, 68cn, 68dn) it is used as source electrode or drain electrode.At this point, the p-type impurity of the 1st diffusion zone 67n Concentration can also be than the p-type impurity of other p-type impurity region 68bn, 68cn and 68dn (hereinafter referred to as 68bn~68dn) Concentration is small.At this point, the concentration of the p-type impurity of the 1st diffusion zone 67n can also be at least than the 2nd diffusion zone 68an and others n The 1/10 of the concentration of the p-type impurity of type extrinsic region 68bn~68dn is small, can also be 1/15 smaller than it.1st diffusion zone as a result, 67n becomes smaller with the engagement concentration at the joint portion of semiconductor substrate 60, so the electric field strength at joint portion can be mitigated.Cause This, 67n's or is reduced to the leakage current of the 1st diffusion zone 67n from the 1st diffusion zone as charge accumulation region.

In addition, in the photographic device 100A in relation to present embodiment, semiconductor substrate 60 containing the 2nd conductivity type (hereinafter, Referred to as p-type) impurity, be adjacent to the 1st diffusion region in the p-type impurity and semiconductor substrate 60 contained in the 1st diffusion zone 67n The concentration of the n-type impurity contained in the part of domain 67n is also possible to 1 × 10¹⁶atoms/cm³Above 5 × 10¹⁶atoms/cm³With Under.The engagement concentration of the 1st diffusion zone 67n and semiconductor substrate 60 become smaller as a result, the electric field strength being able to suppress at joint portion Rising.Therefore, the leakage current at joint portion can be reduced.

It shows schematically as in Fig. 4 like that, pixel 10A generally includes semiconductor substrate 60, configuration semiconductor-based The photoelectric conversion department 12 and Wiring structure 80 of the top of plate 60.Wiring structure 80 includes being configured in be formed in photoelectric conversion department 12 In interlayer insulating film 90 between semiconductor substrate 60 and will be formed in the amplifying transistor on semiconductor substrate 60 22 with The construction that photoelectric conversion department 12 is electrically connected.Here, it includes insulating layer 90a, 90b, 90c and 90d (following that interlayer insulating film 90, which has, Be denoted as 90a~90d) 4 layers of insulating layer lit-par-lit structure, Wiring structure 80 have wiring layer 80a, 80b, 80c and 80d (with Under be denoted as 80a~80d) 4 layers of wiring layer and configuration these wiring interlayers plug (plug) pa1, pa2, pb, pc and pd.In addition, wiring layer 80a includes contact plunger cp1, cp2, cp3, cp4, cp5, cp6 and cp7 (hereinafter referred to as cp1~cp7). In addition, it goes without saying that the quantity of the insulating layer in interlayer insulating film 90 and the quantity of the wiring layer in Wiring structure 80 are simultaneously unlimited Due to the example, can arbitrarily set.

Photoelectric conversion department 12 is configured on interlayer insulating film 90.Photoelectric conversion department 12 includes being formed in interlayer insulating film Pixel electrode 12a on 90, to the transparent electrode 12c and configuration for being placed in pixel electrode 12a in these interelectrode photoelectricity Transform layer 12b.The photoelectric conversion layer 12b of photoelectric conversion department 12 is formed by the inorganic material of organic material or amorphous silicon etc., is received Via the light of transparent electrode 12c incidence, the charge just and born is generated by light-to-current inversion.Photoelectric conversion layer 12b typically across More multiple pixel 10A and formed.In addition, photoelectric conversion layer 12b also may include the layer being made of organic material and by inorganic material Expect the layer constituted.

Transparent electrode 12c is formed by the transparent conductive material of ITO etc., is configured in the light of photoelectric conversion layer 12b Surface side.Transparent electrode 12c is typically same as photoelectric conversion layer 12b, is formed across multiple pixel 10A.It is omitted in Fig. 4 Diagram, but transparent electrode 12c has and the connection of above-mentioned accumulation control line 39.In the movement of photographic device 100A, lead to It crosses the current potential of control accumulation control line 39 and keeps the current potential of transparent electrode 12c different from the current potential of pixel electrode 12a, so as to The signal charge generated by light-to-current inversion pixel electrode 12a is collected.For example, the current potential of control accumulation control line 39, so that The current potential of transparent electrode 12c becomes higher than the current potential of pixel electrode 12a.Specifically, the positive voltage of such as 10V or so is applied On accumulation control line 39.Thereby, it is possible to the hole that will be generated by photoelectric conversion layer 12b-electronics centering hole pixel electricity Pole 12a is collected.The signal charge collected by pixel electrode 12a is accumulated via Wiring structure 80 into the 1st diffusion zone 67n.

Pixel electrode 12a is to be endowed electric conductivity by the metal of aluminium, copper etc., metal nitride or by impurity The electrode of the formation such as polysilicon.Pixel electrode 12a by the pixel electrode 12a with adjacent other pixel 10A spatially Separation, and it is electrically separated with the pixel electrode 12a of other pixel 10A.

Semiconductor substrate 60 includes supporting substrates 61 and 1 or more semiconductor layer being formed on supporting substrates 61.This In, p-type silicon (Si) substrate is illustrated as supporting substrates 61.In this embodiment, semiconductor substrate 60 has the p on supporting substrates 61 The p-type semiconductor layer on n-type semiconductor layer 62n, n-type semiconductor layer 62n on type semiconductor layer 61p, p-type semiconductor layer 61p P-type semiconductor layer 65p on 63p and p-type semiconductor layer 63p.P-type semiconductor layer 63p throughout supporting substrates 61 whole face and shape At.P-type semiconductor layer 65p has that the concentration p-type 66p lower than p-type semiconductor layer 65p of impurity, to be formed in p-type miscellaneous The 1st diffusion zone 67n, the 2nd diffusion zone 68an and p-type impurity region 68bn~68dn and element separation in the 66p of matter region Region 69.

P-type semiconductor layer 61p, n-type semiconductor layer 62n, p-type semiconductor layer 63p and p-type semiconductor layer 65p are typical respectively Be to be formed and carrying out the ion implanting of impurity to the semiconductor layer that is formed with epitaxial growth.P-type semiconductor layer 63p and Impurity concentration in p-type semiconductor layer 65p is degree same to each other, and higher than the impurity concentration of p-type semiconductor layer 61p.Quilt Configure n-type semiconductor layer 62n between p-type semiconductor layer 61p and p-type semiconductor layer 63p inhibit from supporting substrates 61 or Inflow of a small amount of carrier of peripheral circuit 40 to the 1st diffusion zone 67n as the charge accumulation region for accumulating signal charge. In the movement of photographic device 100A, the current potential of n-type semiconductor layer 62n is via setting in the outer of imaging area R1 (referring to Fig.1) The trap contact portion (not shown) of side and controlled.

In addition, in this embodiment, semiconductor substrate 60 has p-type semiconductor layer 61p and n-type semiconductor layer 62n perforation, sets Set the p-type area 64 between p-type semiconductor layer 63p and supporting substrates 61.P-type area 64 and p-type semiconductor layer 63p and p-type Semiconductor layer 65p compares impurity concentration with higher, and p-type semiconductor layer 63p and supporting substrates 61 are electrically connected.It is filled in camera shooting When setting the movement of 100A, the current potentials of p-type semiconductor layer 63p and supporting substrates 61 via the outside that imaging area R1 is set base Plate contact portion (not shown) and controlled.Configuring p-type semiconductor layer 65p in a manner of connecting with p-type semiconductor layer 63p, In the movement of photographic device 100A, the current potential of p-type semiconductor layer 65p can be controlled via p-type semiconductor layer 63p.

On semiconductor substrate 60, amplifying transistor 22, address transistor 24 and reset transistor 26 are formed.Reset crystal Pipe 26 includes the 1st diffusion zone 67n and the 2nd diffusion zone 68an, the insulating layer 70 being formed on semiconductor substrate 60 and insulation Gate electrode 26e on layer 70.Drain region of the 1st diffusion zone 67n and the 2nd diffusion zone 68an as reset transistor 26 And source region functions respectively.1st diffusion zone 67n as the signal charge that will be generated by photoelectric conversion department 12 temporarily The charge accumulation region of accumulation functions.

Amplifying transistor 22 includes on p-type impurity region 68bn and 68cn, a part of insulating layer 70 and insulating layer 70 Gate electrode 22e.P-type impurity region 68bn and 68cn is played respectively as the drain region of amplifying transistor 22 and source region Function.

The configuration element separated region 69 between p-type impurity region 68bn and the 1st diffusion zone 67n.Component separation area 69 be, for example, the impurity diffusion region of p-type.It is by component separation area 69 that amplifying transistor 22 and reset transistor 26 is electrically separated.

Show schematically that the 1st diffusion zone 67n and component separation area 69 pass through in n-type impurity area like that as in Fig. 4 The 1st diffusion zone 67n is formed in the 66p of domain, is configured in a manner of mutually non-touching.For example, as component separation area 69 And in the case where using n-type impurity layer, the p if the 1st diffusion zone 67n is contacted with component separation area 69, at joint portion The two of type impurity concentration and p-type impurity concentration is got higher.Therefore, in the engagement of the 1st diffusion zone 67n and component separation area 69 Portion periphery is easy to happen the leakage current due to the higher engagement concentration.In other words, by by the 1st diffusion zone 67n and member Part separated region 69 is configured in a manner of mutually non-touching, even if using the n-type impurity of high concentration in component separation area 69 Layer is also able to suppress the rising of pn-junction concentration, inhibits leakage current.In addition, having as component separation area 69 and using STI The method of (Shallow Trench Isolation: shallow trench isolation), but in the case also for reduction due to the side STI The leakage current of crystal defect at wall portion preferably configures the 1st diffusion zone 67n and STI in a manner of not contacting with each other.

Component separation area 69 is also deployed between the pixel 10A to adjoin each other, between them by signal deteching circuit 14 is electrically separated from each other.Here, component separation area 69 is arranged on around the group of amplifying transistor 22 and address transistor 24 And around reset transistor 26.

Address transistor 24 includes on p-type impurity region 68cn and 68dn, a part of insulating layer 70 and insulating layer 70 Gate electrode 24e.In this embodiment, address transistor 24 is electrically connected by sharing p-type impurity region 68cn with amplifying transistor 22 It connects on amplifying transistor 22.P-type impurity region 68cn is functioned as the drain region of address transistor 24, p-type impurity Region 68dn is functioned as the source region of address transistor 24.

In this embodiment, by the gate electrode 26e of reset transistor 26, the gate electrode 22e of amplifying transistor 22 and ground Insulating layer 72 is arranged in the mode of the gate electrode 24e covering of location transistor 24.Insulating layer 72 is, for example, silicon oxide layer.In the example In, also insulating layer 71 is clamped between insulating layer 72 and gate electrode 26e, gate electrode 22e and gate electrode 24e.Insulation Layer 71 is, for example, silicon oxide layer.Insulating layer 71 also can have the lit-par-lit structure including multiple insulating layers.Equally, above-mentioned insulation Layer 72 also can have the lit-par-lit structure including multiple insulating layers.

The lit-par-lit structure of insulating layer 72 and insulating layer 71 has multiple contact holes.Here, in insulating layer 72 and insulating layer 71 In be provided with contact hole h1~h7.Contact hole h1~h4 is respectively formed in and the 1st diffusion zone 67n, the 2nd diffusion zone 68an And at the position of others p-type impurity region 68bn and 68dn overlapping.In the position of contact hole h1~h4, it is each configured with contact Plug cp1~cp4.Contact hole h5~h7 is respectively formed in and gate electrode 26e, gate electrode 22e and gate electrode 24e weight Folded position.Contact plunger cp5~cp7 is each configured at the position of contact hole h5~h7.

In the structure illustrated by Fig. 4, wiring layer 80a is the layer with contact plunger cp1~cp7, is typically adulterated There is the polysilicon layer of p-type impurity.Wiring layer 80a be configured in it is in the wiring layer in Wiring structure 80 included, away from semiconductor-based Plate 60 is most nearby.Wiring layer 80b and plug pa1 and pa2 are configured in insulating layer 90a.Plug pa1 is by contact plunger cp1 It is connected with wiring layer 80b, plug pa2 connects contact plunger cp6 with wiring layer 80b.That is, the 1st diffusion zone 67n and amplification are brilliant The gate electrode 22e of body pipe 22 is mutually electrically connected via contact plunger cp1 and cp6, plug pa1 and pa2 and wiring layer 80b It connects.

Wiring layer 80b is configured in insulating layer 90a, can include in part of it above-mentioned vertical signal line 35, Address signal line 34, power-supply wiring 32, reseting signal line 36 and feedback line 53 etc..Vertical signal line 35, address signal line 34, electricity Source wiring 32, reseting signal line 36 and feedback line 53 are connected n via contact plunger cp4, cp7, cp3, cp5 and cp2 respectively On type extrinsic region 68dn, gate electrode 24e, p-type impurity region 68bn, gate electrode 26e and the 2nd diffusion zone 68an.

Wiring layer 80b is connect by the plug pb being configured in insulating layer 90b with wiring layer 80c.Equally, configuration is being insulated Wiring layer 80c is connect by the plug pc in layer 90c with wiring layer 80d.Plug pd in insulating layer 90d is configured by wiring layer 80d is connect with the pixel electrode 12a of photoelectric conversion department 12.Wiring layer 80b~80d and plug pa1, pa2, pb~pd are typically The metallic compound etc. of metal, metal nitride or metal oxide by copper or tungsten etc. etc. is formed.

Plug pa1, pa2, pb~pd, wiring layer 80b~80d, contact plunger cp1, cp6 by photoelectric conversion department 12 and are formed Signal deteching circuit 14 on semiconductor substrate 60 is electrically connected.Plug pa1, pa2, pb~pd, wiring layer 80b~80d, contact Plug cp1, cp6, the pixel electrode 12a of photoelectric conversion department 12, amplifying transistor 22 gate electrode 22e and the 1st diffusion zone 67n accumulates the signal charge (being hole here) generated by photoelectric conversion department 12.

Here, it is conceived to the p-type impurity region being formed on semiconductor substrate 60.The n being formed on semiconductor substrate 60 The 1st diffusion zone 67n in type extrinsic region is configured in the n-type impurity being formed in the p-type semiconductor layer 65p as p trap In the 66p of region.1st diffusion zone 67n is formed near the surface of semiconductor substrate 60, and at least part is located at semiconductor The surface of substrate 60.The junction capacity formed by the pn-junction between p-type 66p and the 1st diffusion zone 67n is as accumulation letter At least part of capacitor of number charge functions, and constitutes a part in charge accumulation region.

In the structure illustrated by Fig. 4, the 1st diffusion zone 67n includes the 1st region 67a and the 2nd region 67b.1st diffusion The impurity concentration of the 1st region 67a of region 67n is than the 2nd diffusion zone 68an and other p-type impurity region 68bn~68dn It is low.The 2nd region 67b in 1st diffusion zone 67n is formed in the 1st region 67a, has the impurity than the 1st region 67a high Concentration.In addition, contact hole h1 is located on the 2nd region 67b, contact plunger cp1 is connected the 2nd region 67b via contact hole h1 On.

As described above, p-type semiconductor layer 65p is configured and being adjacent to p-type semiconductor layer 63p, in photographic device The current potential of p-type semiconductor layer 65p can be controlled when the movement of 100A via p-type semiconductor layer 63p.Adopting with such a configuration With can have part (this that is contacted with the contact plunger cp1 of the electrical connection of photoelectric conversion department 12 with semiconductor substrate 60 In be the 1st diffusion zone 67n the 2nd region 67b) around, the relatively low region of configuration impurity concentration (is the 1st to expand here Dissipate the 1st region 67a and p-type 66p of region 67n).The formation of the 2nd region 67b in 1st diffusion zone 67n is not It is necessary.But it is dense as contact plunger cp1 and the impurity of the 2nd region 67b of the coupling part of semiconductor substrate 60 by making It spends relatively high, can obtain what depletion layer was diffused into around the coupling part of contact plunger cp1 and semiconductor substrate 60 and (exhausts) Effect.In this way, exhausting around the part contacted by inhibition contact plunger cp1 with semiconductor substrate 60, has been able to suppress Because the crystal defect of the semiconductor substrate 60 in contact plunger cp1 Yu the interface of semiconductor substrate 60 (may also be referred to as interface Energy level) leakage current.In addition, by being connected to contact plunger cp1 on the 2nd region 67b with relatively high impurity concentration, It can obtain reducing the effect of contact resistance.

In addition, in this embodiment, between the 2nd region 67b and p-type 66p of the 1st diffusion zone 67n, clipping miscellaneous The matter concentration 1st region 67a lower than the 2nd region 67b, in the 2nd region 67b and p-type semiconductor layer 65p of the 1st diffusion zone 67n Between also clip the 1st region 67a.By the way that the 1st relatively low region 67a of impurity concentration to be configured to the week in the 2nd region 67b It encloses, the electric field strength that can will be formed by the pn-junction of the 1st diffusion zone 67n and p-type semiconductor layer 65p or p-type 66p It mitigates.By mitigating the electric field strength, inhibit the leakage current due to the electric field formed by pn-junction.

As showing schematically in Fig. 3, pixel 10A has and will have the 1st diffusion zone as source electrode and drain electrode Other transistors that the reset transistor 26 of 67n and the 2nd diffusion zone 68an and pixel 10A have (are that amplification is brilliant here Body pipe 22 and address transistor 24) separation separated region (hereinafter referred to as component separation area 69).Component separation area 69 Impurity as contained 2nd conductivity type (hereinafter referred to as p-type) different from N-shaped.At this point, the 1st diffusion zone 67n and being formed in the 1st Component separation area 69 around diffusion zone 67n is matched in a manner of not contacting with each other in the surface of semiconductor substrate 60 It sets.

Specifically, the 1st diffusion zone 67n is formed on the concentration n-type impurity lower than p-type semiconductor layer 65p of impurity In the 66p of region.Depletion layer area is formed between the 1st diffusion zone 67n and p-type 66p.In general, and semiconductor Crystal defect density in the inside of substrate 60 is compared, and the crystal defect density near the surface of semiconductor substrate 60 is higher.Cause This, in the depletion layer area being formed at the joint portion (pn-junction portion) that the 1st diffusion zone 67n is engaged with p-type 66p In, it is formed in depletion layer area at the joint portion near the surface of semiconductor substrate 60 and is formed in the interior of semiconductor substrate 60 Depletion layer area at the pn-junction portion in portion is compared, and leakage current is bigger.

In addition, if being formed in depletion layer area (the hereinafter referred to as interface consumption at the joint portion on the surface of semiconductor substrate 60 To the greatest extent layer) area increase, then leakage current is easy to increase.Therefore, it is intended that consuming the interface exposed on the surface of semiconductor substrate 60 The area of layer becomes minimum to the greatest extent.In order to make the area of the interface depletion layer become smaller, when from the direction perpendicular to semiconductor substrate 60 When observation, the area of the 1st diffusion zone 67n can also be formed as smaller than the 2nd diffusion zone 68an.For example, when from semiconductor When the vertical direction of substrate 60 is observed, the area of the 1st diffusion zone 67n is also possible to the 1/2 of the area of the 2nd diffusion zone 68an Below.In addition, the width of the channel width dimension of the 1st diffusion zone 67n is also possible to the ditch of the 2nd diffusion zone 68an at this time 1/2 or less the width of road width direction.In addition, the 1st diffusion zone 67n and the 2nd diffusion zone 68an are also possible to ditch road width The one party for spending the width in direction and the length of channel length direction is identical size.In addition, about the others in pixel 10A P-type impurity region 68bn~68dn is also the same, when from the direction vertical with semiconductor substrate 60, the 1st diffusion zone 67n Area can also be formed as smaller than the area of other p-type impurity region 68bn~68dn.

In addition, the area of above-mentioned 1st diffusion zone 67n and the 2nd diffusion zone 68an is when from perpendicular to semiconductor substrate When direction is observed, or the not grid with reset transistor 26 in the 1st diffusion zone 67n and the 2nd diffusion zone 68an The area of the part of electrode 26e overlapping.Equally, the area about other p-type impurity region 68bn~68dn is also possible to work as When from the direction perpendicular to semiconductor substrate 60, be set as in other p-type impurity region 68bn~68dn not with amplification The area of the part of the gate electrode 24e overlapping of the gate electrode 22e and address transistor 24 of transistor 22.When from perpendicular to half Conductor substrate 60 direction observation when, with these transistors gate electrode 22e, 24e, 26e be overlapped part compared with not with grid The part of pole electrode 22e, 24e and 26e overlapping, is not easily susceptible to damage during fabrication.Example as the damage being subject to during fabrication Son can be enumerated and be damaged as the plasma treatment bring used in dry-etching process and when by removing resist Ashing processing bring damage.Therefore, leakage current is not susceptible in the part Chong Die with gate electrode 22e, 24e, 26e.Thus, It is because about the 1st diffusion zone 67n and other p-type impurities region in terms of making the area of interface depletion layer become smaller 68bn~68dn can also only consider the influence of the area of part not Chong Die with gate electrode.

In addition, by making the area of the 1st diffusion zone 67n become smaller, the contact hole h1 that is formed on the 1st diffusion zone 67n The distance between gate electrode 26e for example than the contact hole h2 that is formed on the 2nd diffusion zone 68an and gate electrode 26e it Between distance it is small.That is, when from the direction perpendicular to semiconductor substrate 60, contact plunger cp1 and the 1st diffusion zone 67n Coupling part and grid of the coupling part at a distance from gate electrode 26e, than contact plunger cp2 and the 2nd diffusion zone 68an The distance of electrode 26e is small.As described above, the 1st diffusion zone 67n due to impurity concentration it is lower, so resistance value than the 2nd diffusion Region 68an high.Thus, become smaller at a distance from gate electrode 26e by making contact hole h1, the electric current in the 1st diffusion zone 67n Path shortens, so the resistance value in the 1st diffusion zone 67n becomes smaller.In addition, about other p-type impurity region 68bn and 68dn is also the same, is formed in the contact hole h1 in the 1st diffusion zone 67n at a distance from gate electrode 26e, can also be than being formed in Contact hole h3 and h4 in these p-type impurity region 68bn and 68dn is small at a distance from gate electrode 22e and 24e.That is, when from When the vertical direction of semiconductor substrate 60 is observed, the coupling part and gate electrode of contact plunger cp1 and the 1st diffusion zone 67n The distance of 26e, can also be than the coupling part of contact plunger cp3 and p-type impurity region 68bn at a distance from gate electrode 22e It is small.In addition, when from the direction perpendicular to semiconductor substrate 60, the connection of contact plunger cp1 and the 1st diffusion zone 67n It part, can also coupling part and grid than contact plunger cp4 and p-type impurity region 68dn at a distance from gate electrode 26e The distance of electrode 24e is small.

(variation 1)

Fig. 5 is the figure for indicating the circuit structure of the photographic device 100B in relation to modified embodiment of the present embodiment 1.Shown in Fig. 5 Pixel 10B and pixel 10A shown in Fig. 2 between main difference, be that anti-burn is formed on semiconductor substrate 60 With 28 this point of transistor.Hereinafter, being illustrated centered on the point different from embodiment, specifically about common point Bright omission.

As shown in figure 5, charge accumulation node ND is by the drain electrode of reset transistor 26, the grid of amplifying transistor 22, photoelectricity The source electrode and grid electrical connection of the lower electrode of transformation component 12 and anti-burn transistor 28.Here, the leakage of reset transistor 26 Pole is the 1st diffusion zone 67n as charge accumulation region.Anti- burn with the source electrode of transistor 28 be connected VDD wiring or On the anti-burn dedicated power supply line 41 of transistor 28.Here, if excessive light is incident in light-to-current inversion film 12b, the 1st The current potential of diffusion zone 67n is possible to more than VDD.By being with the threshold voltage settings of transistor 28 by anti-burn, expand the 1st Dissipate region 67n current potential it is equal with VDD in the case where open, can be by the charge of surplus from the 1st diffusion zone 67n to power supply line 41 dissipations.As a result, it is possible to prevent the failure of burn etc..

Fig. 6 is the plan view of the layout in the pixel 10B for indicate modified embodiment of the present embodiment 1.As shown in fig. 6, this change It (is anti-here that pixel 10B in shape example, which is also equipped with 3rd transistor different from the 1st transistor (being reset transistor 26 here), Burn transistor 28).Anti- burn transistor 28 includes gate electrode 28e, source region and drain region.Here, the 1st expands Region 67n is dissipated to be functioned as anti-burn with the drain region of transistor 28.In addition, the 1st diffusion zone 67n is also as reset The drain region of transistor 26 functions.In this way, the 1st diffusion zone 67n is by as drain region in above-mentioned 2 transistors Domain shares.P-type impurity region 68en is functioned as anti-burn with the source region of transistor 28.

Here, the concentration of the p-type impurity of the 1st diffusion zone 67n can also be denseer than the p-type impurity of p-type impurity region 68en It spends small.The concentration of the p-type impurity of the 1st diffusion zone 67n becomes than other p-type impurity region 68bn in pixel 10B as a result, The concentration of the p-type impurity of~68ec is small.The engagement concentration of the 1st diffusion zone 67n and semiconductor substrate 60 become smaller as a result, so Leakage current can be reduced.

Fig. 7 is the summary sectional view of the equipment construction of the pixel of this variation.As shown in fig. 7, anti-burn transistor 28 Gate electrode 28e be formed on semiconductor substrate 60 via gate insulating film 70.P-type impurity region 68en is formed on half On the surface of conductor substrate 60.

If excessive light is incident in light-to-current inversion film 12b, the current potential of the 1st diffusion zone 67n rises to and is applied The bias same degree being added on transparent electrode 12c.If such overvoltage is applied on the 1st diffusion zone 67n, have Possible 1st diffusion zone 67n is destroyed or the gate insulating film 70 of amplifying transistor 22 is destroyed.As a result, burn etc. occurs Failure.

On the other hand, according to this modification, it is able to suppress dark current, and also can in the case where excessive light is incident Prevent the failure of each transistor as caused by overvoltage.

(variation 2)

Fig. 8 is the flat of the layout in the pixel 10C indicated in the photographic device 100C in relation to modified embodiment of the present embodiment 2 Face figure.In this variation, the 1st diffusion zone (FD) 67n is round when from the direction perpendicular to semiconductor substrate 60 This point is different from pixel 10A.Hereinafter, being illustrated centered on the point different from embodiment, about the detailed of common point Illustrate omit.

In this variation, as described above, when from the direction perpendicular to semiconductor substrate 60, the 1st diffusion region Domain (FD) 67n is round.As a result, the area on the surface of the semiconductor substrate 60 of the 1st diffusion zone 67n be formed it is rectangular-shaped The case where compared to becoming smaller.Therefore, in the surface of semiconductor substrate 60, in connecing for the 1st diffusion zone 67n and semiconductor substrate 60 The area of the interface depletion layer formed at conjunction portion becomes smaller.Thereby, it is possible to reduce the leakage current at joint portion.

In addition, in this variation, it is same as the photographic device 100A in relation to embodiment, do not have anti-burn crystal Pipe 28, but can also have anti-burn transistor 28 as the photographic device 100B in relation to variation 1.Even if mistake as a result, Big light is incident in photoelectric conversion department 12, can also prevent the failure of each transistor as caused by overvoltage.

(variation 3)

Fig. 9 is the circuit structure for indicating the pixel 10D in the photographic device 100D in relation to modified embodiment of the present embodiment 3 Figure.Figure 10 is the plan view of the layout in the pixel 10D for indicate this variation.In above embodiment and variation, with tool Favorably with being illustrated for the photographic device of the photoelectric conversion department of light-to-current inversion film, but in this variation, so as to use up Electric diode for the photographic device of photoelectric conversion department as being illustrated.

As shown in FIG. 9 and 10, the pixel 10D of this variation has photodiode 13 and transfers transistor 27.Photoelectricity Diode 13 has p-type impurity region 68fn and the pinning layer (not shown) positioned at the top of p-type impurity region 68fn.Pinning layer It is p-type.Photodiode 13 received light will carry out light-to-current inversion and generate charge in the time for exposure.It is providing Time for exposure after, be applied to transfer crystal via transferring signal wire 37 and will make to transfer the transfer signal opened of transistor 27 On the grid of pipe 27.Transferring transistor 27 as a result, becomes open state, and the charge that photodiode 13 generates is forwarded to charge Accumulate node ND.Amplifying transistor 22 is by signal corresponding with the charge for being forwarded to charge accumulation node ND to vertical signal line 35 outputs (not shown).The signal being output in vertical signal line 35 is carried out AD change to the supply (not shown) of AD transformation component It changes.

As shown in Figure 10, transfer transistor 27 include the 1st diffusion zone 67n and p-type impurity region 68fn as source electrode and Drain electrode.In addition, transferring transistor 27 includes gate electrode 27e.Transfer transistor 27 using the 1st diffusion zone 67n as source electrode and Drain electrode a side and between reset transistor 26 share.

In addition, as shown in figure 9, charge accumulation node ND is by the drain electrode of reset transistor 26, the grid of amplifying transistor 22 It is electrically connected with the source electrode for transferring transistor 27.Here, the drain electrode of the reset transistor 26 in Figure 10 is as charge accumulation region The 1st diffusion zone 67n.

In this variation, same as above embodiment and variation, it (is multiple here that pixel 10D, which has the 1st transistor, Bit transistor 26).1st transistor is located in semiconductor substrate, the impurity containing N-shaped, and accumulation is converted by photodiode 13 1st diffusion zone 67n of optical charge afterwards is as source electrode and a side of drain electrode, including the p-type impurity as the impurity containing N-shaped The 2nd diffusion zone 68an in region is as source electrode and another party of drain electrode.At this point, the p-type impurity of the 1st diffusion zone 67n is dense The concentration of the p-type impurity of 2 diffusion zone 68an of Du Bi is small.The joint portion of 1st diffusion zone 67n and semiconductor substrate as a result, The engagement concentration at place becomes smaller, so the leakage current in the 1st diffusion zone 67n is reduced.

In turn, pixel 10D has 2nd transistor (be here amplifying transistor 22) different from reset transistor 26, and the 2nd Transistor includes the 3rd diffusion zone (the hereinafter referred to as other p-type impurities being located in semiconductor substrate 60, containing p-type impurity Region 68bn and 68cn) it is used as source electrode or drain electrode.At this point, the concentration of the p-type impurity of the 1st diffusion zone 67n can also be than other P-type impurity region 68bn and 68cn p-type impurity concentration it is small.At this point, the concentration of the p-type impurity of the 1st diffusion zone 67n Can p-type impurity at least than the 2nd diffusion zone 68an and other p-type impurity region 68bn and 68cn concentration 1/10 It is small, it can also be smaller than 1/15.The 1st diffusion zone 67n becomes smaller with the engagement concentration at the joint portion of semiconductor substrate 60 as a result, So the electric field strength at joint portion can be mitigated.Therefore, from the 1st diffusion zone 67n's as charge accumulation region Or it is reduced towards the leakage current of the 1st diffusion zone 67n.

In addition, semiconductor substrate 60 contains n-type impurity, the 1st diffusion region in the photographic device 100D in relation to this variation The p-type contained in the part for being adjacent to the 1st diffusion zone 67n in p-type impurity and semiconductor substrate 60 contained in the 67n of domain is miscellaneous The concentration of matter is also possible to 1 × 10¹⁶atoms/cm³Above 5 × 10¹⁶atoms/cm³Below.As a result, the 1st diffusion zone 67n with The engagement concentration of semiconductor substrate 60 becomes smaller, and is able to suppress the rising of the electric field strength at joint portion.Therefore, engagement can be reduced Leakage current at portion.

In addition, if depletion layer area (the hereinafter referred to as interface being formed at the joint portion on the surface of semiconductor substrate 60 Depletion layer) area increase, then leakage current is easy to increase.Therefore, it is intended that making the interface exposed on the surface of semiconductor substrate 60 The area of depletion layer becomes minimum.In order to make the area of the interface depletion layer become smaller, when from the side perpendicular to semiconductor substrate 60 To when observation, the area of the 1st diffusion zone 67n can also be formed as smaller than the 2nd diffusion zone 68an.For example, when from partly lead When the vertical direction of structure base board 60 is observed, the area of the 1st diffusion zone 67n is also possible to the area of the 2nd diffusion zone 68an 1/2 or less.In addition, at this point, the width of the channel width dimension of the 1st diffusion zone 67n is also possible to the 2nd diffusion zone 68an's 1/2 or less the width of channel width dimension.In addition, the 1st diffusion zone 67n and the 2nd diffusion zone 68an are also possible to channel The one party of the length of the width and channel length direction of width direction is identical size.In addition, about other in pixel 10D P-type impurity region 68bn and 68cn it is also the same, when from the direction perpendicular to semiconductor substrate 60, the 1st diffusion zone The area of 67n can also be formed as smaller than the area of other p-type impurity region 68bn and 68cn.

In addition, the area of above-mentioned the 1st diffusion zone 67n and the 2nd diffusion zone 68an may be when from perpendicular to half The not grid with reset transistor 26 when the direction observation of conductor substrate in the 1st diffusion zone 67n and the 2nd diffusion zone 68an The area of the part of electrode 26e overlapping.Equally, the area about other p-type impurity region 68bn and 68cn, or when When from the direction perpendicular to semiconductor substrate 60 in others p-type impurity region 68bn and 68cn not with amplification crystal The area of the part of the gate electrode 22e overlapping of pipe 22.When from the direction perpendicular to semiconductor substrate 60, with these crystalline substances The part of gate electrode 22e and the 26e overlapping of body pipe is compared to the not part Chong Die with gate electrode 22e and 26e, during fabrication not Vulnerable to damage.As the example for the damage being subject to during fabrication, can enumerate as used in dry-etching process it is equal from The damage of subprocessing bring and ashing processing bring damage when by removing resist.Therefore, with gate electrode 22e And the part of 26e overlapping is not susceptible to leakage current.Thus, in terms of making the area of interface depletion layer become smaller, be because about 1st diffusion zone 67n and other p-type impurities region 68bn and 68dn can also only consider part not Chong Die with gate electrode Area influence.

In addition, by making the area of the 1st diffusion zone 67n become smaller, the contact hole h1 that is formed in the 1st diffusion zone 67n The distance between gate electrode 26e, such as the contact hole h2 than being formed in the 2nd diffusion zone 68an and gate electrode 26e The distance between it is small.As described above, the 1st diffusion zone 67n due to impurity concentration it is lower, so resistance value become than the 2nd expand Dissipate region 68an high.Thus, become smaller at a distance from gate electrode 26e by making contact hole h1, the electricity in the 1st diffusion zone 67n Flow path shortens, so the resistance value in the 1st diffusion zone 67n becomes smaller.In addition, about other p-type impurity region 68bn and 68cn is also the same, and the contact hole h1 being formed in the 1st diffusion zone 67n can also be than being formed at a distance from gate electrode 26e Contact hole h3 and h9 in these p-type impurity region 68bn and 68cn is small at a distance from gate electrode 22e.

More than, the photographic device in relation to the disclosure is illustrated based on embodiment and variation, but the disclosure is simultaneously It is not limited to these embodiments and variation.Without departing from the purport of the disclosure, embodiment and variation are implemented Form after the various modifications that those skilled in the art expect or by the constituent element of a part in embodiment and variation The other form for combining and constructing is also contained in the scope of the present disclosure.

In addition, influenced due to that can reduce by leakage current bring according to embodiment of the present disclosure and variation, so Provide a kind of photographic device that can be imaged with high image quality.In addition, above-mentioned amplifying transistor 22, address transistor 24, the respective either N-channel MOS, is also possible to P-channel MOS of transistor 28 is used in reset transistor 26 and anti-burn.Each In the case that transistor is P-channel MOS, the impurity of the 1st conductivity type is n-type impurity, and the impurity of the 2nd conductivity type is p-type impurity.? Do not need to make the whole of these transistors be unified for N-channel MOS or P-channel MOS certain.By the transistor in pixel respectively As N-channel MOS, as signal charge and in the case where using electronics, as long as by the respective source electrode of these transistors and leakage The configuration of pole is replaced mutually.

Industrial availability

According to the disclosure, providing a kind of be able to suppress is influenced by dark current bring and is taken the photograph with what high image quality was imaged As device.The photographic device of the disclosure is for example useful for imaging sensor, digital camera etc..The camera shooting of the disclosure fills Set the camera etc. that can be used in medical camera, robot camera, security cameras, carrying in the car and use In.

Label declaration

10A, 10B, 10C, 10D pixel

12 photoelectric conversion departments

13 photodiodes

14 signal deteching circuits

16 feed circuits

22 amplifying transistors

22e, 24e, 26e, 27e, 28e gate electrode

24 address transistors

26 reset transistors

27 transfer transistor

Transistor is used in 28 anti-burns

32 power-supply wirings

35 vertical signal lines

36 reseting signal lines

40 peripheral circuits

42 load circuits

44 column signal processing circuits

48 horizontal signal reading circuits

50 reversal amplifiers

53 feedback lines

60 semiconductor substrates

61 supporting substrates

61p, 63p, 65p p-type semiconductor layer

62n n-type semiconductor layer

64p type region

66p p-type

The 1st region 67a

The 2nd region 67b

The 1st diffusion zone of 67n

The 2nd diffusion zone of 68an

68bn, 68cn, 68dn, 68en, 68fn p-type impurity region

69 component separation areas

70,71,72,90a, 90b, 90c, 90d insulating layer

80 Wiring structures

80a, 80b, 80c, 80d wiring layer

90 interlayer insulating films

100A, 100B, 100C, 100D photographic device

The imaging area R1

The neighboring area R2

Cp1, cp2, cp3, cp4, cp5, cp6, cp7, cp8 contact plunger

H1, h2, h3, h4, h5, h6, h7, h8, h9 contact hole

Pa1, pa2, pb, pc, pd plug

Claims (9)

1. a kind of photographic device, which is characterized in that

Have:

Semiconductor substrate, the 2nd of the 1st diffusion zone including the impurity containing the 1st conductivity type and the impurity containing the 1st conductivity type the Diffusion zone；With

Multiple pixels；

Above-mentioned multiple pixels respectively include:

Light is transformed to charge by photoelectric conversion department；With

1st transistor, including source electrode, drain electrode and gate electrode, and including accumulating at least part of above-mentioned of above-mentioned charge 1st diffusion zone is as above-mentioned source electrode and a side of above-mentioned drain electrode, including above-mentioned 2nd diffusion zone is as above-mentioned source electrode and above-mentioned Another party of drain electrode；

The concentration of the impurity of the 1st conductivity type in above-mentioned 1st diffusion zone is than the 1st conductivity type in above-mentioned 2nd diffusion zone The concentration of impurity is low；

When from the direction vertical with above-mentioned semiconductor substrate, above-mentioned 2nd diffusion region of area ratio of above-mentioned 1st diffusion zone The area in domain is small.

2. photographic device as described in claim 1, which is characterized in that

Above-mentioned semiconductor substrate further includes the 3rd diffusion zone of the impurity containing the 1st conductivity type；

Above-mentioned multiple pixels are separately included including above-mentioned 3rd diffusion zone as source electrode and the 2nd transistor of a side of drain electrode；

The concentration of the impurity of the 1st conductivity type in above-mentioned 1st diffusion zone is than the 1st conductivity type in above-mentioned 3rd diffusion zone The concentration of impurity is low.

3. photographic device as described in claim 1, which is characterized in that

Above-mentioned multiple pixels are separately included including above-mentioned 1st diffusion zone as source electrode and the 3rd transistor of a side of drain electrode.

4. photographic device as described in claim 1, which is characterized in that

The above-mentioned area of above-mentioned 1st diffusion zone is above-mentioned 1st expansion when from the direction vertical with above-mentioned semiconductor substrate Dissipate the area of the not part Chong Die with above-mentioned gate electrode in region；

The above-mentioned area of above-mentioned 2nd diffusion zone is above-mentioned 2nd expansion when from the direction vertical with above-mentioned semiconductor substrate Dissipate the area of the not part Chong Die with above-mentioned gate electrode in region.

5. photographic device as described in claim 1, which is characterized in that

Above-mentioned multiple pixels respectively include:

1st plug is connected to the part 1 of above-mentioned 1st diffusion zone；With

2nd plug is connected to the part 2 of above-mentioned 2nd diffusion zone；

When from the direction vertical with above-mentioned semiconductor substrate, above-mentioned part 1 is at a distance from above-mentioned gate electrode than upper It is small at a distance from above-mentioned gate electrode to state part 2.

6. photographic device as described in claim 1, which is characterized in that

Above-mentioned semiconductor substrate includes the 4th diffusion zone of the impurity containing 2nd conductivity type different from the 1st conductivity type；

Above-mentioned multiple pixels further include respectively other transistors other than above-mentioned 1st transistor, and including above-mentioned 4th diffusion region Domain is as by the separated region of above-mentioned 1st transistor and other above-mentioned transistors separateds；

Above-mentioned 4th diffusion zone does not contact in the surface of above-mentioned semiconductor substrate with above-mentioned 1st diffusion zone.

7. photographic device as described in claim 1, which is characterized in that

Above-mentioned semiconductor substrate contains the impurity of 2nd conductivity type different from the 1st conductivity type；

The concentration of the impurity of the 1st conductivity type contained in above-mentioned 1st diffusion zone is 1 × 10¹⁶atoms/cm³Above and 5 × 10¹⁶atoms/cm³Below；

The impurity of the 2nd conductivity type contained in the part adjacent with above-mentioned 1st diffusion zone in above-mentioned semiconductor substrate it is dense Degree is 1 × 10¹⁶atoms/cm³Above and 5 × 10¹⁶atoms/cm³Below.

8. photographic device as described in claim 1, which is characterized in that

When from the direction vertical with above-mentioned semiconductor substrate, above-mentioned 1st diffusion zone is round.

9. a kind of photographic device, which is characterized in that

Have:

Semiconductor substrate, the 2nd of the 1st diffusion zone including the impurity containing the 1st conductivity type and the impurity containing the 1st conductivity type the Diffusion zone；With

Multiple pixels；

Above-mentioned multiple pixels respectively include:

Light is transformed to charge by photoelectric conversion department；

1st transistor, including source electrode, drain electrode and gate electrode, and including accumulating at least part of above-mentioned of above-mentioned charge 1st diffusion zone is as above-mentioned source electrode and a side of above-mentioned drain electrode, including above-mentioned 2nd diffusion zone is as above-mentioned source electrode and above-mentioned Another party of drain electrode；

1st plug is connected to the part 1 of above-mentioned 1st diffusion zone；With

2nd plug is connected to the part 2 of above-mentioned 2nd diffusion zone；

The concentration of the impurity of the 1st conductivity type in above-mentioned 1st diffusion zone is than the 1st conductivity type in above-mentioned 2nd diffusion zone The concentration of impurity is low；

When from the direction vertical with above-mentioned semiconductor substrate, above-mentioned part 1 is at a distance from above-mentioned gate electrode than upper It is small at a distance from above-mentioned gate electrode to state part 2.