TW201909383A - Camera - Google Patents

Abstract

[Problem] Provide an imaging device capable of suppressing dark current. [Solution] An imaging device including a semiconductor substrate and a plurality of pixels, the semiconductor substrate having a first diffusion region containing impurities of a first conductivity type and a second diffusion region containing impurities of a first conductivity type; Each pixel has a photoelectric conversion unit that converts light into electric charges, and a first transistor; the first transistor includes a source electrode, a drain electrode, and a gate electrode, and the first electrode that accumulates at least a portion of the electric charge. The diffusion field is included as one of the source and the drain, and the second diffusion field is included as the other of the source and the drain; the first conduction in the first diffusion field is included. The impurity concentration of the first diffusion type is smaller than that of the first conductivity type in the second diffusion region; when viewed from a direction perpendicular to the semiconductor substrate, the area of the first diffusion region is larger than that of the second diffusion region. Small area.

Description

Shooting device

The present disclosure relates to a photographing device.

CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used in digital cameras and the like. It is known that these image sensors have a photodiode formed on a semiconductor substrate.

On the other hand, a structure has been proposed in which a photoelectric conversion section having a photoelectric conversion layer is disposed above a semiconductor substrate (for example, Patent Documents 1 and 2). An imaging device having such a structure is sometimes called a laminated type imaging device. In a multilayer imaging device, charges generated by photoelectric conversion are accumulated in a charge accumulation field (referred to as "FD: floating diffusion"). The signal corresponding to the amount of charge accumulated in the charge accumulation area is read through a CCD circuit or a CMOS circuit formed on a semiconductor substrate. Prior technical literature Patent literature

Patent Document 1: International Publication No. 2014/002330 Patent Document 2: International Publication No. 2012/147302

Problems to be Solved by the Invention In a multi-layer type imaging device, a leakage current (hereinafter, sometimes referred to as “dark current”) from the charge accumulation field or the charge accumulation field may deteriorate the obtained image. It would be beneficial if such leakage currents could be reduced.

Means to solve the problem

A photographing device related to one aspect of the present disclosure includes a semiconductor substrate and a plurality of pixels. The semiconductor substrate has a first diffusion region including impurities of a first conductivity type and a second diffusion region including impurities of a first conductivity type. Field; each of the plurality of pixels has a photoelectric conversion unit that converts light into charges, and a first transistor; the first transistor includes a source electrode, a drain electrode, and a gate electrode, and at least a portion of the charge is accumulated The first diffusion field is included as one of the source and the drain, and the second diffusion field is included as the other of the source and the drain; in the first diffusion field, The concentration of impurities in the first conductivity type is smaller than the concentration of impurities in the first conductivity type in the second diffusion region; when viewed from a direction perpendicular to the semiconductor substrate, the area of the first diffusion region is larger than that of the first diffusion region. 2 The area of the diffusion area is small.

An overall or specific aspect may also be implemented as a component, device, module, system, or method. In addition, the overall or specific aspects can also be realized by any combination of components, devices, modules, systems, and methods.

The additional effects and advantages of the disclosed embodiment will be apparent from the description and drawings. The effects and / or advantages are provided separately from various embodiments or features disclosed in the description and drawings, and do not need to be adopted in order to obtain more than one of them. Invention effect

According to the present disclosure, an imaging device capable of suppressing dark current can be provided.

Detailed Description of the Preferred Embodiment An outline of one aspect of the present disclosure is as follows.

[Item 1] An imaging device having a semiconductor substrate and a plurality of pixels, the semiconductor substrate having a first diffusion region containing impurities of a first conductivity type and a second diffusion region containing impurities of a first conductivity type; Each pixel has a photoelectric conversion unit that converts light into electric charges, and a first transistor; the first transistor includes a source electrode, a drain electrode, and a gate electrode, and the first electrode that accumulates at least a portion of the electric charge. The diffusion field is included as one of the source and the drain, and the second diffusion field is included as the other of the source and the drain; the first conduction in the first diffusion field is included. The concentration of the impurity in the type is smaller than the concentration of the impurity in the first conductivity type in the second diffusion region; when viewed from a direction perpendicular to the semiconductor substrate, the area of the first diffusion region is larger than that of the second diffusion region. Small area.

In this way, the impurity concentration of the first conductivity type contained in the first diffusion region is smaller than the impurity concentration of other diffusion regions containing the impurity of the first conductivity type in the pixel. Thereby, since the bonding density with the junction portion of the semiconductor substrate in the first diffusion region is small, the leakage current in the first diffusion region is reduced.

Furthermore, the area of the empty layer formed on the junction portion between the first diffusion region and the semiconductor substrate, especially the surface of the semiconductor substrate, can be reduced. Since the crystal defects near the surface of the semiconductor substrate become larger, if an empty layer is formed here, the leakage current becomes larger. Therefore, the leakage current can be reduced by reducing the area of the empty layer on the surface of the semiconductor substrate. [Item 2] The photographing device according to item 1, wherein the semiconductor substrate further has a third diffusion region containing impurities of a first conductivity type; the plurality of pixels each have a region in which the third diffusion region is used as a source and a drain. One of them includes a second transistor; the concentration of impurities of the first conductivity type in the first diffusion region is smaller than the concentration of impurities of the first conductivity type in the third diffusion region. [Item 3] The photographing device according to Item 1 or 2, wherein each of the plurality of pixels has a third transistor including the first diffusion area as one of a source and a drain. [Item 4] The imaging device of Item 1, wherein the area of the first diffusion area is an area of a portion of the first diffusion area that does not overlap the gate electrode when viewed from a direction perpendicular to the semiconductor substrate. The area of the second diffusion area is an area of a portion of the second diffusion area that does not overlap the gate electrode when viewed from a direction perpendicular to the semiconductor substrate.

[Item 5] The photographing device according to any one of Items 1 to 4, wherein each of the plurality of pixels has a first plug connected to the first part of the first diffusion area, and a second plug connected to the second part. The second plug connected to the second part of the diffusion field; when viewed from a direction perpendicular to the semiconductor substrate, the distance between the first part and the gate electrode is smaller than the distance between the second part and the gate electrode.

Accordingly, since the distance from the first plug in the first diffusion region to the gate electrode of the first transistor is short, the increase in the resistance value in the first diffusion region can be reduced.

[Item 6] The photographing device according to any one of Items 1 to 5, wherein the semiconductor substrate has a fourth diffusion region, and the fourth diffusion region includes impurities of a second conductivity type different from the first conductivity type; The pixels each have a transistor other than the first transistor, and the fourth diffusion region is included as a separation region in which the first transistor is separated from the other transistors; the fourth diffusion region is included in the foregoing The surface of the semiconductor substrate is not in contact with the first diffusion region.

In this way, the surface of the semiconductor substrate on which the leakage current is most prone is not in contact with the first diffusion region containing impurities of the first conductivity type and the separation region containing impurities of the second conductivity type different from the first conductivity type. Therefore, the leakage current at the joint portion on the surface of the semiconductor substrate can be reduced.

[Item 7] The photographing device according to any one of Items 1 to 6, wherein the semiconductor substrate contains impurities of a second conductivity type different from the first conductivity type; impurities of the first conductivity type included in the aforementioned first diffusion field the concentration of 1 × 10 ¹⁶ atoms / cm ³ or ^{more, 5 × 10 16 atoms / cm} 3 or less; concentration of the second conductivity type of the impurity of the semiconductor substrate in the above-described first diffusion adjacent to the portion of the field contains the 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁶ atoms / cm ³ or less.

In this way, by reducing the concentration of the impurities in the first conductivity type and the second conductivity type, it is possible to suppress an increase in the electric field strength at the junction between the first diffusion region and the semiconductor substrate, and to reduce the leakage current.

[Item 8] The photographing device according to any one of Items 1 to 7, wherein the first diffusion area is circular when viewed from a direction perpendicular to the semiconductor substrate.

Thereby, since the area of the first diffusion region on the surface of the semiconductor substrate is small, the area of the empty layer formed on the junction portion of the surface of the semiconductor substrate can be made small. This can reduce the leakage current. [Item 9] An imaging device including a semiconductor substrate and a plurality of pixels, the semiconductor substrate having a first diffusion region containing impurities of a first conductivity type and a second diffusion region containing impurities of a first conductivity type; Each pixel includes: a photoelectric conversion unit that converts light into electric charges; a first transistor including a source electrode, a drain electrode, and a gate electrode, and regards the first diffusion area in which at least a portion of the electric charge is accumulated as the source electrode And one of the aforementioned drain electrodes is included, and the aforementioned second diffusion domain is included as the other of the aforementioned source electrode and the aforementioned drain electrodes; a first plug is connected to the first part of the aforementioned first diffusion domain; The second plug is connected to the second part of the second diffusion area; the concentration of impurities of the first conductivity type in the first diffusion area is smaller than the concentration of impurities of the first conductivity type in the second diffusion area. When viewed from a direction perpendicular to the semiconductor substrate, the distance between the first portion and the gate electrode is smaller than the distance between the second portion and the gate electrode.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Incidentally, the embodiments described below are all summary or specific examples. The numerical values, shapes, materials, constituent elements, arrangement and connection forms, steps, and order of steps shown in the following embodiments are examples, and the gist is not intended to limit the present disclosure. As long as no contradiction occurs, the various aspects described in this specification can be combined with each other. In addition, among the constituent elements of the following embodiments, the constituent elements that are not described in the independent request item representing the highest-level concept are described as arbitrary constituent elements. In each figure, the constituent elements having substantially the same function are shown by common reference symbols, and duplicate descriptions are sometimes omitted or simplified.

In addition, various elements shown in the drawings are only schematic representations for understanding the present disclosure, and the size ratio and appearance may be different from the actual objects.

Incidentally, in this manual, the light-receiving side of the photographing device is regarded as "upper", and the opposite side of the light-receiving side is regarded as "lower". The same applies to the "upper surface" and "lower surface" of each component. The surface facing the light-receiving side of the imaging device is regarded as the "upper surface", and the surface facing the opposite side of the light-receiving side is regarded as the "lower surface". Incidentally, the terms "upper", "lower", "upper", and "lower" are only used to specify the mutual arrangement of components, and are not intended to limit the posture when using the camera.

(Embodiment) FIG. 1 is a configuration diagram of a photographing apparatus according to this embodiment. As shown in FIG. 1, a photographing device 100A related to this embodiment includes a plurality of pixels 10A and a peripheral circuit 40 formed on a semiconductor substrate 60. Each pixel 10A includes a photoelectric conversion section 12 arranged above a semiconductor substrate 60. That is, as an example of an imaging device related to the present disclosure, a laminated type imaging device 100A will be described.

In the example shown in FIG. 1, the pixels 10A are arranged in a matrix of m columns and n rows. Here, m and n are integers of 2 or more. The pixels 10A are arranged in a two-dimensional manner on the semiconductor substrate 60, for example, thereby forming an imaging area R1. As described above, each of the pixels 10A includes the photoelectric conversion section 12 disposed above the semiconductor substrate 60. Therefore, the imaging area R1 is defined as the area covered by the photoelectric conversion section 12 in the semiconductor substrate 60. Incidentally, although the photoelectric conversion sections 12 of each pixel 10A are shown as being separated from each other in space in FIG. 1 for convenience of explanation, the photoelectric conversion sections 12 of a plurality of pixels 10A may be arranged on a semiconductor substrate without an interval therebetween. 60 on.

The number and arrangement of the pixels 10A are not limited to the illustrated examples. For example, the number of pixels 10A included in the photographing device 100A may be one. Although in this example, the center of each pixel 10A is located on a grid point of a square grid, the configuration of the pixel 10A may not be so. For example, the plurality of pixels 10A may be arranged such that each center is located on a grid point such as a triangular grid or a hexagonal grid. If the pixels 10A are arranged one-dimensionally, the imaging device 100A can be used as a linear sensor.

In the configuration shown by way of example in FIG. 1, the peripheral circuit 40 includes a vertical scanning circuit (also referred to as a “column scanning circuit”) 46 and a horizontal signal reading circuit (also referred to as a “row scanning circuit”) 48. The vertical scanning circuit 46 is connected to an address signal line 34 provided corresponding to each column of the plurality of pixels 10A. The horizontal signal reading circuit 48 is connected to a vertical signal line 35 provided corresponding to each row of the plurality of pixels 10A. As shown schematically in FIG. 1, these circuits are arranged in a peripheral area R2 outside the shooting area R1. The peripheral circuit 40 may further include a signal processing circuit, an output circuit, a control circuit, and a power supply for supplying a predetermined voltage to each pixel 10A. A part of the peripheral circuit 40 may be arranged on a substrate different from the semiconductor substrate 60 on which the pixel 10A is formed.

FIG. 2 is a diagram showing a circuit configuration of the imaging device 100A according to the embodiment. In order to prevent the drawing from becoming complicated, FIG. 2 displays four pixels 10A arranged in two rows and two columns among the plurality of pixels 10A shown in FIG. 1.

The photoelectric conversion section 12 of each pixel 10A receives the incidence of light and causes positive and negative charges (typically a hole-electron pair) to occur. The photoelectric conversion section 12 of each pixel 10A is connected to the accumulation control line 39. When the imaging device 100A operates, the accumulation control line 39 is applied with a predetermined voltage. By applying a predetermined voltage to the accumulation control line 39, the electric charge of one of the positive and negative charges generated by the photoelectric conversion can be selectively accumulated in the electric charge accumulation field. The following example shows the case where the positive charge of the positive and negative charges generated by photoelectric conversion is used as a signal charge.

Each pixel 10A includes a signal detection circuit 14 electrically connected to the photoelectric conversion section 12. In the structure shown by way of example in FIG. 2, the signal detection circuit 14 includes an amplifier transistor 22 (also referred to as a “read transistor”) and a reset transistor 26. In this example, the signal detection circuit 14 further includes an address transistor (also referred to as a "column selection transistor") 24. As described in detail below with reference to the drawings, the amplification transistor 22, the reset transistor 26, and the address transistor 24 of the signal detection circuit 14 are typically field-effect transistors formed on a semiconductor substrate 60 supporting the photoelectric conversion section 12. (FET: Field Effect Transistor). In the following, unless specifically mentioned, an example in which an N-channel MOS (Metal Oxide Semiconductor) transistor is used as the transistor is described. Incidentally, which of the two diffusion layers of the FET is equivalent to the source and the drain is determined by the polarity of the FET and the level of the potential at that moment. Therefore, which one is the source and the drain varies with the operating state of the FET.

As shown schematically in FIG. 2, the gate of the amplifier transistor 22 is electrically connected to the photoelectric conversion unit 12. The charge generated by the photoelectric conversion section 12 is a charge accumulation node (also referred to as a “Floating Diffusion node”) accumulated between the photoelectric conversion section 12 and the amplifier transistor 22 (ND). Incidentally, the charge storage node ND refers to a field that electrically connects the charge storage area, the gate of the amplifier transistor 22, the lower electrode of the photoelectric conversion unit 12, and the charge storage area.

The drain of the amplifier transistor 22 is connected to a power supply wiring (also referred to as a source-coupled power supply) 32 that supplies a predetermined power supply voltage VDD (for example, about 3.3V) to each pixel 10A when the imaging device 100A is in operation. In other words, the amplifier transistor 22 outputs a signal voltage corresponding to the amount of signal charge generated by the photoelectric conversion section 12. The source of the amplifier transistor 22 is connected to the drain of the address transistor 24.

The source of the address transistor 24 is connected to the vertical signal line 35. As shown in the figure, the vertical signal line 35 is provided for each of a plurality of pixels 10A, and the vertical signal line 35 is connected to a load circuit 42 and a column signal processing circuit (also referred to as a “column signal accumulation circuit”) 44. The load circuit 42 forms a source follower circuit together with the amplifier transistor 22.

The gate of the address transistor 24 is connected to the address signal line 34. The address signal line 34 is provided for each of the plurality of pixels 10A. The address signal line 34 is connected to the vertical scanning circuit 46. The vertical scanning circuit 46 applies a column selection signal to the address signal line 34 to control the opening and closing of the address transistor 24. Thereby, the column of the read object is scanned in the vertical direction (row direction), and the column of the read object is selected. The vertical scanning circuit 46 controls the turning on and off of the address transistor 24 through the address signal line 34, whereby the output of the gain transistor 22 of the selected pixel 10A can be read by the corresponding vertical signal line 35. The configuration of the address transistor 24 is not limited to the example shown in FIG. 2, and may be between the drain of the amplifier transistor 22 and the power supply wiring 32.

The signal voltage from the pixel 10A that is output to the vertical signal line 35 through the address transistor 24 is input to a plurality of column signal processing circuits 44 corresponding to the vertical signal line 35 and arranged in the rows of each pixel 10A. Corresponding column signal processing circuit 44. The field signal processing circuit 44 and the load circuit 42 may be part of the peripheral circuit 40 described above.

The column signal processing circuit 44 performs suppressed noise signal processing and analog-to-digital conversion (AD conversion) and the like represented by correlated double sampling. The field signal processing circuit 44 is connected to the horizontal signal reading circuit 48. The horizontal signal reading circuit 48 sequentially reads signals from the plurality of column signal processing circuits 44 to the horizontal common signal line 49.

In the structure shown in FIG. 2 as an example, the signal detection circuit 14 includes a reset transistor 26 that connects the drain to the charge accumulation node ND. The gate of the reset transistor 26 is connected to a reset signal line 36 connected to the vertical scanning circuit 46. The reset signal line 36 is provided for each of the plurality of pixels 10A in the same manner as the address signal line 34. The vertical scanning circuit 46 may select a pixel 10A to be a reset target in a row unit by applying a row selection signal to the address signal line 34. In addition, the vertical scanning circuit 46 can apply a reset transistor to the gate of the reset transistor 26 by applying a reset signal that controls the opening and closing of the reset transistor 26 through the reset signal line 36. 26 is on. Because the reset transistor 26 is turned on, the potential of the charge accumulation node ND is reset.

In this example, the source of the reset transistor 26 is connected to one of the feedback lines 53 provided for each of the plurality of pixels 10A. That is, in this example, the voltage of the feedback line 53 is supplied to the charge accumulation node ND as a reset voltage for initializing the charge of the photoelectric conversion section 12. Here, the above-mentioned feedback line 53 is connected to the output terminal of one of the inverting amplifiers 50 corresponding to the inverting amplifier 50 provided for each of the plurality of pixels 10A. The inverting amplifier 50 may be part of the peripheral circuit 40 described above.

Focus on one of the rows of a plurality of pixels 10A. As shown, the inverting input terminal of the inverting amplifier 50 is connected to the vertical signal line 35 of the row. In addition, the output terminal of the inverting amplifier 50 and one or more pixels 10A belonging to the same row are connected through a feedback line 53. When the photographing device 100A is operated, a predetermined voltage Vref (for example, a positive voltage of 1V or around 1V) is supplied to the non-inverting input terminal of the inverting amplifier 50. By selecting one of the one or more pixels 10A belonging to the row, the address transistor 24 and the reset transistor 26 are turned on, thereby forming a feedback path that makes the output of the pixel 10A negative. Due to the formation of the feedback path, the voltage of the vertical signal line 35 converges toward the input voltage Vref for the non-inverting input terminal of the inverting amplifier 50. In other words, due to the formation of the feedback path, the voltage of the charge accumulation node ND and the voltage of the vertical signal line 35 are reset to a voltage like Vref. Regarding the voltage Vref, a voltage of any magnitude within a range of a power supply voltage (for example, 3.3 V) and a ground voltage (0 V) can be used. The inverting amplifier 50 may also be referred to as a feedback amplifier. As such, the imaging device 100A includes a feedback circuit 16 including the inverting amplifier 50 as a part of the feedback path.

As the transistor is turned on or off, it is known that thermal noise called kTC noise occurs. The noise that occurs when the reset transistor is turned on or off is called reset noise. The reset noise generated when the reset transistor is turned off after the potential in the charge accumulation area is reset will remain in the charge accumulation area before the signal charge is accumulated. However, by using feedback, the reset noise that occurs as the reset transistor is turned off can be reduced. International Publication No. 2012/147302 describes the use of feedback to suppress reset noise in detail. For reference, the entire disclosure of International Publication No. 2012/147302 is incorporated in this specification.

In the configuration shown in FIG. 2 as an example, the AC component of the thermal noise is fed back to the source of the reset transistor 26 due to the formation of the feedback path. In the configuration shown in FIG. 2 as an example, since a feedback path is formed until a moment before the reset transistor 26 is turned off, it is possible to reduce reset noise that occurs with the reset transistor 26 turned off.

FIG. 3 is a plan view showing a layout in a pixel 10A according to the embodiment. FIG. 4 is a schematic cross-sectional view showing a device structure of the pixel 10A. FIG. 3 is a schematic view showing each element (amplifier transistor 22, address transistor 24, and reset transistor 26) formed on the semiconductor substrate 60 when the pixel 10A shown in FIG. 4 is viewed from a direction perpendicular to the semiconductor substrate 60. Etc.) configuration. Here, the amplification transistor 22 and the address transistor 24 are arranged linearly along the up-down direction of the paper surface.

FIG. 4 is a schematic cross-sectional view of the device structure of the pixel 10A according to the embodiment. FIG. 4 is a cross-sectional view in a case where the pixel 10A is cut along the line A-A in FIG. 3 and expanded in the direction of an arrow.

Incidentally, in FIGS. 3 and 4, the first diffusion region 67 n which is an n-type impurity region is a drain region of the reset transistor 26 and is a charge accumulation region (FD).

As shown in FIGS. 3 and 4, the pixel 10A of the imaging device 100A according to this embodiment includes a first transistor (here, the reset transistor 26). The first transistor is an impurity located in a semiconductor substrate and containing a first conductivity type (hereinafter referred to as an n-type). The first diffusion region 67n in which the photocharges converted by the photoelectric conversion section 12 are accumulated is used as a source and One of the drains is included, and the second diffusion region 68an, which is an n-type impurity region containing n-type impurities, is included as the other of the source and the drain. In this embodiment, the concentration of n-type impurities in the first diffusion region 67n is smaller than the concentration of n-type impurities in the second diffusion region 68an.

In addition, the pixel 10A has a second transistor (here, the amplification transistor 22 or the address transistor 24) different from the reset transistor 26. The second transistor is located in the semiconductor substrate 60 and will include an n-type transistor. The third diffusion region of impurities (hereinafter referred to as other n-type impurity regions 68bn, 68cn, and 68dn) is included as a source or a drain. At this time, the concentration of the n-type impurity in the first diffusion region 67n may be lower than the concentration of the n-type impurity in the other n-type impurity regions 68bn, 68cn, and 68dn (hereinafter referred to as 68bn to 68dn.). At this time, the concentration of the n-type impurity in the first diffusion region 67n may be at least 1/10 smaller than the concentration of the n-type impurity in the second diffusion region 68an and other n-type impurity regions 68bn to 68dn, or may be greater than 1 / 15 small. Thereby, since the joint concentration in the joint portion between the first diffusion region 67n and the semiconductor substrate 60 is small, the electric field intensity at the joint portion can be relaxed. Therefore, the leakage current in the first diffusion region 67n which is itself a charge accumulation region or toward the first diffusion region 67n is reduced.

In addition, the imaging device 100A related to this embodiment may be as follows: the semiconductor substrate 60 includes impurities of the second conductivity type (hereinafter referred to as p-type), the concentration of n-type impurities included in the first diffusion region 67n, and the semiconductor The concentration of the p-type impurity contained in the portion of the substrate 60 adjacent to the first diffusion region 67n is 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁶ atoms / cm ³ or less. Thereby, the bonding density of the first diffusion region 67n and the semiconductor substrate 60 is small, and an increase in the electric field strength at the bonding portion can be suppressed. Therefore, it is possible to reduce the leakage current in the joint portion.

As shown schematically in FIG. 4, the pixel 10A is roughly provided with a semiconductor substrate 60, a photoelectric conversion section 12 disposed above the semiconductor substrate 60, and a wiring structure 80. The wiring structure 80 is arranged in the interlayer insulating layer 90 and has a structure for electrically connecting the amplifier transistor 22 formed on the semiconductor substrate 60 and the photoelectric conversion section 12, wherein the interlayer insulating layer 90 is formed in the photoelectric conversion section 12 and the semiconductor Between the substrates 60. Here, the interlayer insulating layer 90 has a laminated structure including four insulating layers of insulating layers 90a, 90b, 90c, and 90d (hereinafter referred to as 90a to 90d.), And the wiring structure 80 has wiring layers 80a, 80b, 80c, And four wiring layers of 80d (hereinafter referred to as 80a to 80d), and plugs pa1, pa2, pb, pc, and pd arranged between the wiring layers. The wiring layer 80a includes contact plugs cp1, cp2, cp3, cp4, cp5, cp6, and cp7 (hereinafter referred to as cp1 to cp7). Incidentally, as a matter of course, the number of insulating layers in the interlayer insulating layer 90 and the number of wiring layers in the wiring structure 80 are not limited to this example, and can be arbitrarily set.

The photoelectric conversion section 12 is disposed on the interlayer insulating layer 90. The photoelectric conversion section 12 includes a pixel electrode 12a formed on the interlayer insulating layer 90, a transparent electrode 12c facing the pixel electrode 12a, and a photoelectric conversion layer 12b disposed between the electrodes. The photoelectric conversion layer 12b of the photoelectric conversion section 12 is formed of an organic material or an inorganic material such as amorphous silicon, and receives light incident through the transparent electrode 12c, and generates positive and negative charges by photoelectric conversion. The photoelectric conversion layer 12b is typically formed across a plurality of pixels 10A. The photoelectric conversion layer 12b may include a layer made of an organic material and a layer made of an inorganic material.

The transparent electrode 12c is formed of a transparent conductive material such as ITO, and is disposed on the light-receiving surface side of the photoelectric conversion layer 12b. Like the photoelectric conversion layer 12b, the transparent electrode 12c is typically formed across a plurality of pixels 10A. Although not shown in FIG. 4, the transparent electrode 12 c has a connection to the accumulation control line 39 described above. When the photographing device 100A operates, the potential of the transparent electrode 12c and the potential of the pixel electrode 12a can be made different by controlling the potential of the accumulation control line 39, and the signal charge generated by the photoelectric conversion can be collected by the pixel electrode 12a. For example, the potential of the accumulation control line 39 is controlled so that the potential of the transparent electrode 12c is higher than the potential of the pixel electrode 12a. Specifically, for example, a positive voltage of approximately 10 V is applied to the accumulation control line 39. As a result, the hole-electron centering hole generated in the photoelectric conversion layer 12b can be collected by the pixel electrode 12a. The signal charges collected by the pixel electrode 12a are accumulated in the first diffusion region 67n through the wiring structure 80.

The pixel electrode 12a is an electrode formed of a metal such as aluminum or copper, a metal nitride, or polycrystalline silicon that is made conductive by doping impurities. The pixel electrode 12a is spatially separated from the pixel electrode 12a of another adjacent pixel 10A, thereby being electrically separated from the pixel electrode 12a of the other pixel 10A.

The semiconductor substrate 60 includes a support substrate 61 and one or more semiconductor layers formed on the support substrate 61. Here, a p-type silicon (Si) substrate is used as an example to show the support substrate 61. In this example, the semiconductor substrate 60 includes a p-type semiconductor layer 61p on the support substrate 61, an n-type semiconductor layer 62n on the p-type semiconductor layer 61p, a p-type semiconductor layer 63p on the n-type semiconductor layer 62n, and a p-type semiconductor. A p-type semiconductor layer 65p on the layer 63p. The p-type semiconductor layer 63 p is formed across the entire surface of the support substrate 61. The p-type semiconductor layer 65p has a p-type impurity region 66p having a lower concentration of impurities than the p-type semiconductor layer 65p, a first diffusion region 67n, a second diffusion region 68an, and an n-type impurity region 68bn formed in the p-type impurity region 66p. ~ 68dn, component separation area 69.

Each semiconductor layer of the p-type semiconductor layer 61p, the n-type semiconductor layer 62n, the p-type semiconductor layer 63p, and the p-type semiconductor layer 65p is typically formed by implanting impurity ions into a semiconductor layer formed by epitaxial growth. The impurity concentrations of the p-type semiconductor layer 63p and the p-type semiconductor layer 65p are approximately the same as each other and higher than the impurity concentration of the p-type semiconductor layer 61p. The n-type semiconductor layer 62n disposed between the p-type semiconductor layer 61p and the p-type semiconductor layer 63p is a first diffusion area that suppresses a small number of carriers from the support substrate 61 or the peripheral circuit 40 from being a charge accumulation area that accumulates signal charges. 67n inflow situation. During the operation of the imaging device 100A, the potential of the n-type semiconductor layer 62n is controlled through a well contact (not shown) provided outside the imaging area R1 (refer to FIG. 1).

In this example, the semiconductor substrate 60 has a p-type region 64 provided between the p-type semiconductor layer 63p and the support substrate 61 and penetrating the p-type semiconductor layer 61p and the n-type semiconductor layer 62n. Compared with the p-type semiconductor layer 63p and the p-type semiconductor layer 65p, the p-type region 64 has a higher impurity concentration and is electrically connected to the p-type semiconductor layer 63p and the support substrate 61. During the operation of the imaging device 100A, the potentials of the p-type semiconductor layer 63p and the support substrate 61 are controlled through substrate contacts (not shown) provided outside the imaging area R1. The p-type semiconductor layer 65p is arranged so as to be in contact with the p-type semiconductor layer 63p, whereby the potential of the p-type semiconductor layer 65p can be controlled by the p-type semiconductor layer 63p during the operation of the imaging device 100A.

An amplifier transistor 22, an address transistor 24, and a reset transistor 26 are formed on the semiconductor substrate 60. The reset transistor 26 includes a first diffusion region 67n, a second diffusion region 68an, an insulating layer 70 formed on the semiconductor substrate 60, and a gate electrode 26e on the insulating layer 70. The first diffusion region 67n and the second diffusion region 68an function as the drain region and the source region of the reset transistor 26, respectively. The first diffusion area 67n functions as a charge accumulation area in which signal charges generated by the photoelectric conversion section 12 are temporarily accumulated.

The amplifier transistor 22 includes n-type impurity regions 68bn, 68cn, a part of the insulating layer 70, and a gate electrode 22e on the insulating layer 70. The n-type impurity regions 68bn and 68cn function as the drain region and the source region of the gain transistor 22, respectively.

An element isolation region 69 is disposed between the n-type impurity region 68bn and the first diffusion region 67n. The element isolation region 69 is, for example, a p-type impurity diffusion region. Through the element separation area 69, the amplifier transistor 22 and the reset transistor 26 are electrically separated.

As shown schematically in FIG. 4, the first diffusion region 67 n is formed in the p-type impurity region 66 p, whereby the first diffusion region 67 n and the element isolation region 69 are disposed so as not to contact each other. For example, when a p-type impurity layer is used as the element isolation region 69, if the first diffusion region 67n is in contact with the element isolation region 69, both the p-type impurity concentration and the n-type impurity concentration at the junction will change. high. Therefore, a leakage current due to the high bonding concentration is liable to occur in the periphery of the bonding portion between the first diffusion region 67n and the element isolation region 69. In other words, by arranging the first diffusion region 67n and the element isolation region 69 so as not to contact each other, even if a high-concentration p-type impurity layer is used in the element isolation region 69, an increase in pn junction concentration can be suppressed. Suppress leakage current. In addition, although there is a method using STI (Shallow Trench Isolation) as the element isolation region 69, in this case, in order to reduce the leakage current caused by the crystal defect of the STI sidewall portion, it is desirable to reduce the first diffusion region 67n and the STI to Configured without touching each other.

An element separation area 69 is also disposed between the pixels 10A adjacent to each other, and the signal detection circuits 14 are electrically separated therebetween. Here, the element separation area 69 is provided around the group of the amplifier transistor 22 and the address transistor 24 and around the reset transistor 26.

The address transistor 24 includes n-type impurity regions 68cn, 68dn, a part of the insulating layer 70, and a gate electrode 24e on the insulating layer 70. In this example, the address transistor 24 is electrically connected to the amplifier transistor 22 by sharing the n-type impurity region 68cn with the amplifier transistor 22. The n-type impurity region 68cn functions as a drain region of the address transistor 24, and the n-type impurity region 68dn functions as a source region of the address transistor 24.

In this example, an insulating layer 72 is provided so as to cover the gate electrode 26e of the reset transistor 26, the gate electrode 22e of the amplifier transistor 22, and the gate electrode 24e of the address transistor 24. The insulating layer 72 is, for example, a silicon oxide film. In this example, an insulating layer 71 is further interposed between the insulating layer 72 and the gate electrode 26e, the gate electrode 22e, and the gate electrode 24e. The insulating layer 71 is, for example, a silicon oxide film. The insulating layer 71 may have a multilayer structure including a plurality of insulating layers. Similarly, the above-mentioned insulating layer 72 may have a laminated structure including a plurality of insulating layers.

The laminated structure of the insulating layer 72 and the insulating layer 71 has a plurality of contact holes. Here, contact holes h1 to h7 are provided in the insulating layer 72 and the insulating layer 71. The contact holes h1 to h4 are formed at positions overlapping the first diffusion region 67n, the second diffusion region 68an, and other n-type impurity regions 68bn and 68dn, respectively. Contact plugs cp1 to cp4 are arranged at the positions of the contact holes h1 to h4, respectively. The contact holes h5 to h7 are formed at positions overlapping the gate electrode 26e, the gate electrode 22e, and the gate electrode 24e, respectively. The contact holes h5 to h7 are respectively provided with contact plugs cp5 to cp7.

In the structure shown in FIG. 4 by way of example, the wiring layer 80a is a layer having contact plugs cp1 to cp7, and is typically a polycrystalline silicon layer doped with n-type impurities. Among the wiring layers included in the wiring structure 80, the wiring layer 80 a is arranged closest to the semiconductor substrate 60. The wiring layer 80b and the plugs pa1 and pa2 are arranged in the insulating layer 90a. The plug pa1 connects the contact plug cp1 with the wiring layer 80b, and the plug pa2 connects the contact plug cp6 with the wiring layer 80b. That is, the first diffusion region 67n and the gate electrode 22e of the amplifier transistor 22 are electrically connected to each other through the contact plugs cp1, cp6, the plugs pa1, pa2, and the wiring layer 80b.

The wiring layer 80b is disposed in the insulating layer 90a, and may include a part of the vertical signal line 35, the address signal line 34, the power supply wiring 32, the reset signal line 36, and the feedback line 53 described above. The vertical signal line 35, the address signal line 34, the power wiring 32, the reset signal line 36, and the feedback line 53 are respectively connected to the n-type impurity region 68dn and the gate electrode 24e through the contact plugs cp4, cp7, cp3, cp5, and cp2 The n-type impurity region 68bn, the gate electrode 26e, and the second diffusion region 68an are connected.

The plug pb disposed in the insulating layer 90b connects the wiring layer 80b and the wiring layer 80c. Similarly, the plug pc disposed in the insulating layer 90c connects the wiring layer 80c and the wiring layer 80d. The plug pd disposed in the insulating layer 90 d connects the wiring layer 80 d to the pixel electrode 12 a of the photoelectric conversion section 12. The wiring layers 80b to 80d and the plugs pa1, pa2, and pb to pd are typically formed of a metal such as copper or tungsten, a metal nitride, or a metal compound such as a metal oxide.

The plugs pa1, pa2, pb to pd, the wiring layers 80b to 80d, and the contact plugs cp1 and cp6 electrically connect the photoelectric conversion section 12 and the signal detection circuit 14 formed on the semiconductor substrate 60. The plugs pa1, pa2, pb to pd, the wiring layers 80b to 80d, the contact plugs cp1, cp6, the pixel electrode 12a of the photoelectric conversion section 12, the gate electrode 22e of the amplifier transistor 22, and the first diffusion area 67n The signal charges (here, holes) generated by the photoelectric conversion section 12 are accumulated.

Here, the n-type impurity region formed on the semiconductor substrate 60 will be focused on. In the n-type impurity region formed by the semiconductor substrate 60, the first diffusion region 67n is disposed in the p-type impurity region 66p formed as a p-well in the p-type semiconductor layer 65p. The first diffusion region 67n is formed near the surface of the semiconductor substrate 60, and at least a part thereof is located on the surface of the semiconductor substrate 60. The junction capacitance formed by the pn junction between the p-type impurity region 66p and the first diffusion region 67n functions as a capacitance that accumulates at least a portion of a signal charge, and constitutes a part of the charge accumulation region.

In the structure shown in FIG. 4 by way of example, the first diffusion region 67n includes the first region 67a and the second region 67b. The impurity concentration of the first region 67a of the first diffusion region 67n is lower than that of the second diffusion region 68an and other n-type impurity regions 68bn to 68dn. The second region 67b of the first diffusion region 67n is formed in the first region 67a and has a higher impurity concentration than the first region 67a. The contact hole h1 is located in the second area 67b, and the contact plug cp1 is connected to the second area 67b through the contact hole h1.

As described above, the p-type semiconductor layer 65p is disposed adjacent to the p-type semiconductor layer 63p, whereby the potential of the p-type semiconductor layer 65p can be controlled through the p-type semiconductor layer 63p during the operation of the imaging device 100A. By adopting such a structure, it is possible to surround the contact plug cp1 having electrical connection with the photoelectric conversion portion 12 and the portion (here, the second area 67b of the first diffusion area 67n and the second area 67b) in contact with the semiconductor substrate 60, A region where the impurity concentration is relatively low is arranged (here, the first region 67a of the first diffusion region 67n and the p-type impurity region 66p). It is not necessary to form the second region 67b in the first diffusion region 67n. However, by increasing the impurity concentration in the second area 67b, which is the connection portion between the contact plug cp1 and the semiconductor substrate 60, it is possible to suppress the empty layer from becoming wider around the connection portion between the contact plug cp1 and the semiconductor substrate 60 (Empty) effect. In this way, by suppressing vacancy around the portion where the contact plug cp1 is in contact with the semiconductor substrate 60, it is possible to suppress a crystal defect (also referred to as a crystal defect) of the semiconductor substrate 60 caused at the interface between the contact plug cp1 and the semiconductor substrate 60. Interface state). In addition, by connecting the contact plug cp1 to the second field 67b having a higher impurity concentration, an effect of reducing contact resistance can be obtained.

In this example, the second region 67b of the first diffusion region 67n and the p-type impurity region 66p are separated by the first region 67a having a lower impurity concentration than the second region 67b, and the second region 67b of the first diffusion region 67n and A first region 67a is also interposed between the p-type semiconductor layers 65p. By arranging the first region 67a having a relatively low impurity concentration around the second region 67b, the electric field strength formed by the pn junction between the first diffusion region 67n and the p-type semiconductor layer 65p or the p-type impurity region 66p can be relaxed. By reducing this electric field strength, the leakage current caused by the electric field formed by the pn junction is suppressed.

As shown schematically in FIG. 3, the pixel 10A includes: a reset transistor 26, and a first diffusion region 67n and a second diffusion region 68an as source and drain electrodes; and a separation region (hereinafter, referred to as an element separation region 69). ), To separate other transistors (here, the amplifier transistor 22 and the address transistor 24) included in the pixel 10A. The element isolation field 69 is, for example, an impurity including a second conductivity type (hereinafter referred to as a p-type) different from the n-type. At this time, the first diffusion region 67 n and the element isolation region 69 formed around the first diffusion region 67 n are disposed so as not to contact each other on the surface of the semiconductor substrate 60.

Specifically, the first diffusion region 67n is formed in a p-type impurity region 66p having an impurity concentration lower than that of the p-type semiconductor layer 65p. An empty layer region is formed between the first diffusion region 67n and the p-type impurity region 66p. Generally, the density of crystal defects near the surface of the semiconductor substrate 60 is higher than the density of crystal defects inside the semiconductor substrate 60. Therefore, the leakage current ratio of the empty layer region formed in the junction portion (pn junction) where the first diffusion region 67n and the p-type impurity region 66p are joined, the empty layer region formed in the junction portion near the surface of the semiconductor substrate 60. The leakage current in the empty layer region formed in the pn junction portion inside the semiconductor substrate 60 is large.

In addition, if the area of an empty layer region (hereinafter referred to as an interface empty layer) formed at a junction portion on the surface of the semiconductor substrate 60 is increased, the leakage current is likely to increase. Therefore, it is desirable to minimize the area of the interface empty layer exposed on the surface of the semiconductor substrate 60. In order to make the area of the interface empty layer small, it may be formed in such a manner that the area of the first diffusion region 67n is smaller than that of the second diffusion region 68an when viewed from a direction perpendicular to the semiconductor substrate 60. For example, when viewed from a direction perpendicular to the semiconductor substrate 60, the area of the first diffusion area 67n is less than or equal to 1/2 of the area of the second diffusion area 68an. In this case, the width in the channel width direction of the first diffusion region 67n may be equal to or less than 1/2 of the width in the channel width direction of the second diffusion region 68an. Incidentally, the first diffusion area 67n and the second diffusion area 68an may be the same size as one of the width in the channel width direction and the length in the channel length direction. In addition, the same applies to other n-type impurity regions 68bn to 68dn in the pixel 10A. The area of the first diffusion region 67n may be larger than that of the other n-type impurity regions 68bn to 68dn when viewed from a direction perpendicular to the semiconductor substrate 60. It is formed in a small area.

In addition, the areas of the first diffusion region 67n and the second diffusion region 68an described above may also be the reset transistor 26 in the first diffusion region 67n and the second diffusion region 68an when viewed from a direction perpendicular to the semiconductor substrate. The area of the portion where the gate electrode 26e overlaps. Similarly, the area of the other n-type impurity regions 68bn to 68dn may be the gate of the non-single-amplified transistor 22 in the other n-type impurity regions 68bn to 68dn when viewed from a direction perpendicular to the semiconductor substrate 60. The area of the portion where the electrode 22e and the gate electrode 24e of the address transistor 24 overlap. When viewed from a direction perpendicular to the semiconductor substrate 60, portions overlapping with the gate electrodes 22e, 24e, and 26e of these transistors are more difficult to withstand damage during manufacture than portions that do not overlap with the gate electrodes 22e, 24e, and 26e. . The damage during manufacturing is, for example, caused by the plasma treatment used in the dry etching process, or by the ashing treatment when the photoresist is peeled off. This makes it difficult for a leakage current to occur in the portions overlapping the gate electrodes 22e, 24e, and 26e. Therefore, in terms of making the area of the interface empty layer small, regarding the first diffusion region 67n and other n-type impurity regions 68bn to 68dn, the influence of the area of the portion that does not overlap with the gate electrode may also be considered.

In addition, by making the area of the first diffusion region 67n small, the distance between the contact hole h1 formed in the first diffusion region 67n and the gate electrode 26e is, for example, longer than the contact hole h2 formed in the second diffusion region 68an. The distance from the gate electrode 26e is small. That is, when viewed from a direction perpendicular to the semiconductor substrate 60, the distance between the connection portion of the contact plug cp1 and the first diffusion area 67n and the gate electrode 26e is greater than the connection of the contact plug cp2 and the second diffusion area 68an. Partly, the distance from the gate electrode 26e is small. As described above, since the first diffusion region 67n has a low impurity concentration, the resistance value is higher than that of the second diffusion region 68an. Therefore, by reducing the distance between the contact hole h1 and the gate electrode 26e, the current path in the first diffusion region 67n can be shortened, thereby reducing the resistance value in the first diffusion region 67n. Incidentally, the same is true for the other n-type impurity regions 68bn and 68dn, and the distance between the contact hole h1 formed in the first diffusion region 67n and the gate electrode 26e may also be greater than that formed in the n-type impurity regions 68bn and 68dn The distance between the contact holes h3 and h4 and the gate electrodes 22e and 24e is small. That is, when viewed from a direction perpendicular to the semiconductor substrate 60, the distance between the contact plug cp1 and the first diffusion region 67n and the gate electrode 26e may be greater than the contact plug cp3 and the n-type impurity region. The distance between the connection portion of 68bn and the gate electrode 22e is small. In addition, the distance between the contact plug cp1 and the first diffusion region 67n and the gate electrode 26e when viewed from a direction perpendicular to the semiconductor substrate 60 may be greater than the contact plug cp4 and the n-type impurity region 68dn. The distance between the connection portion and the gate electrode 24e is small.

(Modification 1) FIG. 5 is a diagram showing a circuit configuration of an imaging device 100B according to Modification 1 of this embodiment. The main difference between the pixel 10B shown in FIG. 5 and the pixel 10A shown in FIG. 2 is that the anti-burnout crystal 28 is formed on the semiconductor substrate 60. The following description focuses on the differences from the embodiment, and common points are omitted from detailed description.

As shown in FIG. 5, the charge accumulation node ND is electrically connected to the drain of the reset transistor 26, the gate of the amplifier transistor 22, the lower electrode of the photoelectric conversion unit 12, the source of the burn-in prevention transistor 28 and the gate. connection. Here, the drain of the reset transistor 26 is a first diffusion region 67n which is a charge accumulation region. The source of the anti-burnout transistor 28 is connected to a VDD wiring or a power supply line 41 dedicated to the anti-burnout transistor 28. Here, if excessive light enters the photoelectric conversion film 12b, the potential of the first diffusion region 67n may exceed VDD. The threshold voltage of the anti-burnout transistor 28 can be set to turn on when the potential of the first diffusion region 67n is equal to VDD, so that the excessive charge flows from the first diffusion region 67n to the power line 41. As a result, malfunctions such as burnout can be prevented.

FIG. 6 is a plan view showing a layout in a pixel 10B according to the first modification of the present embodiment. As shown in FIG. 6, the pixel 10B according to this modification further includes a third transistor (here, a burn-in prevention transistor 28) that is different from the first transistor (here, the reset transistor 26). The anti-burnout transistor 28 includes a gate electrode 28e, a source region, and a drain region. Here, the first diffusion region 67 n functions as a drain region of the anti-burnout transistor 28. Incidentally, the first diffusion region 67n also functions as the drain region of the reset transistor 26. As described above, in the two transistors described above, the first diffusion region 67n is shared as the drain region. The n-type impurity region 68en functions as a source region of the anti-burnout transistor 28.

Here, the concentration of the n-type impurity in the first diffusion region 67n may be smaller than the concentration of the n-type impurity in the n-type impurity region 68en. Accordingly, the concentration of the n-type impurities in the first diffusion region 67n is smaller than the concentration of the n-type impurities in the other n-type impurity regions 68bn to 68ec in the pixel 10B. Accordingly, since the junction concentration of the first diffusion region 67n and the semiconductor substrate 60 is small, leakage current can be reduced.

FIG. 7 is a schematic cross-sectional view of a device structure of a pixel according to this modification. As shown in FIG. 7, the gate electrode 28 e of the anti-burnout transistor 28 is formed on the semiconductor substrate 60 via a gate insulating film 70. The n-type impurity region 68 en is formed on the surface of the semiconductor substrate 60.

When excessive light enters the photoelectric conversion film 12b, the potential of the first diffusion region 67n rises to the same level as the bias voltage applied to the transparent electrode 12c. If such an overvoltage is applied to the first diffusion region 67n, the first diffusion region 67n may be destroyed or the gate insulating film 70 of the amplifier transistor 22 may be destroyed. As a result, malfunctions such as burning out occur.

On the other hand, according to this modification, dark current can be suppressed, and failure of each transistor due to overvoltage can be prevented even in the case where excessive light is incident.

(Modification 2) FIG. 8 is a plan view showing a layout within a pixel 10C of an imaging device 100C related to Modification 2 of this embodiment. This modification is different from the pixel 10A in that the first diffusion region (FD) 67n is circular when viewed from a direction perpendicular to the semiconductor substrate 60. The following description focuses on the differences from the embodiment, and common points are omitted from detailed description.

In this modification, as described above, when viewed from a direction perpendicular to the semiconductor substrate 60, the first diffusion region (FD) 67n is circular. Thereby, the area of the first diffusion region 67n on the surface of the semiconductor substrate 60 is smaller than that in the case of forming a rectangular shape. Therefore, on the surface of the semiconductor substrate 60, the area of the interstitial empty layer formed at the junction between the first diffusion region 67n and the semiconductor substrate 60 is small. This can reduce the leakage current in the joint portion.

Incidentally, although this modification example does not include the anti-burnout crystal 28 similarly to the imaging device 100A of the embodiment, it may have the anti-burnout crystal 28 like the imaging device 100B of the first modification. Thereby, even if excessive light enters the photoelectric conversion section 12, failure of each transistor due to overvoltage can be prevented. (Modification 3) FIG. 9 is a diagram showing a circuit configuration of a pixel 10D of an imaging device 100D according to Modification 3 of this embodiment. FIG. 10 is a plan view showing a layout in a pixel 10D according to this modification. Although the imaging device exemplified in the above embodiment and the modification example has a photoelectric conversion section using a photoelectric conversion film, the imaging device exemplified in this modification example uses a photoelectric diode as the photoelectric conversion section. As shown in FIGS. 9 and 10, the pixel 10D of this modification example includes a photodiode 13 and a transmission transistor 27. The photodiode 13 has an n-type impurity region 68fn and a pinning layer (not shown) located above the n-type impurity region 68fn. The pinned layer is a field of p-type impurities. The photodiode 13 generates a charge by photoelectrically converting light received during the exposure time. After the predetermined exposure time is over, a transmission signal for turning on the transmission transistor 27 is applied to the gate of the transmission transistor 27 through the transmission signal line 37. Thereby, the transmission transistor 27 is turned on, and the charge generated by the photodiode 13 is transferred to the charge storage node ND. The amplifier transistor 22 outputs a signal corresponding to the charge transferred to the charge accumulation node ND to a vertical signal line 35 (not shown). The signal output to the vertical signal line 35 is supplied to an AD conversion section (not shown) and AD converted. As shown in FIG. 10, the transmission transistor 27 includes the first diffusion region 67 n and the n-type impurity region 68 fn as a source and a drain. The transmission transistor 27 includes a gate electrode 27e. The transmission transistor 27 is shared with the reset transistor 26 by using the first diffusion region 67n as one of a source and a drain. In addition, as shown in FIG. 9, the charge accumulation node ND is electrically connected to the drain of the reset transistor 26, the gate of the amplifier transistor 22, and the source of the transmission transistor 27. Here, the drain of the reset transistor 26 in FIG. 10 is a first diffusion region 67n which is a charge accumulation region. In this modified example, similarly to the above-described embodiment and modified example, the pixel 10D has a first transistor (here, the reset transistor 26). The first transistor is located in the semiconductor substrate and contains n-type impurities. The first diffusion region 67n of the photocharge accumulation converted by the photodiode 13 is included as one of the source and the drain. The second diffusion region 68an, which is an n-type impurity region containing n-type impurities, is included as the other of the source and the drain. At this time, the concentration of the n-type impurity in the first diffusion region 67n is smaller than the concentration of the n-type impurity in the second diffusion region 68an. Thereby, since the joint concentration in the joint portion between the first diffusion region 67n and the semiconductor substrate is small, the leakage current in the first diffusion region 67n is reduced. In addition, the pixel 10D has a second transistor (here, the amplified transistor 22) different from the reset transistor 26. The second transistor is located in the semiconductor substrate 60 and includes a third diffusion region containing n-type impurities. (Hereinafter referred to as other n-type impurity regions 68bn and 68cn.) It is included as a source or a drain. At this time, the concentration of the n-type impurity in the first diffusion region 67n may be smaller than the concentration of the n-type impurity in the other n-type impurity regions 68bn and 68cn. At this time, the concentration of the n-type impurity in the first diffusion region 67n may be at least 1/10 smaller than the concentration of the n-type impurity in the second diffusion region 68an and other n-type impurity regions 68bn and 68cn, or may be greater than 1 / 15 small. Thereby, since the joint concentration in the joint portion between the first diffusion region 67n and the semiconductor substrate 60 is small, the electric field intensity at the joint portion can be relaxed. Therefore, the leakage current in the first diffusion region 67n which is itself a charge accumulation region or toward the first diffusion region 67n is reduced. In addition, the imaging device 100D related to this modification may be as follows: the semiconductor substrate 60 includes p-type impurities, the concentration of the n-type impurities included in the first diffusion region 67n, and the semiconductor substrate 60 is adjacent to the first diffusion region 67n. The concentration of the p-type impurity contained in the portion is 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁶ atoms / cm ³ or less. Thereby, the bonding density of the first diffusion region 67n and the semiconductor substrate 60 is small, and an increase in the electric field strength at the bonding portion can be suppressed. Therefore, it is possible to reduce the leakage current in the joint portion. In addition, if the area of an empty layer region (hereinafter referred to as an interface empty layer) formed at a junction portion on the surface of the semiconductor substrate 60 is increased, the leakage current is likely to increase. Therefore, it is desirable to minimize the area of the interface empty layer exposed on the surface of the semiconductor substrate 60. In order to make the area of the interface empty layer small, it may be formed in such a manner that the area of the first diffusion region 67n is smaller than that of the second diffusion region 68an when viewed from a direction perpendicular to the semiconductor substrate 60. For example, when viewed from a direction perpendicular to the semiconductor substrate 60, the area of the first diffusion area 67n is less than or equal to 1/2 of the area of the second diffusion area 68an. In this case, the width in the channel width direction of the first diffusion region 67n may be equal to or less than 1/2 of the width in the channel width direction of the second diffusion region 68an. Incidentally, the first diffusion area 67n and the second diffusion area 68an may be the same size as one of the width in the channel width direction and the length in the channel length direction. In addition, the other n-type impurity regions 68bn and 68cn in the pixel 10D are the same, and the area of the first diffusion region 67n when viewed from the direction perpendicular to the semiconductor substrate 60 may be larger than that of the other n-type impurity regions 68bn and 68cn. It is formed in a small area. In addition, the areas of the first diffusion region 67n and the second diffusion region 68an described above may also be the reset transistor 26 in the first diffusion region 67n and the second diffusion region 68an when viewed from a direction perpendicular to the semiconductor substrate. The area of the portion where the gate electrode 26e overlaps. Similarly, the area of the other n-type impurity regions 68bn and 68cn may also be the gate of the non-single-amplified transistor 22 in the other n-type impurity regions 68bn and 68cn when viewed from a direction perpendicular to the semiconductor substrate 60. The area of the portion where the electrode 22e overlaps. The portions overlapping the gate electrodes 22e and 26e of these transistors when viewed from a direction perpendicular to the semiconductor substrate 60 are more difficult to withstand damage during manufacture than the portions not overlapping the gate electrodes 22e and 26e. The damage during manufacturing is, for example, caused by the plasma treatment used in the dry etching process, or by the ashing treatment when the photoresist is peeled off. This makes it difficult for a leakage current to occur in the portions overlapping the gate electrodes 22e and 26e. Therefore, in terms of making the area of the interface depletion layer small, regarding the first diffusion region 67n and other n-type impurity regions 68bn and 68cn, the influence of the area of the portion that does not overlap the gate electrode may also be considered. In addition, by making the area of the first diffusion region 67n small, the distance between the contact hole h1 formed in the first diffusion region 67n and the gate electrode 26e is, for example, longer than the contact hole h2 formed in the second diffusion region 68an. The distance from the gate electrode 26e is small. As described above, since the first diffusion region 67n has a low impurity concentration, the resistance value is higher than that of the second diffusion region 68an. Therefore, by reducing the distance between the contact hole h1 and the gate electrode 26e, the current path in the first diffusion region 67n can be shortened, thereby reducing the resistance value in the first diffusion region 67n. Incidentally, the same is true for the other n-type impurity regions 68bn and 68cn. The distance between the contact hole h1 formed in the first diffusion region 67n and the gate electrode 26e may be greater than that formed in the n-type impurity regions 68bn and 68cn. The distance between the contact holes h3, h9 and the gate electrode 22e is small.

Although the imaging device related to the present disclosure has been described based on the embodiments and the modifications, the present disclosure is not limited to the embodiments and the modifications. As long as the subject matter of the present disclosure is not exceeded, other forms that can be conceived by the industry are various modifications to the implementation forms and modifications, and other forms constructed by combining the constituent elements of the implementation forms and the modifications are also included in the scope of this disclosure .

In addition, according to the embodiments and modifications of the present disclosure, the influence of leakage current can be reduced, and therefore, an imaging device capable of shooting with high image quality can be provided. Incidentally, the amplifying transistor 22, the address transistor 24, the reset transistor 26, and the anti-burnout transistor 28 may be N-channel MOS or P-channel MOS, respectively. When each transistor is a P-channel MOS, the impurity of the first conductivity type is a p-type impurity, and the impurity of the second conductivity type is an n-type impurity. It is not necessary to unify all the transistors with either N-channel MOS or P-channel MOS. When each transistor in the pixel is an N-channel MOS and uses electrons as signal charges, the source and drain configurations of the transistors of the transistors can also be exchanged with each other. Industrial availability

According to the present disclosure, it is possible to provide a photographing device capable of shooting with high image quality while suppressing the influence of dark current. The photographing device of the present disclosure is useful for an image sensor, a digital camera, and the like, for example. The imaging device of the present disclosure can be used for a medical camera, a robot camera, a surveillance camera, a camera mounted on a vehicle, and the like.

10A, 10B, 10C, 10D ‧‧‧ pixels

12‧‧‧Photoelectric Conversion Department

12a‧‧‧pixel electrode

12b‧‧‧photoelectric conversion layer

12c‧‧‧Transparent electrode

13‧‧‧photodiode

14‧‧‧Signal detection circuit

16‧‧‧Feedback circuit

22‧‧‧Amplifier transistor

22e, 24e, 26e, 27e, 28e‧‧‧Gate electrode

24‧‧‧Address Transistor

26‧‧‧Reset transistor

27‧‧‧Transistor

28‧‧‧Anti-burning transistor

32‧‧‧Power wiring

34‧‧‧Address signal line

35‧‧‧Vertical Signal Line

36‧‧‧Reset signal line

37‧‧‧Transmission signal line

39‧‧‧accumulation control line

40‧‧‧Peripheral circuit

41‧‧‧Power cord

42‧‧‧Load circuit

44‧‧‧column signal processing circuit

46‧‧‧Vertical Scan Circuit

48‧‧‧horizontal signal reading circuit

49‧‧‧horizontal communication line

50‧‧‧ Reverse Amplifier

53‧‧‧Feedback

60‧‧‧Semiconductor substrate

61‧‧‧Support substrate

61p, 63p, 65p‧‧‧p-type semiconductor layers

62n‧‧‧n-type semiconductor layer

64‧‧‧p-type field

66p‧‧‧p-type impurity field

67a‧‧‧The first area

67b‧‧‧Field 2

67n‧‧‧The first area of proliferation

68an‧‧‧The second area of proliferation

68bn, 68cn, 68dn, 68en, 68fn‧‧‧n type impurities

69‧‧‧Component separation field

70, 71, 72, 90a, 90b, 90c, 90d

80‧‧‧Wiring Structure

80a, 80b, 80c, 80d‧‧‧ wiring layer

90‧‧‧ interlayer insulation

100A, 100B, 100C, 100D‧‧‧ camera

ND‧‧‧charge accumulation node

R1‧‧‧Photography

R2‧‧‧Areas

cp1, cp2, cp3, cp4, cp5, cp6, cp7, cp8‧‧‧ contact plug

h1, h2, h3, h4, h5, h6, h7, h8, h9‧‧‧ contact holes

pa1, pa2, pb, pc, pd‧‧‧plug

Fig. 1 is a block diagram of a photographing device according to an embodiment. Fig. 2 is a diagram showing a circuit configuration of a photographing device according to an embodiment. Fig. 3 is a plan view showing a layout in a pixel according to the embodiment. Fig. 4 is a schematic cross-sectional view of a pixel device structure according to the embodiment. 5 is a diagram showing a circuit configuration of an imaging device according to Modification 1 of the embodiment. 6 is a plan view showing a layout in a pixel according to a first modification of the embodiment. Fig. 7 is a schematic cross-sectional view of a device structure of a pixel according to a first modification of the embodiment. 8 is a plan view showing a layout in a pixel according to Modification 2 of the embodiment. 9 is a diagram showing a circuit configuration of a pixel according to a third modification of the embodiment. 10 is a plan view showing a layout in a pixel according to a third modification of the embodiment.

Claims (9)

A photographing device includes a semiconductor substrate and a plurality of pixels. The semiconductor substrate includes a first diffusion region containing impurities of a first conductivity type and a second diffusion region containing impurities of a first conductivity type. Each of the plurality of pixels includes a A photoelectric conversion unit for converting light into electric charges; and a first transistor including a source electrode, a drain electrode, and a gate electrode, and including the first diffusion region as one of the source electrode and the drain electrode, The aforementioned second diffusion region is included as the other of the aforementioned source and drain, wherein the first diffusion region accumulates at least a portion of the aforementioned charge, and the impurities of the first conductivity type in the aforementioned first diffusion region The concentration is smaller than that of the first conductivity type impurity in the second diffusion region. When viewed from a direction perpendicular to the semiconductor substrate, the area of the first diffusion region is smaller than the area of the second diffusion region. . For example, the imaging device of claim 1, wherein the semiconductor substrate further includes a third diffusion region containing impurities of the first conductivity type, and each of the plurality of pixels includes a second transistor, and the second transistor treats the third diffusion region as Contained as one of the source and the drain, the concentration of impurities of the first conductivity type in the first diffusion region is smaller than the concentration of impurities of the first conductivity type in the third diffusion region. For example, the imaging device of claim 1, wherein each of the plurality of pixels includes a third transistor, and the third transistor includes the first diffusion region as one of a source and a drain. The imaging device of claim 1, wherein the area of the first diffusion area is an area of a portion of the first diffusion area that does not overlap the gate electrode when viewed from a direction perpendicular to the semiconductor substrate, and the second area The area of the diffusion area is an area of a portion of the second diffusion area that does not overlap the gate electrode when viewed from a direction perpendicular to the semiconductor substrate. For example, the imaging device of claim 1, wherein each of the plurality of pixels includes: a first plug connected to the first part of the first diffusion field; and a second plug connected to the second part of the second diffusion field. When viewed from a direction perpendicular to the semiconductor substrate, the distance between the first portion and the gate electrode is smaller than the distance between the second portion and the gate electrode. For example, the imaging device of claim 1, wherein the semiconductor substrate includes a fourth diffusion region, the fourth diffusion region contains impurities of a second conductivity type different from the first conductivity type, and each of the plurality of pixels includes other than the first transistor. The other transistor includes the fourth diffusion region as a separation region that separates the first transistor from the other transistor. The fourth diffusion region is on the surface of the semiconductor substrate and does not differ from the first transistor. Contact in the area of proliferation. For example, the imaging device of claim 1, wherein the semiconductor substrate contains impurities of a second conductivity type different from the first conductivity type, and the concentration of the impurities of the first conductivity type included in the first diffusion field is 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁶ atoms / cm ³ or less, the concentration of impurities of the second conductivity type included in the semiconductor substrate adjacent to the first diffusion region is 1 × 10 ¹⁶ atoms / cm ³ or more, 5 × 10 ¹⁶ atoms / cm ³ or less. The imaging device according to claim 1, wherein the first diffusion area is circular when viewed from a direction perpendicular to the semiconductor substrate. A photographing device includes a semiconductor substrate and a plurality of pixels. The semiconductor substrate includes a first diffusion region containing impurities of a first conductivity type and a second diffusion region containing impurities of a first conductivity type. Each of the plurality of pixels includes: A photoelectric conversion unit that converts light into an electric charge; and a first transistor including a source, a drain, and a gate electrode, and including the first diffusion region as one of the source and the drain, The foregoing second diffusion region is included as the other of the foregoing source and the drain, wherein the first diffusion region accumulates at least a portion of the charge; the first plug and the first portion of the first diffusion region And the second plug is connected to the second part of the second diffusion region, and the concentration of the impurity of the first conductivity type in the first diffusion region is higher than that of the impurity of the first conductivity type in the second diffusion region. The concentration is small. When viewed from a direction perpendicular to the semiconductor substrate, the distance between the first portion and the gate electrode is smaller than the distance between the second portion and the gate electrode.