TWI513011B - Differential varactor device - Google Patents

Description

Differential variable capacitance element

The present invention relates to a differential variable capacitance element.

In the modern information industry, various data, materials, messages, and images are transmitted in the form of electronic signals, and the processing circuits used to process electronic signals become the most important foundation in the modern information industry. The oscillator in the circuit is one of the important circuit building blocks in modern digital systems. For example, in a general information system (eg, a personal computer), a global clock is needed to coordinate the various digital circuits in the digital system, and the clock is generated by the oscillator. In addition, to coordinate different clock synchronization (such as in the communication system for transmitting signals), a phase loop lock (PLL) circuit is also required; in the phase-locked circuit, a precision voltage-controlled oscillator is required. -controlled oscillators (VCOs), which control the voltage-controlled oscillator to oscillate different oscillation signals with different voltages to coordinate the clock synchronization. In addition, as in some sophisticated filters, a resistor-capacitor (RC) filter that adjusts the filter frequency is required.

Whether it is the filter characteristics of a resistor-capacitor (RC) filter (such as the passband bandwidth of a filter) or the oscillatory characteristics of an inductor-capacitor (LC) voltage-controlled oscillator (like the frequency of a oscillating signal), It can be adjusted by changing the value of the capacitor. Therefore, a capacitor having an adjustable capacitance value, that is, a variable capacitance, has been used in an element having such characteristics. In the operating range of the variable capacitor, the capacitance value decreases with the voltage applied to it. A variety of variable capacitors have been developed for use in integrated circuit components, among which are PN junction varactors and metal-oxide semiconductor (MOS) variable capacitors. Most often it is common.

However, in the case of a MOS variable capacitor, the tuning ratio is defined as the ratio of the maximum capacitance to the minimum capacitance of the variable capacitor, which can only reach 3 at an operating frequency of 10 GHz. In other words, the range of variation of the MOS variable capacitance adjustable capacitance value is limited by its tuning ratio. In view of this, increasing the tuning ratio of the variable capacitor is an industry goal.

One of the main objects of the present invention is to provide a differential variable capacitance element to increase the tuning ratio.

To achieve the above objective, the present invention provides a differential variable capacitance element including a substrate, a well region, five first doped regions, four first insulating layers, and a first gate and a second gate. a third gate and a fourth gate. The substrate has a first conductivity type. The well zone is disposed in the substrate and the well zone has a second conductivity type. The fifth first doped regions are disposed in the well region and aligned along a first direction, and the first doped regions have a second conductivity type. The first insulating layer is disposed on the well region, and each of the first insulating layers is disposed between any two adjacent first doped regions. The first gate, the second gate, the third gate and the fourth gate are respectively disposed on the first insulating layers, and are sequentially arranged along the first direction.

To achieve the above objective, the present invention further provides a differential variable capacitance element including a substrate, a first well region and a second well region, three third doped regions, three fourth doped regions, and two a fourth insulating layer, a first gate and a second gate, and a third gate and a fourth gate. The substrate has a first conductivity type. The first well region and the second well region are disposed in the substrate and arranged along a first direction, and the first well region and the second well region have a second conductivity type. The third doped region is disposed in the first well region and arranged along the first direction, and the third doped region has the second conductivity type. The fourth doped region is disposed in the second well region and arranged along the first direction, and the fourth doped region has the second conductivity type. The third insulating layer is disposed on the first well region, and each of the third insulating layers is respectively located between any two adjacent third doped regions. The fourth insulating layer is disposed on the second well region, and each of the fourth insulating layers is respectively located between any two adjacent fourth doping regions. The first gate and the second gate are respectively disposed on the third insulating layers, and are sequentially arranged along the first direction. The third gate and the fourth gate are respectively disposed on the fourth insulating layers, and are sequentially arranged along the first direction.

To achieve the above object, the present invention further provides a differential variable capacitance element including a plurality of differential variable capacitance units. Each of the differential variable capacitor units has two gates respectively electrically connected to a first output end and a second output end, wherein the differential variable capacitor unit has a tuning ratio and the tuning ratio is greater than 4.

The differential variable capacitance element of the present invention is tuned by arranging gates electrically connected to different gate voltages in a first direction, and different differential variable capacitance units in the same well region. The ratio is greater than 4, which effectively increases its adjustable capacitance Wai.

Please refer to FIG. 1 to FIG. 3 . FIG. 1 is a top view of a differential variable capacitance element according to a first preferred embodiment of the present invention, and FIG. 2 is a cross-sectional line AA′ along FIG. 1 . A schematic cross-sectional view, and Fig. 3 is a schematic cross-sectional view taken along line BB' of Fig. 1. As shown in FIGS. 1 and 2, the differential variable capacitance element 100 is fabricated on a substrate 102, such as a germanium substrate, and the substrate 102 has a first conductivity type. Moreover, the differential variable capacitance element 100 includes a well region 104, five first doping regions 106, and four first gate structures 108. The well region 104 is disposed in the substrate 102 and has a second conductivity type that is different from the first conductivity type. The first doped regions 106 are disposed in the well region 104 and are aligned along a first direction 110, and the first doped regions 106 have a second conductivity type. In this embodiment, the first conductivity type is a P type, and the second conductivity type is an N type, but is not limited thereto, and the first conductive type and the second conductive type of the present invention may also be interchanged.

In the present embodiment, the first gate structures 108 are respectively disposed on the N-type well regions 104 between any two adjacent N-type first doping regions 106. The first gate structure 108 includes a first insulating layer 112, a gate, and two first sidewalls 116. The gates are respectively disposed on the first insulating layers 112, and the first sidewalls 116 are respectively It is disposed on each side of each gate and each of the first insulating layers 112. Only a single one of the gates is disposed between the two adjacent first doped regions 106 in the first direction 110. It can be seen that the N-type well region 104, any two adjacent N-type first doped regions 106, and the respective first gate structures 108 between any two adjacent N-type first doped regions 106 may constitute First variable electric The second pattern is a group of four, and the two adjacent first variable capacitors 117 share the same N-type first doping region 106. In addition, each of the gates of the present embodiment is composed of a polysilicon layer, but is not limited thereto, and the gate of the present invention may also be a metal gate.

In this embodiment, the gate of the first gate structure 108 can be divided into a first gate 114a, a second gate 114b, a third gate 114c and a fourth gate 114d, along the first The directions 110 are arranged in order. Moreover, the differential variable capacitance element 100 further includes a plurality of P-type doping regions 118, a plurality of contact plugs 120, a plurality of conductive layers, a first output terminal 122, a second output terminal 124, and a third output. End 126. The P-type doping region 118 is disposed in the P-type substrate 102 and is used to electrically connect the P-type substrate 102 to the outside. The contact plug 120, the conductive layer, the first output end 122, the second output end 124, and the third output end 126 are disposed on the P-type substrate 102, and the contact plugs 120 are respectively disposed in the P-type doping region 118, first The gate 114a, the second gate 114b, the third gate 114c, the fourth gate 114d, and a portion of the N-type first doping region 106. The conductive layer includes a first conductive layer 128a, a second conductive layer 128b, a third conductive layer 128c, and a fourth conductive layer 128d, respectively disposed on the first gate 114a, the second gate 114b, and the third gate. The first conductive layer 128a, the second conductive layer 128b, the third conductive layer 128c and the fourth conductive layer 128d are electrically connected to the first gate 114a by the contact plug 120, respectively. The second gate 114b, the third gate 114c and the fourth gate 114d. The first conductive layer 128a and the third conductive layer 128c are electrically connected to the first output end 122, so that the first gate 114a and the third gate 114c can pass through the first conductive layer 128a and the third conductive layer 128c. Electrically connecting to the corresponding contact plug 120 to the first output end The second conductive layer 128b and the fourth conductive layer 128d are electrically connected to the second output end 124, so that the second gate 114b and the fourth gate 114d can pass through the second conductive layer 128b and the fourth conductive layer. 128d and the corresponding contact plug 120 are electrically connected to the second output end 124. The N-type first doping region 106 can be electrically connected to the third output terminal 126 by the contact plug 120. For example, in the embodiment, the first gate electrode 114a and the second gate electrode 114b are located between the first gate electrode 114a and the second gate electrode 114b. The N-type first doping region 106 between the third gate 114c and the fourth gate 114d is in contact with the corresponding contact plug 120 and is electrically connected to the third output terminal 126. The first output terminal 122 and the second output terminal 124 can be respectively used as different gate outputs of the differential variable capacitance element 100 for electrically connecting to two different gate voltages, and the third output terminal 126 is used as a difference. The control terminal of the variable capacitance element 100 is electrically connected to a control voltage. Therefore, any two first variable capacitors 117 electrically connected to different gate voltages may constitute a first differential variable varactor unit 119, wherein a first differential variable capacitor unit 119 is only The first gate variable 114a and the second gate 114b have the third gate 114c and the fourth gate 114d, and the differential variable capacitance element 100 of the present embodiment There is two first differential variable capacitance units 119 arranged in parallel with each other and arranged along the first direction 100. In other embodiments of the present invention, the differential variable capacitance element 100 further includes a fourth output terminal electrically connected to the P-type doping region 118 by the contact plug 120 for use as the P-type substrate 102. The output. Moreover, the manner in which the first gate 114a and the third gate 114b of the present invention are electrically connected to the first output terminal 122, and the second gate 114b and the fourth gate 114d are electrically connected to the second output terminal 124, The manner in which the N-type first doping region 106 is electrically connected to the third output terminal 126 and the P-type doping region 118 are electrically connected to the fourth output terminal is not limited to the above manner, and other gold may be utilized. It is achieved by an internal wiring or a buried line structure.

As shown in FIG. 3, the differential variable capacitance element 100 further includes four second gate structures 130 and five N-type second doping regions 132, wherein the second gate structure 130 is disposed adjacent to the first gate. The N-type well region 104 of the pole structure 108 is located between any two adjacent N-type second doping regions 132, and the second gate structure 130 and the first gate structure 108 are along a second direction. 134 arranged. Each of the second gate structures 130 includes a second insulating layer 136, a gate, and two second sidewalls 138. The gates are respectively disposed on the second insulating layers 136, and the second sidewalls 138 are respectively disposed on the second gate layer 138. Each of the gates and each of the second insulating layers 136 are on both sides. Therefore, the N-type well region 104, any two adjacent N-type second doped regions 132, and each of the second gate structures 130 between any two adjacent N-type second doped regions 132 may constitute a first Two variable capacitors 139, and two adjacent second variable capacitors share the same N-type second doping region 132. In this embodiment, the gate of the second gate structure 130 can be divided into a fifth gate 140a, a sixth gate 140b, a seventh gate 140c and an eighth gate 140d. The fifth gate 140a, the sixth gate 140b, the seventh gate 140c, and the eighth gate 140d are sequentially arranged along the first direction 110. The conductive layer further includes a fifth conductive layer 128e, a sixth conductive layer 128f, a seventh conductive layer 128g, and an eighth conductive layer 128h, respectively disposed on the fifth gate 140a and the sixth gate 140b. The seventh gate 140c and the eighth gate 140d, and the fifth conductive layer 128e, the sixth conductive layer 128f, the seventh conductive layer 128g and the eighth conductive layer 128h are respectively electrically connected by the corresponding contact plugs 120. The five gates 140a, the sixth gate 140b, the seventh gate 140c, and the eighth gate 140d. In addition, the fifth conductive layer 128e and the seventh conductive layer 128g are electrically connected to the first output end 122, so that the fifth gate 140a and the seventh gate 140c can be borrowed. The fifth conductive layer 128e, the seventh conductive layer 128g and the corresponding contact plug 120 are electrically connected to the first output end 122, and the sixth conductive layer 128f and the eighth conductive layer 128h are electrically connected to the second output. The second terminal 140b and the eighth gate 140d are electrically connected to the second output end 124 by the sixth conductive layer 128f, the eighth conductive layer 128h and the corresponding contact plug 120. An N-type second doping region 132 between the fifth gate 140a and the sixth gate 140b and between the seventh gate 140c and the eighth gate 140d is in contact with the corresponding contact plug 120. It is electrically connected to the third output terminal 126.

Therefore, it can be seen that any two second variable capacitors 139 electrically connected to different gate voltages can constitute a second differential variable capacitance unit 141, and the differential variable capacitance element 100 of the embodiment has two A second differential variable capacitance unit 141 that is parallel to each other and arranged along the first direction 110. The first gate 114a and the third gate 114c of the first differential variable capacitor unit 119 are connected in parallel with the fifth gate 140a and the seventh gate 140c of the second differential variable capacitor unit 141. The output terminal 122, and the second gate 114b and the fourth gate 114d of the first differential variable capacitor unit 119 and the sixth gate 140b of the second differential variable capacitor unit 141 are connected in parallel with the eighth gate 140d to The second output terminal 124, and the first differential variable capacitor unit 119 and the second differential variable capacitor unit 141 are arranged along the second direction 134 on the same N-type well region 104, so that the first differential variable The capacitor unit 119 and the second differential variable capacitor unit 141 are connected to each other in parallel. It should be noted that the differential variable capacitance element 100 of the present embodiment has the gates electrically connected to different gate voltages staggered along the first direction 110, and the first differential variable capacitance unit 119 is different. And the second differential variable capacitor unit 141 is disposed in the same N-type well region 104, The tuning ratio of the differential variable capacitance element 100 is made greater than 4 to effectively increase its adjustable capacitance range.

In other embodiments of the present invention, the differential variable capacitance element 100 may also have a plurality of first differential variable capacitance units 119 arranged along the first direction 110. Further, the differential variable capacitance element 100 may have a plurality of second differential variable capacitance units 141 arranged along the first direction 110. In addition, the differential variable capacitance element 100 of the present invention is not limited to having only the first differential variable capacitance unit 119 and the second differential variable capacitance unit 141 arranged in the second direction 134, and may have a plurality of differentials. The variable capacitance units are arranged in the second direction 134.

The differential variable capacitance element of the present invention is not limited to the above embodiment. The other embodiments and variations of the present invention are described in the following, and the same reference numerals will be used to refer to the same elements, and the repeated parts will not be described again.

Please refer to FIG. 4, which is a top view of another variation of the differential variable capacitance element according to the first preferred embodiment of the present invention. As shown in FIG. 4, compared with the above embodiment, the N-type second doping region 132 of the modified shape may be a portion of the extended N-type first doping region 106, so the second gate structure 130 is respectively disposed on Between two adjacent N-type first doped regions 106.

Please refer to FIG. 5, which is a differential variable power according to a second preferred embodiment of the present invention. The top view of the component is shown. As shown in FIG. 5, in the differential variable capacitance element 200 of the present embodiment, the fifth conductive layer 128e and the seventh conductive layer 128g are electrically connected to the second output end 124. The fifth gate 140a and the seventh gate 140c are electrically connected to the second output terminal 124, and the sixth conductive layer 128f and the eighth conductive layer 128h are electrically connected to the first output terminal 122, so that the sixth gate The pole 140b and the eighth gate 140d are electrically connected to the first output end 122.

Please refer to FIG. 6. FIG. 6 is a top view of a differential variable capacitance element according to a third preferred embodiment of the present invention. As shown in FIG. 6, in the differential variable capacitance element 250 of the present embodiment, the first conductive layer 128a, the second conductive layer 128b, the fifth conductive layer 128e, and the sixth conductive portion are compared with the first embodiment. The layer 128f is electrically connected to the first output end 122, and electrically connects the first gate 114a, the second gate 114b, the fifth gate 140a and the sixth gate 140b to the first output terminal 122, and the third The conductive layer 128c, the fourth conductive layer 128d, the seventh conductive layer 128g and the eighth conductive layer 128h are electrically connected to the second output terminal 124, so that the third gate 114c, the fourth gate 114d, and the seventh gate 140c The eighth gate 140d is electrically connected to the second output terminal 124. In this embodiment, the adjacent first gate 114a and second gate 114b and the adjacent fifth gate 140a and sixth gate 140b are electrically connected to the same first output terminal 122, and the phase The adjacent third gate 114c and the fourth gate 114d and the adjacent seventh gate 140c and the eighth gate 140d are electrically connected to the same second output terminal 124 to be electrically connected to the first output end. The first gate 114a and the second gate 114b of the second gate 114b and the third gate 114c and the fourth gate 114d electrically connected to the second output terminal 124 are arranged in the first direction 110 in a staggered manner. Similarly, the fifth gate 140a and the first electrode electrically connected to the first output terminal 122 The sixth gate 140b and the seventh gate 140c and the eighth gate 140d electrically connected to the second output terminal 124 are also arranged in the first direction 110 in a staggered manner.

Please refer to FIG. 7 to FIG. 9 . FIG. 7 is a top view of a differential variable capacitance element according to a fourth preferred embodiment of the present invention, and FIG. 8 is a cross-sectional line CC′ along FIG. 7 . A schematic cross-sectional view, and Fig. 9 is a schematic cross-sectional view taken along line DD' of Fig. 7. As shown in FIGS. 7 and 8, the differential variable capacitance units of the differential variable capacitance element 300 of the present embodiment are respectively disposed in different well regions as compared with the first embodiment. The differential variable capacitance element 300 of the present embodiment includes an N-type first well region 302, an N-type second well region 304, a three-N-type third doping region 306, and a three-N-type fourth doping region 308. Two third gate structures 310 and two fourth gate structures 312. The N-type first well region 302 and the N-type second well region 304 are disposed in the P-type substrate 102 and are arranged along the first direction 110. N-type third doped regions 306 are disposed in the N-type first well region 302 and are aligned along the first direction 110. The N-type fourth doped regions 308 are disposed in the N-type second well region 304 and are aligned along the first direction 110.

Moreover, each of the third gate structures 310 is disposed on the N-type first well region 302 and is respectively located between any two adjacent N-type third doping regions 306. Each of the third gate structures 310 includes a third insulating layer 314, a gate, and two third sidewalls 316. The gates are respectively disposed on the third insulating layers 314, and the third sidewalls 316 are respectively disposed on the third gate layer 316. Each of the gates and each of the third insulating layers 314 are on both sides. In addition, the gate of the third gate structure 310 can be divided into a first gate 318a and a second gate 318b, which are electrically connected to the first output terminal 122 and the second output terminal 124, respectively. Only two adjacent N-type third doping regions 306 are disposed between There is a single one of the first gate 318a and the second gate 318b. Moreover, the N-type first well region 302 is electrically connected to the third output terminal 126 by an N-type third doping region 306 between the first gate 318a and the second gate 318b. Thereby, the N-type first well region 302, the N-type third doping region 306, and the third gate structure 310 can constitute a third differential variable capacitance unit 319.

Each of the fourth gate structures 312 is disposed on the N-type second well region 304 and is respectively located between any two adjacent N-type fourth doped regions 308. Each of the fourth gate structures 312 includes a fourth insulating layer 320, a gate, and two fourth sidewalls 322. The gates are respectively disposed on the fourth insulating layers 320, and the fourth sidewalls 322 are respectively disposed on the fourth gate layer 322. Each of the gates and each of the fourth insulating layers 320 are on both sides. In addition, the gate of the fourth gate structure 312 can be divided into a third gate 324a and a fourth gate 324b, and the first gate 318a, the second gate 318b, the third gate 324a and the fourth gate 324b Arranged in the first direction 110 in sequence. Only one of the third gate 324a and the fourth gate 324b is disposed between the two adjacent N-type fourth doping regions 308. The third gate 324a is electrically connected to the first output terminal 122, and the fourth gate 324b is electrically connected to the second output terminal 124. Moreover, the N-type second well region 304 is electrically connected to the third output terminal 126 by an N-type fourth doping region 308 between the third gate 324a and the fourth gate 324b. Thereby, the N-type second well region 304, the N-type fourth doping region 308, and the fourth gate structure 312 can constitute a fourth differential variable capacitance unit 325.

In addition, as shown in FIG. 9, the differential variable capacitance element 300 of the present embodiment further includes an N-type third well region 326, an N-type fourth well region 328, and a three-N-type fifth doping region 330. Three N-type sixth doped regions 332, two fifth gate structures 334, and two sixth gate structures 336. The N-type third well region 326 and the N-type fourth well region 328 are disposed in the P-type substrate 102 and are arranged along the first direction 110. The N-type fifth doped regions 330 are disposed in the N-type third well region 326 and are aligned along the first direction 110. The N-type sixth doped regions 332 are disposed in the N-type fourth well region 328 and are aligned along the first direction 110. The fifth gate structure 334 is disposed on the N-type third well region 326 and is respectively located between any two adjacent N-type fifth doping regions 330 and along the third gate structure 310 along the second direction 134. arrangement. Each of the fifth gate structures 334 includes a fifth insulating layer 338 and a gate disposed on the fifth insulating layer 338. Moreover, the gate of the fifth gate structure 334 can be divided into a fifth gate 340a and a sixth gate 340b. The sixth gate structure 336 is disposed on the N-type fourth well region 328 and is respectively located between any two adjacent N-type sixth doping regions 332 and along the fourth gate structure 312 along the second direction 134. arrangement. Each of the sixth gate structures 336 includes a sixth insulating layer 342 and a gate disposed on the sixth insulating layer 342. Moreover, the gate of the sixth gate structure 336 can be divided into a seventh gate 344a and an eighth gate 344b. The fifth gate 340a, the sixth gate 340b, the seventh gate 344a, and the eighth gate 344b are sequentially arranged along the first direction 110. In this embodiment, the fifth gate 340a and the seventh gate 344a are electrically connected to the first output end 122, and the sixth gate 340b and the eighth gate 344b are electrically connected to the second output end 124. Moreover, the N-type third well region 326 and the N-type fourth well region 328 are respectively disposed by the N-type fifth doping region 330 between the fifth gate 340a and the sixth gate 340b and at the seventh gate 344a. The N-type sixth doping region 332 between the eighth gate 344b and the eighth gate 344b is electrically connected to the third output terminal 126. Thereby, the N-type third well region 326, the N-type fifth doping region 330, and the fifth gate structure 334 can constitute a fifth differential variable capacitance unit 345, and the N-type fourth well region 328, N-type Sixth doping region 332 And the sixth gate structure 336 can constitute a sixth differential variable capacitance unit 346.

Please refer to FIG. 10 and FIG. 11 , FIG. 10 is a top view of a differential variable capacitance element according to a fifth preferred embodiment of the present invention, and FIG. 11 is a sixth preferred embodiment of the present invention. The top view of the differential variable capacitance element is shown. As shown in FIG. 10, the fifth conductive layer 128e and the seventh conductive layer 128g are electrically connected to the second output end 124, so that the fifth gate 340a and the seventh gate 344a are The second conductive layer 128f is electrically connected to the first output end 122, and the sixth gate 340b and the eighth gate 344b are electrically connected to the sixth gate 344b. The first output terminal 122. As shown in FIG. 11 , the first conductive layer 128 a , the second conductive layer 128 b , the fifth conductive layer 128 e and the sixth conductive layer 128 f are electrically connected to the first output end 122 , so that The first gate 318a, the second gate 318b, the fifth gate 340a and the sixth gate 340b are electrically connected to the first output end 122, and the third conductive layer 128c, the fourth conductive layer 128d, and the seventh conductive layer 128g and the eighth conductive layer 128h are electrically connected to the second output end 124, and the third gate 324a, the fourth gate 324b, the seventh gate 344a and the eighth gate 344b are electrically connected to the second output end. 124.

The effects of the differential variable capacitance element of each of the preferred embodiments of the present invention will be further described below. Please refer to Table 1. Table 1 series shows the maximum capacitance value and minimum capacitance value of the differential variable element of each embodiment when the differential variable capacitance element operates at an operating frequency of 10 GHz, and the tuning ratio thereof, that is, the maximum capacitance value and the minimum capacitance. The ratio of values. As shown in Table 1, when two gates electrically connected to one gate voltage and two gates electrically connected to another gate voltage are staggered in the first direction, the differential variable capacitor Component The tuning ratio can be greater than 3.68. The gates electrically connected to different gate voltages are staggered along the first direction, and at the same time, different differential variable capacitor units are disposed in different N-type well regions, and the tuning ratio of the differential variable capacitance elements is Greater than 4.13. Moreover, the gates electrically connected to different gate voltages are staggered along the first direction, and at the same time, different differential variable capacitor units are disposed in the same N-type well region, and the tuning ratio of the differential variable capacitance component is The system is greater than 4.83. Therefore, the differential variable capacitance element of the present invention can effectively increase the tuning ratio and increase the adjustable capacitance range of the differential variable capacitance element.

In summary, the differential variable capacitance device of the present invention is staggered in one direction by gates electrically connected to different gate voltages, and different differential variable capacitance units are disposed in the same well region. In the middle, the tuning ratio is greater than 4, thereby effectively increasing the adjustable capacitance range.

The above description is only a preferred embodiment of the present invention, and the patent application scope according to the present invention Equivalent changes and modifications made are intended to be within the scope of the present invention.

100‧‧‧Differential variable capacitance element

102‧‧‧Base

104‧‧‧ Well Area

106‧‧‧First doped area

108‧‧‧First gate structure

110‧‧‧First direction

112‧‧‧First insulation

114a‧‧‧first gate

114b‧‧‧second gate

114c‧‧‧third gate

114d‧‧‧fourth gate

116‧‧‧First side wall

117‧‧‧First variable capacitor

118‧‧‧Doped area

119‧‧‧First Differential Variable Capacitor Unit

120‧‧‧Contact plug

122‧‧‧ first output

124‧‧‧second output

126‧‧‧ third output

128a‧‧‧First conductive layer

128b‧‧‧Second conductive layer

128c‧‧‧ third conductive layer

128d‧‧‧fourth conductive layer

128e‧‧‧ fifth conductive layer

128f‧‧‧ sixth conductive layer

128g‧‧‧ seventh conductive layer

128h‧‧‧8th conductive layer

130‧‧‧Second gate structure

132‧‧‧Second doped area

134‧‧‧second direction

136‧‧‧Second insulation

138‧‧‧Second side wall

139‧‧‧Second variable capacitor

140a‧‧‧ fifth gate

140b‧‧‧ sixth gate

140c‧‧‧ seventh gate

140d‧‧‧eightth gate

141‧‧‧Second differential variable capacitor unit

200‧‧‧Differential variable capacitance element

250‧‧‧Differential variable capacitance components

300‧‧‧Differential variable capacitance components

302‧‧‧First Well Area

304‧‧‧Second well area

306‧‧‧ Third doped area

308‧‧‧fourth doping zone

310‧‧‧ Third Gate Structure

312‧‧‧fourth gate structure

314‧‧‧ Third insulation layer

316‧‧‧ third side wall

318a‧‧‧first gate

318b‧‧‧second gate

319‧‧‧3rd differential variable capacitor unit

320‧‧‧fourth insulation

322‧‧‧fourth side wall

324a‧‧‧third gate

324b‧‧‧fourth gate

325‧‧‧fourth differential variable capacitor unit

326‧‧‧ Third Well Area

328‧‧‧Four Well Area

330‧‧‧ fifth doping area

332‧‧‧ sixth doping area

334‧‧‧ fifth gate structure

336‧‧‧ sixth gate structure

338‧‧‧ fifth insulation

340a‧‧‧ fifth gate

340b‧‧‧ sixth gate

342‧‧‧ sixth insulation layer

344a‧‧‧ seventh gate

344b‧‧‧ eighth gate

345‧‧‧ fifth differential variable capacitor unit

346‧‧‧ sixth differential variable capacitor unit

Fig. 1 is a top plan view showing a differential variable capacitance element according to a first preferred embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view taken along line AA' of Fig. 1.

Fig. 3 is a schematic cross-sectional view taken along line BB' of Fig. 1.

Fig. 4 is a top plan view showing another variation of the differential variable capacitance element according to the first preferred embodiment of the present invention.

Figure 5 is a top plan view of a differential variable capacitance element according to a second preferred embodiment of the present invention.

Figure 6 is a top plan view of a differential variable capacitance element according to a third preferred embodiment of the present invention.

Figure 7 is a top plan view of a differential variable capacitance element according to a fourth preferred embodiment of the present invention.

Fig. 8 is a schematic cross-sectional view taken along line CC' of Fig. 7.

Fig. 9 is a schematic cross-sectional view taken along line DD' of Fig. 7.

Figure 10 is a top plan view of a differential variable capacitance element according to a fifth preferred embodiment of the present invention.

Figure 11 is a top plan view of a differential variable capacitance element according to a sixth preferred embodiment of the present invention.

102. . . Base

104. . . Well area

106. . . First doped region

108. . . First gate structure

112. . . First insulating layer

114a. . . First gate

114b. . . Second gate

114c. . . Third gate

114d. . . Fourth gate

116. . . First side wall

117. . . First variable capacitor

118. . . Doped region

119. . . First differential variable capacitance unit

120. . . Contact plug

128a. . . First conductive layer

128b. . . Second conductive layer

128c. . . Third conductive layer

128d. . . Fourth conductive layer

Claims (22)

A differential variable capacitance element comprising: a substrate having a first conductivity type; a well region disposed in the substrate, the well region having a second conductivity type; and a first doped region disposed on The first well region has a second conductivity type; and the fourth gate is a first gate, a second gate, and a first a third gate and a fourth gate, wherein the first gate, the second gate, the third gate and the fourth gate are respectively disposed between any two adjacent first doped regions And in the first direction along the first direction, wherein only one of the gates is disposed between the two adjacent first doped regions in the first direction By. The differential variable capacitance element of claim 1, wherein the first gate and the third gate are electrically connected to a first output terminal, and the second gate and the fourth gate are electrically connected Connected to a second output. The differential variable capacitance element according to claim 2, further comprising: a fifth gate, a sixth gate, a seventh gate and an eighth gate, which are disposed on the well region and along The first direction is sequentially arranged, and the fifth gate, the sixth gate, the seventh gate, and the eighth gate are respectively associated with the first gate, the second gate, and the third The gate and the fourth gate are arranged along a second direction. The differential variable capacitance element according to claim 3, wherein the fifth gate and the seventh The gate is electrically connected to the first output end, and the sixth gate and the eighth gate are electrically connected to the second output end. The differential variable capacitance element of claim 3, wherein the fifth gate and the seventh gate are electrically connected to the second output terminal, and the sixth gate and the eighth gate are electrically connected Connected to the first output. The differential variable capacitance element according to claim 3, wherein the fifth gate, the sixth gate, the seventh gate, and the eighth gate are respectively disposed adjacent to any two of the first Between the doped regions. The differential variable capacitance element according to claim 3, further comprising five second doped regions disposed in the well region, wherein the second doped regions have the second conductivity type, wherein the fifth gate The sixth gate, the seventh gate and the eighth gate are respectively disposed between any two adjacent second doped regions. The differential variable capacitance element of claim 7, wherein the second doping between the fifth gate and the sixth gate and between the seventh gate and the eighth gate The inter-cell is electrically connected to a third output. The differential variable capacitance device of claim 1, wherein the first gate and the second gate are electrically connected to a first output terminal, and the third gate and the fourth gate are electrically connected Connected to a second output. The differential variable capacitance element of claim 1, wherein the first doping between the first gate and the second gate and between the third gate and the fourth gate The inter-cell is electrically connected to a third output. The differential variable capacitance device of claim 1, wherein the first gate, the second gate, the third gate, and the fourth gate are respectively formed of a polysilicon layer. A differential variable capacitance element includes: a substrate having a first conductivity type; a first well region and a second well region disposed in the substrate and sequentially arranged along a first direction, and The first well region and the second well region have a second conductivity type; three third doped regions are disposed in the first well region and arranged along the first direction, and the third doping The region has the second conductivity type; the third and fourth doped regions are disposed in the second well region and arranged along the first direction, and the fourth doped regions have the second conductivity type; a gate and a second gate are disposed on the first well region and are respectively located between the two adjacent third doped regions, and are sequentially arranged along the first direction, wherein the two phases are Between the adjacent third doped regions, only one of the first gate and the second gate is disposed; and a third gate and a fourth gate are disposed in the second well region Up, and respectively located between any two adjacent fourth doped regions, and sequentially arranged along the first direction, wherein two adjacent fourth doped regions are between The third gate is provided with the One of the fourth gates is single. The differential variable capacitance device of claim 12, wherein the first gate and the third gate are electrically connected to a first output terminal, and the second gate and the fourth gate are electrically connected Connected to a second output. The differential variable capacitance element of claim 13, further comprising: a third well region and a fourth well region disposed in the substrate and sequentially arranged along the first direction, and the third The well region and the fourth well region have the second conductivity type; the third fifth doping region is disposed in the third well region and arranged along the first direction, and the fifth doped region has the a second conductivity type; three sixth doped regions disposed in the fourth well region and arranged along the first direction, and the sixth doped regions have the second conductivity type; a fifth gate And a sixth gate disposed on the third well region and respectively located between any two adjacent fifth doped regions and arranged along the first direction; and a seventh gate An eighth gate is disposed on the fourth well region and is respectively located between any two adjacent sixth doped regions and arranged along the first direction. The differential variable capacitance element of claim 14, wherein the fifth gate and the seventh gate are electrically connected to the first output terminal, and the sixth gate and the eighth gate are electrically connected Connected to the second output. The differential variable capacitance element according to claim 14, wherein the fifth gate and the first The seventh gate is electrically connected to the second output end, and the sixth gate and the eighth gate are electrically connected to the first output end. The differential variable capacitance element of claim 14, wherein the first well region, the second well region, the third well region, and the fourth well region are electrically connected to a third output terminal. The differential variable capacitance device of claim 12, wherein the first gate and the second gate are electrically connected to a first output terminal, and the third gate and the fourth gate are electrically connected Connected to a second output. A differential variable capacitance element includes: a plurality of differential variable capacitance units, each of the differential variable capacitance units having only a first gate and a second gate, and the first gates are electrically Connected to a first output terminal, the second gates are electrically connected to a second output terminal, wherein the differential variable capacitance elements have a tuning ratio, and the tuning ratio is greater than 4. The differential variable capacitance element according to claim 19, further comprising a well region, and the differential variable capacitance unit is disposed on the well region. The differential variable capacitance element according to claim 19, further comprising a plurality of well regions, and each of the differential variable capacitance units is disposed on each of the well regions. The differential variable capacitance element of claim 19, wherein the first is electrically connected to the first Each of the gates of the output terminal and the gates electrically connected to the second output terminal are staggered in a direction.