TW200532813A - Varactor and differential varactor - Google Patents

Abstract

A varactor is provided. The varactor is consisted of a second type substrate, two gate structures, a first type doped region and a second type doped region. These two gate structures having a gate dielectric layer and a gate conductive layer are located on the substrate. The first type doped region is located in the substrate between these two gate structures. The second type doped region is located in the substrate on the other side of the gate structure without the first type doped region. Wherein the first type doped region is electrically connected to a first electrode, the second type doped region is electrically connected to a second electrode, and these two gate structure is electrically connected to the first electrode or the second electrode. Since the varactor includes structures of a MOS varactor and a junction varactor, it has character of these two varactors.

Description

200532813 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a variable capacitor (varact 0r), and in particular to a variable capacitor and a capacitor whose capacitance and voltage have a large modulation range Dynamic variable capacitor (Differential Varactor). Prior technology In a typical communication system, information signals (such as TV programs) are modulated (T u n e) and placed on a high-frequency carrier to facilitate signal transmission. With the characteristics of different carrier signals at different frequencies, many information signals are transmitted at the same time. Therefore, the receiver in the communication system needs to use a Voltage Controlled Oscillator (V C 0) to separate the information signal from the carrier. V C 0 includes an LC (Inductive Capacitance) circuit composed of a variable capacitor and an inductor. By changing the capacitance of the variable capacitor with the voltage modulation, the oscillation frequency of VC0 can be changed accordingly. Common variable capacitors include MOS variable capacitors based on a Metal-Oxide Semiconductor Transistor (MOS) structure, and a junction formed by staggering p-type doped regions and n-type doped regions. Junction variable capacitor. Among them, although the capacitance of M0S variable capacitor has a large modulation range ((maximum capacitance-minimum capacitance) / minimum capacitance), but this modulation range only falls within a small voltage modulation range (about 1 V). That is, a small voltage modulation will cause a large change in capacitance. However, although the capacitance of the M0S variable capacitor has a large modulation range, the voltage modulation range is too small, which has the disadvantage of being difficult to control the capacitance modulation. On the other hand, the junction type can be

12868TWF.PTD Page 6 200532813 V. Description of the invention (2) Although the voltage of the transformer has a large modulation range (greater than 2 V), the capacitance modulation range corresponding to this modulation range is not large enough, so This makes the connection type variable capacitor limited in use. Moreover, for a differential variable capacitor obtained by applying the above-mentioned variable capacitor, the above-mentioned problems may cause the quality factor (Q-F act 〇) of the differential variable capacitor itself to be poor, thereby affecting its quality. Problems with charge storage capacity. Therefore, it is necessary to develop a variable capacitor having a wide range of modulation voltage and a wide range of modulation capacitance characteristics. SUMMARY OF THE INVENTION In view of this, an object of the present invention is to provide a variable capacitor to solve the problem that the conventional variable capacitor does not have a sufficiently large modulation range of its capacitance or voltage. Another object of the present invention is to provide a differential variable capacitor to improve the quality factor of the differential variable capacitor. The present invention provides a variable capacitor. The variable capacitor includes a second type substrate, two gate structures, a first type doped region and a second type doped region. The two gate structures are arranged on a second type substrate, and each gate structure is composed of a lower gate dielectric layer and an upper gate conductive layer. In addition, a first-type doped region is disposed in a second-type substrate between the two gate structures. In addition, the second-type doped region is disposed in a second-type substrate on the other side of the two gate structures where the first-type doped region is not disposed. The first type doped region is electrically connected to the first electrode terminal, and the second type doped region is electrically connected to the second electrode terminal, and the two gate structures are connected to the first electrode terminal or Second electricity

12868TWF.PTD Page 7 200532813 V. Description of the invention (3) Extreme electrical connection. The present invention provides a differential variable capacitor. The differential variable capacitor is composed of at least one pair of variable capacitors arranged on a second type substrate. Each pair of variable capacitors includes a first variable capacitor. A capacitor and a second variable capacitor. The first variable capacitor system includes two first gate structures, a first type first doped region and a second type first doped region, and the second variable capacitor system is adjacent to the first variable capacitor. The second variable capacitor includes two second gate structures, a first type second doped region and a second type second doped region. The two first gate structures described above are arranged on a second type substrate, and each of the first gate structures is composed of a lower first dielectric layer and an upper first conductive layer. In addition, a first-type first doped region is disposed in a second-type substrate between the two first gate structures. In addition, a second-type first doped region is disposed in a second-type substrate on the other side of the two first gate structures where the first-type first doped region is not disposed. In addition, the above-mentioned two second gate structures are arranged on a second type substrate, and each of the second gate structures is composed of a lower gate dielectric layer and an upper gate conductive layer. In addition, a first-type second doped region is disposed in the second-type substrate between the two second gate structures. In addition, the second-type second doped region is disposed in the second-type substrate on the other side of the two second gate structures where the first-type second doped region is not disposed, and is the same as the second-type first The doped regions are adjacent. Moreover, the first gate structure and the first type first doped region are electrically connected to a modulation voltage terminal, and the second gate structure and the first type second doped region are electrically connected to a relative modulation Voltage terminal, and second type first doped region and second type

12868TWF.PTD Page 8 200532813 V. Description of the invention (4) The second doped region is grounded. Because the variable capacitor or the differential variable capacitor of the present invention includes a MOS variable capacitor mainly composed of a gate structure, and a junction mainly composed of a first type doped region and a second type doped region Variable capacitors, so this variable capacitor or differential variable capacitor has the characteristics of both types of variable capacitors, so its capacitance and voltage have a large modulation range. Also, the quality factor of the differential variable capacitor can be improved. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings, as follows. Embodiments In the following examples, the present invention will be described with the first type being a P-type doped type and the second type being an n-type doped type. However, those skilled in the art can easily infer that the doping patterns of the first type and the second type can be exchanged with each other. Therefore, other embodiments that are opposite to the doping patterns of the following embodiments are omitted from description. In addition, in the following embodiments, the present invention will be described using the first electrode terminal as an anode and the second electrode terminal as a cathode. Similarly, those skilled in the art can also easily infer that the electrodes of the first electrode terminal and the second electrode terminal can also be exchanged with each other. Therefore, the description of other embodiments opposite to the electrodes of the following embodiments is omitted. First Embodiment FIG. 1 is a schematic cross-sectional view of a variable capacitor according to a preferred embodiment of the present invention. Please refer to FIG. 1, the variable capacitor of the present invention

12868TWF.PTD Page 9 200532813 V. Description of the invention (5) The device includes an n-type substrate 100, two gate structures 1 02, 1 04, a p-type doped region 106 and an n-type doped region 1 1 0. In a preferred embodiment, the variable capacitor further includes a p-type lightly doped region 108, an n-type lightly doped region 1 1 2, a spacer 1 1 4 and a silicided metal layer 1 16. Among them, the two gate structures 10 and 102 are arranged on the n-type substrate 100, and each of the gate structures 10 and 102 is formed by a lower gate dielectric layer 1 1 8 It is composed of the upper gate conductive layer 120. In addition, the two gate structures 102 and 104 may be disposed on an n-type substrate 100, or may be disposed on a p-type substrate (not shown) having an n-type well region (not shown). In addition, the material of the gate dielectric layer 1 1 8 is, for example, silicon oxide, silicon nitride, or other suitable dielectric materials, and the material of the gate conductive layer 1 20 is, for example, polycrystalline silicon, doped polycrystalline silicon, or other suitable materials. Of conductive materials. In addition, the p-type doped region 106 is disposed in the n-type substrate 100 between the two gate structures 102 and 104, and the two gate structures 丨 〇2 and 丨 〇4 This p-type doped region 106 is shared. In a preferred embodiment, a p-type lightly doped region is further disposed between the n-type substrate 100 and the p-type doped region 106 under the two gate structures 102 and 104. 8. In addition, the n-type doped region 1 10 is disposed in the two gate structures 102 and 104 without a p-type doped region. The ^ -type substrate on the other side of the gate structure. 〇 中. In a preferred embodiment, it further includes arranging a lightly doped region 112 between the n-type substrate 100 and the n-type doped region η0 below the two gate structures 102 and 104. ° In a preferred embodiment, a spacer 1 1 4 is further arranged on the side walls of the two gate structures 102 and 104, and the spacer 1 1 4 is covered with a p-type electrode.

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Page 10 200532813 V. Description of the invention (6) Doped region 108 and n-type lightly doped region 1 12. In another preferred embodiment, it further includes a silicided metal layer 116, which is disposed on the gate conductive layer 120 of the two gate structures 102 and 104, and the p-type doped region 106 and n-type doped. The impurity region 1 1 0 is used to reduce the resistance of the two gate structures 1 102, 104, the p-type doped region 106 and the n-type doped region 1 1 0, thereby increasing their conductivity. . In particular, the aforementioned P-type doped region 10 is electrically connected to the first electrode 1 2 (for example, the anode), and the n-type doped region 1 1 0 is electrically connected to the second electrode 1 2 4 (For example, the cathode), and the two gate structures 10 2 and 10 4 are electrically connected to the first electrode 1 2 2. Of course, in another preferred embodiment, the two gate structures 102, 104 are, for example, electrically connected to the second electrode 12 (such as a cathode) as shown in FIG. The detailed description is that the above-mentioned p-type doped region 10 6 is electrically connected to the first electrode 1 2 2 (for example, an anode), and the n-type doped region 1 1 0 is electrically connected to the second electrode 1 24, and the two gate structures 10, 102 and 104 are electrically connected to the second electrode 1 24. Because the above-mentioned variable capacitors include a MOS variable capacitor mainly with a gate structure of 102 or 104, and a junction type mainly composed of a p-type doped region 106 and an n-type doped region 1 1 0 Variable capacitors, so this variable capacitor has the characteristics of both types of variable capacitors. In detail, in addition to the variable capacitor of the present invention, in addition to the region between the p-type doped region 106 and the n-type doped region 110, the gate dielectric layer 1 1 8 can also be used to store charge (capacitance). Charge. Therefore, the variable capacitor of the present invention has a better charge storage capability than the conventional MOS variable capacitor or the junction type variable capacitor, that is, the adjustable range of its capacitance is larger.

12868TWF.PTD Page 11 200532813 V. Description of the invention (Ό In addition, the variable capacitor of the present invention has a distance between p-type doped region 1 0 and n-type doped region 1 1 0 by the gate structure 1 0 2 and 1 0 4 to control. That is, the narrower the line width of the gate structure 10 2 and 104, the distance between the p-type doped region 1 0 and the n-type doped region 1 1 〇 The smaller it will be, this will reduce the resistance of the variable capacitor, so that the Q factor used to evaluate the variable capacitor will be improved. In addition, in order to prove that the present invention can indeed increase the modulation range of the capacitor, the above is used The variable capacitor performs voltage modulation and corresponding capacitance measurement. The results are shown in Figure 2. Figure 2 is the relationship between the capacitance and the voltage of the variable capacitor, where the horizontal axis represents the modulation voltage (V), and The vertical axis indicates the normalized capacitor. From Figure 2, it can be seen that, within such a large modulation range of voltage 0.5V ~ 2.5V, the modulation range of the capacitor can reach about 70%, compared to The modulation range of the capacitance of the conventional variable capacitor is only 40%. The present invention The capacitance of a variable capacitor does have a large modulation range, and its voltage also has a large modulation range. The second embodiment is shown in FIG. 3, which shows a differential according to a preferred embodiment of the present invention. A schematic cross-sectional view of a variable capacitor of the first embodiment is a variant application of the single variable capacitor of the first embodiment. Please refer to FIG. 3, the differential variable valley device of the present invention is arranged on an n-type substrate 2 The at least one pair of electrically-powered valley states 200 is formed by each of the two pairs, and each pair of variable capacitors includes a variable capacitor 204a and a variable capacitor 204b.

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200532813 V. Description of the invention (8) In the embodiment, the variable capacitor 2 0 4 a further includes a P-type lightly doped region 2 1 4 a, an n-type lightly doped region 2 1 8 a, and a spacer 2 2 0 a. Silicon silicide layer 2 2 2 a. Among them, the two gate structures 2 0 8 a and 2 1 0 a are arranged on an n-type substrate 2 02, and each of the gate structures 2 0 8 a and 2 1 0 a is dielectric by a lower gate. The layer 224a is composed of the gate conductive layer 226a. In addition, the two gate structures 2 0a and 2 10a may be disposed on an n-type substrate 2 0 2, or may be a P-split substrate (not illustrated) having an n-type well region (not illustrated). ) On. In addition, the material of the inter-dielectric layer 2 2 4a is, for example, stone oxide, nitride, or other suitable dielectric materials, and the material of the gate conductive layer 2 2 6 a is, for example, polycrystalline silicon, doped polycrystalline silicon, or other suitable materials. Conductive material. In addition, a p-type doped region 2 1 2 a is disposed in the n-type substrate 2 0 2 between the gate structures 2 0 8 a and 2 1 0 a, and the inter-electrode structure 2 0 8 a This p-type doped region 2 1 2a is shared with 2 1 Oa. In a comparative example, a p-type lightly doped region 2 is further provided between the n-type substrate 200 and the p-type doped region 2 1 2 a under the two gate structures 208a and 210a. 1 4 a. In addition, the n-type doped region 2 1 6 a is disposed in the n-type substrate 20 2 on the other side of the two gate structures 2 8 a and 210 a where the p-type doped region 212 a is not disposed. In a preferred embodiment, an n-type lightly doped region 218a is further disposed between the n-type substrate 202 and the n-type doped region 216 & below the gate structures 2 0a and 210a. In a preferred embodiment, a gap wall 2 2 0a is further disposed on the side walls of the gate structures 2 0 8 a and 2 1 0 a, and the gap wall 2 2 0 a covers a P-type electrode. The doping region 214a and the n-type lightly doped region 218a. In another preferred embodiment, it further includes a silicided metal layer 2 2 2 a, which is configured at the two gate junctions.

12868TWF.PTD Page 13 200532813 V. Description of the invention (9) The gate conductive layer 226a of the structures 208a and 210a and the p-type doped region 212a and the n-type doped region 2 1 6a are used to reduce the two gates. The resistance values of the pole structures 208a and 212a, the P-type doped region 212a, and the n-type doped region 216a increase their conductivity. In addition, another variable capacitor 2 0 4 b is adjacent to the variable capacitor 2 0 4 a and the variable capacitor 2 4 b includes two gate structures 2 0 8 b, 2 1 0 b, and p-type. The doped region 2 1 2 b and the n-type doped region 2 1 6 b. In a preferred embodiment, the variable capacitor 204b further includes a p-type lightly doped region 214b, a ^ -type lightly doped region 218b, a spacer 220b, and a silicided metal layer 222b. Each of the gate structures 2 0 8 b and 2 1 0 b is composed of a lower gate dielectric layer 2 2 4 b and an upper gate conductive layer 226 b. In addition, the n-type doped region 2 16b of the variable capacitor 204b is adjacent to the n-type doped region ^ 16a of the variable capacitor 204a, so it can be regarded as the same doped region. In addition, the configuration relationship of other related components of the variable capacitor 204b is the same as that of the variable capacitor 204a, and is not repeated here. " In particular, 'the gate structure 208a, 2 10a of the variable capacitor 2 0a described above and its p-type doped region 2 1 2 a are electrically connected to a modulation voltage terminal 2 2 8, Moreover, the gate structures 208b, 2iob and the p-type doped region 2 12b of the variable capacitor 204b are electrically connected to a relative modulation voltage terminal 230. Therefore, under the interaction of the modulation voltage and the relative modulation voltage, the n-type doped regions 21 \ 3 and 2 1 6 b located between the modulation voltage terminal 2 28 and the relative modulation voltage terminal 2 3 0 will be grounded. . In this way, the differential variable capacitor will have a higher resistance value, and its quality factor (q Factor) can be further improved.

12868TWF.PTD Page 14 200532813 V. Description of the invention (ίο) In addition, like the variable capacitor in the first embodiment described above, this differential variable capacitor also includes a gate structure 2 0a, 208b M0S variable capacitors based on SiC, 210a or 210b, and junction type variable capacitors based on p-type doped regions 212a, 212b and n-type doped regions 216a, 216b. Therefore, this differential variable capacitor has the characteristics of both types of variable capacitors. In other words, this differential variable capacitor has a better charge storage capability than conventional M0S variable capacitors or face-to-face variable capacitors, and both its capacitance and voltage have a larger modulation range. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

12868TWF.PTD Page 15 200532813 Brief Description of Drawings Figure 1 is a schematic cross-sectional view of a variable capacitor according to a preferred embodiment of the present invention. Fig. 2 is a diagram showing the relationship between capacitance and voltage of a variable capacitor according to a preferred embodiment of the present invention. 3 is a schematic cross-sectional view of a differential variable capacitor according to a preferred embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a variable capacitor according to another preferred embodiment of the present invention. [Illustration of figure mark] 1 00, 2 0 2: n-type base 1 0 2, 1 0 4, 2 0 8 a, 2 1 0 a, 2 0 8 b, 2 1 0 b: gate structure 106, 212a , 212b: p-type doped regions 108, 214a, 214b: p-type lightly doped regions 110, 216a, 216b: n-type doped regions 112, 218a, 218b: n-type lightly doped regions 1 1 4, 2 2 0 a, 2 2 0 b: spacers 116, 222a, 222b: silicided metal layers 118, 224a, 224b: gate dielectric layers 1 2 0, 2 2 6 a, 2 2 6 b: gate conductive layer 122: anode 124 : Cathode 2 0 0: a pair of variable capacitors 2 0 4 a, 2 0 4 b: variable capacitor 2 2 8: modulation voltage terminal

12868TWF.PTD Page 16 200532813 Brief description of the diagram 2 3 0: Relative modulation voltage terminal 2 3 2: Ground

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Claims (1)

200532813 6. Scope of patent application 1. A variable capacitor (Varactor), comprising: a second-type substrate; two gate structures arranged on the second-type substrate, and each of the gate structures is gated by one of the lower layers A dielectric layer and an upper gate conductive layer; a first type doped region disposed in the second type substrate between the two gate structures; and a second type doped region disposed in In the second-type substrate on the other side of the two-gate structure where the first-type doped region is not disposed, the first-type doped region is electrically connected to a first electrode terminal, and the first The second type doped region is electrically connected to a second electrode terminal, and the two gate structure is electrically connected to one of the first electrode terminal and the second electrode terminal. 2. The variable capacitor according to item 1 of the scope of patent application, wherein the first-type doped region is a p-type doped region and the second-type doped region is an n-type doped region. 3. The variable capacitor according to item 1 of the scope of patent application, wherein the first-type doped region is an n-type doped region and the second-type doped region is a p-type doped region. 4. The variable capacitor according to item 1 of the scope of patent application, further comprising a silicided metal layer disposed on the gate conductive layer, the first type doped region and the second type doped region. 5. The variable capacitor as described in item 1 of the patent application scope, further comprising: 12868TWF.PTD Page 18 200532813 6. Scope of patent application-a first-type lightly doped region disposed between the second-type substrate and the first-type doped region under each gate structure; and a second A lightly doped region is disposed between the second type substrate and the second type doped region under each gate structure. 6. The variable capacitor according to item 5 of the scope of patent application, further comprising a gap wall disposed on a side wall of each of the gate structures, and covering the first type lightly doped region and the second type lightly doped Area. 7. A differential variable capacitor (Differential Varactor), the differential variable capacitor is composed of at least one pair of variable capacitors arranged on a second type substrate, each pair of variable capacitors Including: a first variable capacitor, the first variable capacitor includes: two first gate structures arranged on the second-type substrate, and each of the first gate structures is mediated by a first gate of a lower layer An electric layer and a first gate conductive layer on the upper layer; a first type first doped region disposed in the second type substrate between the two first gate structures; and a second type first A doped region is disposed in the second-type substrate on the other side of the two first gate structures where the first-type first doped region is not disposed; and a second variable capacitor and the first A variable capacitor is adjacent, and the second variable capacitor includes: two second gate structures arranged on the second-type substrate, and each of the second gate structures is dielectric by a second gate of a lower layer Layer to layer 12868TWF.PTD Page 19 200532813 6. Scope of patent application: a second gate conductive layer, a first type second doped region, arranged in the second type substrate between the two second gate structures And a second-type second doped region, which is disposed in the second-type substrate on the other side of the second-gate structure where the first-type second-doped region is not disposed, and is in contact with the first-type substrate. The second type first doped region is adjacent, wherein the first gate structure and the first type first doped region are electrically connected to a modulation voltage terminal, and the second gate structure and the first type The second doped region is electrically connected to a relative modulation voltage terminal, and the second type first doped region and the second type second doped region are grounded. 8. The differential variable capacitor according to item 7 in the scope of patent application, wherein the first-type first doped region and the first-type second doped region are P-type doped regions, and the second The first type doped region and the second type doped region are n-type doped regions. 9. The differential variable capacitor according to item 7 in the scope of the patent application, wherein the first type first doped region and the first type second doped region are n-type doped regions, and the second type The first type doped region and the second type doped region are p-type doped regions. 1 0 · The differential variable capacitor according to item 7 of the scope of patent application, further comprising a silicided metal layer disposed on the first gate conductive layer, the second gate conductive layer, and the first type first On the doped region, the first type second doped region, the second type first doped region, and the second type second doped region. 1 1 · Differential variable capacitor as described in item 7 of the scope of patent application 12868TWF.PTD Page 20 200532813 6. The patent application scope further includes: a first-type lightly doped region, the second-type substrate disposed under each of the first gate structure and each of the first-type first Between the doped regions; and a second-type lightly doped region disposed between the second-type substrate and the second-type first doped region under the first gate structure. 1 2. The differential variable capacitor according to item 11 of the scope of patent application, further comprising a gap wall disposed on a side wall of each of the first gate structures and covering the first lightly doped region and The second-type lightly doped region. 1 3. The differential variable capacitor according to item 7 of the scope of patent application, further comprising: a first-type lightly doped region, the second-type substrate and the second-type substrate disposed below each of the second gate structure; Between a first-type second doped region; and a second-type lightly doped region disposed between the second-type substrate and the second-type second doped region under each of the second gate structure. 14. The differential variable capacitor as described in item 13 of the scope of patent application, further comprising a gap wall disposed on a side wall of each of the second gate structures, and covering the first lightly doped region and The second-type lightly doped region. 12868TWF.PTD Page 21