TW200950059A - Semiconductor device - Google Patents

Abstract

A technique which can improve manufacturing yield and product reliability is provided in a semiconductor device having a triple well structure. An inverter circuit INV1 which includes an n-channel type field effect transistor 254n formed in a shallow p-type well 252 and a p-channel type field effect transistor 254p formed in a shallow n-type well 251, and does not contribute to circuit operations is provided in a deep n-type well formed in a p-type substrate; the shallow p-type well 252 is connected to the substrate 1 using a wiring of a first layer 253(M1); and the gate electrode of the p-channel type field effect transistor 254p and the gate electrode of the n-channel type field effect transistor 254n are connected to the shallow n-type well 251 using a wiring of an uppermost layer 255(M8).

Description

200950059 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for forming a well having a three-layer structure, that is, a so-called triple well structure, the aforementioned triple well structure A deep well having a second conductivity type different from the first conductivity type in the substrate of the second conductivity type, and further having a shallow conductivity of the first conductivity type in the deep well. [Prior Art] A logic circuit and I/〇 (Input/) of a semiconductor integrated circuit device having a so-called triple well structure are described in Japanese Patent Laid-Open Publication No. Hei. No. Hei. The 三utput, input output circuit, the above-mentioned triple well structure means that a deep well is formed on the p-type semiconductor substrate and 2 wells for forming the p-type MISFETi 11 well and for constructing the MISFET are formed thereon. A technique disclosed in Japanese Laid-Open Patent Publication No. Hei 9-725-6 (Patent Document 2) is a technique in which a nonvolatile semiconductor memory having a floating electrode and a control gate electrode on a semiconductor substrate is used. Forming n wells on the P-type semiconductor substrate, forming # in the n-well, forming an n-type diffusion layer for preventing electrification, and electrically connecting the anti-charged layer to the control gate electrode to prevent Etching: The reliability of the insulating film caused by charging is reduced or the dielectric is broken. In addition, in Japanese Patent Laid-Open Publication No. Hei. No. 5-34-548 (the patent publication does not have a technique, that is, by connecting a floating wiring to a caliper body, the electric charge flowing in the marine wiring is slid into the tongs. a diode, thereby preventing a short circuit between the floating wiring and the ground line adjacent to the floating wiring. Further, a technique is disclosed in Japanese Patent Laid-Open Publication No. 2001-358143 (Patent Document 4), that is, a wiring layer having at least one wiring layer and an uppermost layer, wherein the at least one wiring layer includes a plurality of relay pins electrically connected to the plurality of gate electrodes, and the wiring layer of the uppermost layer includes a plurality of relay pins respectively Electrically connecting a plurality of wiring patterns, and wiring the gate electrodes using the wiring pattern of the uppermost layer, thereby preventing etching processing

The charged charge at the time of the wiring layer escapes to a region other than the gate electrode, resulting in deterioration of the gate insulating film. [Patent Document 1] Japanese Patent Laid-Open Publication No. Hei. No. 2006-303753 [Patent Document 2] Japanese Patent Laid-Open Publication No. Publication No. Hei No. 2005-340548 [Patent Document 4] 。 〇〇 143 143 143 143 143 143 143 143 143 143 143 143 143 143 143 143 143 143 143 143 143 143 143 143 143 System System System System System System System System System System System System System System System System System System System System System System System System A semiconductor device of well construction. However, the semiconductor device having the triple well structure has various technical problems described below. In general, between the field effect transistors formed in the different triple well regions and between the field effect transistors formed in the triple well region and the substrate, the signals are exchanged as needed, but are required to be electrically connected. The inventors of the present invention found that in a specific circuit, insulation breakdown of a gate insulating film of a field effect transistor due to a triple well structure occurs. As an effective method to prevent the insulation damage of 137166.doc 200950059, yj, such as 0, considers the field effect transistor formed by 汴L_次甲刀 in the different triple well regions via the level shifting circuit. The method of electrical connection. However, the early shift circuit was originally designed to connect the regions where the power supply voltages are different from each other. It is cumbersome to design them only between the regions where the power supply voltages are the same, and the level shift circuit will In the case of a partial area, there is a problem that the semiconductor device becomes large, and the manufacturing cost of the product becomes high. SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for improving manufacturing yield and product reliability in a semiconductor device having a triple well structure. The above and other objects and features of the present invention will become apparent from the description and appended claims. [Technical means for solving the problem] An embodiment of the representative ten inventions in (4) of the present application is briefly described as follows. The present embodiment is a semiconductor device comprising: a type substrate; a deep n-type well not connected to the substrate; a shallow p-type well and a shallow 11-type well formed in different regions of the ice n-type well; and The phaser circuit is composed of an in-channel type field effect transistor formed in the shallow p-type well and a p-channel type field effect transistor formed in the shallow n-type well. The shallow p-type well system uses the first layer wiring and the substrate wiring, and the gate electrode of the 13-channel type field effect transistor and the gate electrode of the n-channel type field effect transistor are formed at the same time as the gate electrode or in the wiring step. Interconnected at an earlier stage, and directly or indirectly connected to the substrate, the portion having the substrate potential, the 137166.doc 200950059 deep n-type well, the shallow P-type well, the shallow n-type well or the circuit action using the uppermost wiring Wiring at a specific location. Further, another embodiment is a semiconductor device comprising: a p-type substrate, a standing well not connected to the substrate; shallow? a well formed in a region other than a deep n-type well in the substrate: a shallow, well formed in the deep (four) well; and an inverter circuit formed by the n-channel type formed in the shallow p-type well Field effect transistor and formed in the above shallow n-type well? Channel type field effect transistor. The gate electrode of the Ρ channel type field effect transistor and the gate electrode of the η channel type field effect transistor are connected to each other at the same time as the gate electrode formation or at an earlier stage of the wiring step, and are directly used by the wiring of the uppermost layer. Or indirectly connected to a substrate, a portion having a substrate potential, a deep n-type well, a shallow p-type well, a shallow n-type well, or a specific portion of the circuit operation. Further, another embodiment is a semiconductor device comprising: a p-type US plate; a deep n-type well not connected to the substrate; ^ (4) formed in the deep well; and a shallow well type formed in the deep n-type In the region other than the shallow n-type well in the well, and not connected to the substrate; and an inverter circuit, which is formed by the n-channel type field effect transistor formed in the shallow well type and formed in the shallow n-type well Channel type field effect transistor. The gate electrode between the ρ channel type field effect transistor and the gate electrode of the η channel type field effect transistor are connected to each other at the same time as the gate electrode formation or at an earlier stage of the wiring step, and are directly or indirectly using the most wiring. The ground is connected to the substrate, the portion having the substrate potential, the clothing type 11 well, the shallow p type well, the shallow n type well, or a specific part of the circuit operation. Still another embodiment is a semiconductor device comprising: a p-type 137166.doc 200950059 plate; a deep n-type well; a shallow p-type well and a shallow 11-type well, which are formed in different regions of the deep well type well And an inverter circuit comprising: an n-channel type field effect transistor formed in the shallow P-type well; and a meandering channel type field effect transistor formed in the shallow n-type well. The gate electrode of the ρ channel type field effect transistor and the gate electrode of the η channel type field effect transistor are directly or indirectly connected to the substrate, the portion having the substrate potential, or the portion having the power supply potential, using the wiring of the uppermost layer. Eight knives and one *16 fat: Nongzhi, the soldiers include: 1) type substrate; heart type well; and shallow Ρ type well and shallow „type well' are formed in different areas of the deep η type well. At least one of the deep well, the above-mentioned & well and the shallow n-type well is directly or indirectly connected to the substrate or the portion having the substrate potential using the wiring of the uppermost layer. Further, an embodiment-type semiconductor device includes: a p-type substrate in-type well; and a shallow p-type well and a shallow-type well, which are formed in different regions in the deep well. The wiring between the portion in the well and the portion in the shallow (four) well formed in the substrate, the substrate region, or the portion in the shallow well having the substrate potential is directly or indirectly performed by wiring the upper layer. Further, an embodiment is a semiconductor device including a type well; and a shallow p-type well and a shallow n-type well are formed in a deep η; different regions in the well. The well is not connected to the substrate, the inner well, the deep type 11 well, and the shallow n-type well. The upper part of the well and the part in the above (4) well, the part of the shallow n-type well formed in the substrate area or the substrate At least the wiring order between the two - J37166.doc 200950059 is directly or indirectly using the uppermost wiring.

Still another embodiment is a semiconductor device comprising: a p-type substrate; a deep n-type well formed in the substrate; a shallow-type well and a shallow n-type well, which are formed in different regions in the deep well And an n-channel field effect transistor formed in a shallow p-type well. The gate of the field effect transistor is connected with the shallow n-type well, the shallow well type is connected with the ground potential, the gate electrode of the field effect transistor is directly or indirectly connected with the shallow n-type well, and the field effect transistor corresponds to the shallow hit The well is made to be in an on state or an off state by accumulating the amount of charge. People, for an implementation, like you, Shengba contains: p-type substrate 'deep η-type well, which is formed in the substrate; shallow (four) well and shallow η-type well, which are formed in deep wells. , Thunder _ ^ L grave, and η channel type field effect day body 'is formed in shallow well type well. Field effect, military and Japanese body and pole and shallow n-type well wiring, shallow p-type well and grounding potential connection wiring of the gate electrode of the % effect transistor and the dirty state wiring, the middle of the wiring... "Electricity The body is turned on or off according to the intermediate potential of the floating state. [Effects of the Invention] 'When the insulation damage of the triple well region is prevented, the formation of the semiconductor device in the middle of the semiconductor device having the triple well structure can be improved. The manufacturing efficiency of the gate insulating film of the field effect transistor and the reliability of the product. [Embodiment] For the sake of convenience, it is divided into a plurality of parts, except for the case where it is specifically indicated, in the following embodiments. In the following description, 137166.doc 200950059 or the like is not related to each other, but there is a relationship between some or all of the other modifications, detailed descriptions, supplementary explanations, etc. In the following embodiments, When the number, such as the number, the numerical value, the quantity, the range, etc., are specifically indicated, and the case is clearly limited to a specific number in principle, etc. The specific number is not limited to a specific number or more, and may be a specific number or less. Further, in the following embodiments, the constituent elements (including the element steps and the like) are of course not necessarily required, except for the case where it is specifically indicated. In addition, in the following embodiments, when the shape, the positional relationship, and the like of the constituent elements and the like are recited, the case is specifically indicated, and it is clearly not the case in principle. Other than the case, it includes elements that are substantially similar or similar to the shape, etc. The same applies to the above numerical values and ranges. Further, in the drawings used in the following embodiments, even a plan view is sometimes used. The pattern is easy to observe, and the shadow is also partially marked. In addition, in the following embodiment, 'the MISFET (Metal) which will represent the field effect transistor

The Insulator Semiconductor Field Effect Transistor is abbreviated as MIS, the p-channel type MISFET is abbreviated as pMIS, and the n-channel type MISFET is abbreviated as nMIS. Further, in the following embodiments, when a wafer is referred to, a Si (Silicon 'sprayed) single crystal wafer is mainly used, but not only for this, but also an SOI (Silicon On Insulator) wafer, An insulating film substrate or the like for forming an integrated circuit thereon. The shape is not only circular or substantially circular, but also includes squares, rectangles, and the like. Further, in the following embodiments, deep wells and shallow wells are used in expressing the wells constituting the triple well structure 137166.doc •10-200950059, where the deep and shallow portions refer to the depth from the main surface of the substrate to the thickness direction of the substrate. Relatively roughly divided into two types, namely deep wells and shallow wells. Therefore, the depth of a plurality of deep wells may not be fixed and sometimes different from each other. Similarly, the depth of a plurality of shallow wells may not be fixed and sometimes different from each other, but the depth of a plurality of deep wells must be formed to be larger than a plurality of shallow wells. / Woodiness. Further, the shallow well system is formed in the substrate or in the deep well, and a plurality of shallow wells are sometimes formed in regions different from each other in the substrate in which the deep well is not formed or in regions different from each other in the deep well. In the drawings, the same functions are denoted by the same reference numerals, and the description thereof will not be repeated. Hereinafter, embodiments of the present invention will be described in detail based on the drawings. First, in order to make the semiconductor device according to the embodiment of the present invention more clear, the reason for the dielectric breakdown of the gate insulating film formed in the triple well region discovered by the inventors of the present invention will be described. The inventors of the present invention conducted research and found that when the lower wiring panel

When a connection hole for connecting the lower layer wiring and the layer wiring is formed on the insulating film formed between the upper wirings, the gate insulating film formed by the 重IS formed in the Dongkai region may cause dielectric breakdown. The present invention goes to A, a丨^ + the sage of the sheep, speculating that since the formation of the connection hole is performed by dry etching using the plasma thunder, i ir, + + €, The electrification caused by the discharge led to the static mine. Furthermore, it has been clarified that the deep wells constituting the triple well area are charged by the electric power, which causes the insulation of the gate insulating film of the MIS in the path from the deep well to the substrate to be broken. Especially when the area of the deep well is larger 砵 _ large. Furthermore, the mechanism for causing dielectric breakdown of the gate insulating film of the field effect transistor 137166.doc 200950059 due to the electric discharge of the plasma discharge frequency is, for example, the plasma of the advanced VLSI technology by Cheung. Charging Destruction, 1998, IEDM short course (C. Cheung, "Plasma Charging Damage in Advanced VLSI Technology", 1998 IEDM Short Course) and McVittie's "plasma current, voltage and charging", 1997, on electricity The second international seminar on pulp damage (J. McVittie, "Plasma Currents, Voltages and Charging", 1997 2nd International Symposium on Plasma Process-Induced Damage, Tutorial) is described in detail. The analysis results of the insulation breakdown of the gate insulating film of the MIS formed in the triple well region obtained by the inventors of the present invention will be specifically described with reference to Figs. 1 to 8'. 1 is a configuration diagram of an audio image processing apparatus used for analysis by the inventors of the present invention. FIG. 2 is a view showing an example of a 1/〇 (input and output) circuit unit and a logic circuit unit constituting the audio image processing apparatus of FIG. FIG. 3 is a schematic diagram for explaining a circuit component of a first good generating mechanism in a deep well in which a positive charge is accumulated. FIG. 4(a) and FIG. 4(1?) are for explaining an inverter circuit. FIG. 5 is a schematic cross-sectional view showing a circuit element of a second defective generating mechanism in which a positive charge is accumulated in a deep well, and FIG. 6 is a schematic diagram of the sound image processing apparatus of FIG. FIG. 7 is a circuit diagram for explaining another example of the circuit portion and the logic circuit portion of the 输入 (input rotation), and FIG. 7 is a third defect generation mechanism for explaining that a negative charge is accumulated in a shallow well having the same conductivity as that of the substrate. FIG. 8 is a cross-sectional view showing a circuit component of a fourth circuit in which a negative charge is accumulated in a shallow well having the same conductivity as that of the substrate. 137166.doc 200950059 . As shown in Fig. 1, the audio image processing device LSI is composed of a plurality of circuits such as an image processing circuit, a communication circuit, and a sound control circuit, and these circuits are large: each of which is provided with an I/O circuit unit. The /〇 circuit unit intermittently supplies the voltage of the circuit operation to the logic circuit unit as a signal. Fig. 1 • The I/O circuit unit 1 is exemplified in the control circuit of the pass k, and the 1/〇 circuit provided in the / circuit is omitted, but most of the other circuits are also provided with the I/O circuit unit. . As shown in Fig. 2, in the logic circuit portion, deep n-type wells 200, 300 are formed in regions different from each other in the P-type substrate 1. Due to the necessity of designing the circuit for supplying the power supply voltage, the deep n-type wells 2, 3, and 3 are not electrically connected to the substrate 1. Further, a plurality of deep n-type wells are formed in the logic circuit portion in addition to the deep n-type wells 200, 300, but the illustration is omitted here. The inventors of the present invention have manufactured a semiconductor device having a triple well structure (for example, φ such as the above-described sound image processing device LSI) and performed a function check to confirm that: between the inside and the outside of the deep well, when the gate electrode of the MIS is When the gate of MIS is connected, it is found that the gate insulating film of MIS has the third defect of dielectric breakdown - the generating mechanism and the third defective generating mechanism, and the inside of the same deep well, • When the gate electrode of MIS and the MIS are not extremely At the time of wiring, the second defective generating mechanism and the fourth defective generating mechanism which caused the dielectric breakdown of the gate insulating film of MIS were found. The first and second defective generating means are mechanisms caused by the discharge of the positive electric charge. The third and fourth defective generating mechanisms are mechanisms caused by the discharge of the negative electric charge. Hereinafter, the first to fourth defective generation mechanisms will be described. The so-called 137166.doc •13- 200950059 inverter circuit is composed of a set of pMIS and nMIS, and the two electrodes are connected and the drains of the two are connected, and then the source and formation of pMIS are The pMIS n-type well connection, the source of nMIS and the formation of nMIS

The circuit of the P-well connection. First, when the gate electrode of MIS and the gate electrode of MIS are connected between the inside and the outside of the deep well, the first defective generating mechanism of the gate insulating film of MIS due to positive charging is destroyed, and the same In the inside of the deep well, when the gate electrode of the MIS is connected to the drain electrode of the MIS, the second defective generating mechanism of the MIS closed-electrode insulating film is damaged by the positive charging. I. The first defect-producing mechanism (the insulation between the inside and the outside of the deep well when the MIS's closed electrode and the MIS's drain electrode are connected due to the positive charge of the deep well). As shown in FIG. 2 above, shallow n-type wells 201 and shallow p-type wells 202 are formed in regions different from each other in the deep n-type well 200, and further, pMIS 203p is formed in the shallow n-type well 201, An nMIS 203η is formed in the shallow p well 202. The inverter circuit is constituted by the pMIS 203p and the nMIS 203n, and it is confirmed by the function check of the present inventors that the gate insulating film of the pMIS 203p or the gate insulating film of the nMIS 203n is insulated. The gate electrode of pMIS 203ρ and the gate electrode of nMIS 203η use the third layer wiring 2 (Μ3) and the outer region of the deep n-type well 200, for example, the pMIS 103p bungee and nMIS formed on the I/O circuit portion. The 103η is electrically connected. Further, an inverter circuit having nMIS 207n as a constituent element is formed in the deep n-type well 200, and the nMIS 207n is formed in a shallow well type electrically connected to the substrate 1 via the first layer wiring 206 (Μ1). In 205, the gate electrode 137166.doc -14 - 200950059 is wired to the specific portion by the third layer wiring 208 (M3). Next, a mechanism for causing dielectric breakdown of the gate insulating film of the pMIS 203p or the gate insulating film of the nMIS 203n of the inverter circuit will be described with reference to Figs. 3 and 4 . 3 is a view showing formation of a connection hole in the interlayer insulating film formed on the third layer wiring (to reach the shallow n-type well 20 1 and the shallow p-type well 202 via the first layer, the second layer, and the third layer wiring) The plasma discharge of the dry etching method causes a positive charging of the deep n-type well 200 of the semiconductor device in the middle of manufacturing. If a positive charge flows from the connection hole into the shallow n-type well 201 and the shallow p-type well 202 formed in the deep n-type well 200, since the deep n-type well 200 is not electrically connected to the substrate 1, the positive charge flowing in will accumulate. In the deep η type well 200. On the other hand, even if the positive electric charge flows into the shallow p-type well 102 which is not formed in the deep n-type well 200 and is formed on the substrate 1, since the conductivity type of the shallow p-type well 102 is the same as that of the substrate 1, the inflow is positive. The charge will discharge toward the substrate 1. However, it is considered to be in an inverter circuit composed of a pMIS (not shown) formed in the shallow n-type well 1 0 1 formed on the substrate 1 and an nMIS (not shown) formed in the shallow p-type well 102. When the gate electrodes of the pMIS and the nMIS are connected to each other and there is a floating state, the shallow n-type well 101 formed in the different regions from each other and the shallow p-type well 102 become a low-resistance conduction state. This phenomenon can be explained as follows. First, as shown in FIG. 4(a), when a voltage Vcc is applied to the source of the pMIS constituting the inverter circuit having the above characteristics, between the gate electrode G of the pMIS and the channel and the gate electrode G of the nMIS A capacitor C is formed between the channel and the channel. As a result, a voltage Vcc/2 is applied to the gate electrode G of the pMIS and the gate electrode G of the nMIS, respectively, so that pMIS and nMIS are turned on. When pMIS and nMIS become the conduction state 137166.doc -15- 200950059, as shown in Fig. 4(b), the positive charge flows from the source S of the pMIS formed in the n-well n-well to the immersion D, and further from p The drain D of the nMIS formed in the p-well of the well flows to the source S, and then flows to the p-well of the p-well formed with the nMIS, and the substrate p-sub 〇, regardless of the wiring state of the gate electrode of nMIS 1 03η The shallow n-type well 101 and the shallow p-type well 102 are both turned into a low-resistance conduction state via the inverter circuit, and the positive electric charge is self-wiring toward the substrate via the shallow n-type well 101 and the shallow p-type well 102. 1 discharge (path I of Figure 3). Therefore, the potential of the gate electrode of the inverter circuit composed of the pMIS 203p and the nMIS 203n becomes equal to the potential (〇V) of the substrate 1, and the voltage applied to the gate insulating film becomes large, thereby causing dielectric breakdown. Produced. Moreover, even when the gate electrodes of the inverter circuit formed in the shallow n-type well 01 and the shallow p-type well 102 are all connected, when the connection destination of the gate electrode of the nMIS 103n is positively charged, nMIS The 103n also becomes in an on state, and the positive electric charge is discharged from the wiring toward the drain of the nMIS 101n, the source, the shallow p-type well 102, and the substrate 1 (path II of FIG. 3). Therefore, the potential of the gate electrode of the inverter circuit composed of pMIS 203ρ and nMIS 203η becomes equal to the potential of the substrate (〇V), and the voltage applied to the gate insulating film becomes large, thereby causing dielectric breakdown. produce. However, it is considered that whether or not the connection destination of the gate electrode of the nMIS 103n is continually dominated by the positive charging system depends on the circuit configuration and the shape of the circuit constituent elements. Therefore, a semiconductor device manufactured in large quantities accidentally causes dielectric breakdown. Further, when the area of the deep n-type well 200 is, for example, 1 mm 2 or more, the amount of charge accumulated in the deep n-type well 200 is increased, and insulation breakdown is likely to occur. 137166.doc •16· 200950059 Π. The second bad-producing mechanism (in the same deep well, when the gate electrode of mis is connected to the electrode of the MIS, the insulation is broken due to the positive charge of the deep well). As shown in Fig. 2 above, in the deep n-type well 3 彼此 different regions. The towel is formed with shallow _ well and shallow ρ-type well 3 〇 4, and then within the & type well 3 〇 4, An nMIS 308 is formed. The shallow well 304 is electrically connected to the substrate 1 by the first layer wiring 3〇5 (M1) due to the circuit design. Further, in the squat 300, in a region different from the shallow n-type well 303 and the shallow p-type well 304, shallow n-type wells 3〇1 and shallow p-type wells 3〇2 are formed in regions different from each other, and further _3 3〇7ρ is formed in the shallow η type well 3〇1, and nMIS 3G7n is formed in the shallow ρ type well. The inverter circuit is constituted by the pMIS 3Q7p and the nMIS 3() 7η, and the output section of the inverted II circuit and the gate electrode system of n_3 〇8 formed in the shallow p-type well 3〇4, using the seventh layer The i line 3 i (m 7) is electrically connected. Further, the output section of the inverter circuit formed by the nMIS 3〇9n formed in the pMIS 3〇9p and the shallow p type well 3〇4 formed in the shallow n-type well 303, and the PMIS 3 of the inverter electric circuit The gate electrode of 〇7? and the gate electrode of IS 307n are electrically connected using the seventh layer wiring 31G (M7), but the illustration is omitted. Like the pole electrode between the inverter circuits composed of the state π 3〇9p and nMIS 3〇9n, the nMls formed in the shallow ρ-well 304 are the poles of the inverter circuits. The seventh layer wiring or the wiring 312 of the layer before the seventh layer is electrically connected to a specific portion required for the operation of the circuit. Next, a mechanism for causing insulation breakdown of the gate insulating film of 308 by wiring the inside of the same deep well will be described with reference to Fig. 5 . Fig. $ is a diagram showing the deep η-type well of the semiconductor device in the middle of manufacturing due to the plasma discharge of the dry etching method in the case where the connection hole 137166.doc 17 200950059 is formed on the interlayer insulating film formed on the wiring of the seventh layer. 〇 is a schematic diagram of charging. At this stage, all of the gate electrodes of the inverter circuit in which the 11 river 18 formed in the shallow p-type well 309 is a component are wired to a specific portion. Therefore, the shallow well type 304 and the shallow η type well 3〇3 or the bead type η type well 300 constitute a diode, and flow into the deep type 11 well through the shallow 卩 type well 3〇2, the shallow η type well ^, 3〇3 The positive charge in 3〇〇 does not discharge and accumulates. It can be inferred that the connection destination of the wiring 310 (M7) is at the same potential (0 V) as that of the substrate 1 when the deep n-type well 3 is charged, and at this time, the pMIS 3〇7p is turned on. The result is formed from the deep! Type 1 well 300 to the shallow n-type well 3〇1, the shallow η-type well 3〇1 formed in the pMIS 307ρ source, the drain, the wiring 3u (M7) and the riMIS 308 gate electrode Connection path. From this, it can be inferred that the substrate is formed in the nMIS 308! It is an inversion layer of equipotential, and therefore a large voltage is applied to the gate insulating film, resulting in insulation breakdown. At this time, since the potential difference is also generated on the gate insulating film of the pMIS 307p, the gate insulating film may also cause dielectric breakdown, but no dielectric breakdown occurs in the functional inspection performed by the present inventors. It is presumed that the reason is that there is a structural defect called a weak point in the dielectric breakdown portion of nMIS 308, and in contrast, there is no weak point in the gate insulating film of pMls 3〇7p. In this case, the defective generating mechanism (the first and second defective generating mechanisms) when the deep n-type wells 200 and 300 are positively charged is described. However, depending on the product, the deep n-type wells 200 and 300 may be formed. The shallow p-type well is also negatively charged, and it is also speculated that the gate insulating film of (10) is insulated and damaged due to the negative p-band of the shallow p-type well. Specifically, it is shallow as shown in Figure 6. The area of the well 2〇2, 3〇2 137166.doc -18- 200950059 This situation is more significant when it is larger. Secondly, the third defective generating mechanism that causes dielectric breakdown due to the negative charging of the gate insulating film of MIS when the gate electrode of MIS is connected to the drain electrode of MIS between the inside and the outside of the deep well, and in the same deep well In the inside, when the gate electrode of the MIS is connected to the drain electrode of the MIS, the fourth defect generation mechanism that causes dielectric breakdown due to the negative charge of the gate insulating film of the MIS will be described. ❹

第. Third bad-producing mechanism (insulation breakdown caused by negative charging of deep wells when the gate electrode of Mis is connected to the drain electrode of MIS between the internal and external parts of the deep well) β Use the Figure 7 for the inverter circuit ipMIS A mechanism for insulating damage caused by a gate insulating film of 2 〇 3 ρ or a gate insulating film of nMIS 203 η will be described. Fig. 7 is a view showing the plasma discharge in the dry etching method in the case where the connection holes are formed in the interlayer insulating film formed on the third layer wiring, which results in the formation of the deep n-type well 200 in the middle half of the manufacturing apparatus. Schematic diagram of the negative charging of the p-type well 2〇2. When a negative charge flows from the connection hole into the shallow p-type well 202 formed in the deep n-type well 2, the shallow p-type well 2〇2 is formed in the deep n-type well 2〇〇 and is not electrically connected to the substrate 1. The connection 'so the negative charge flowing in will accumulate in the shallow p-type well. On the other hand, even if the charge inflow is not formed in the deep n-type well 200 and is formed in the shallow p-type well 1〇2 in the substrate crucible, since the type is the same as the substrate, the inflow charge will also be directed toward the base two. In the negative charge that exists in the wiring, since the nMIS 1G3n connected to the wiring 2 (Μ3) is oriented in the direction of the shallow well 102, the negative charge will pass through the shallow P-well 1 〇 2 and discharge toward the base W. 137166.doc •19- 200950059 Therefore, by pMIS 203p and nMlS 2〇3!! 槿 夕 g 士 士 士 势 wn wn wn wn wn 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒The potential Μ ~ 伹 () v) phase is dedicated, and the voltage applied to the gate insulating film becomes large, resulting in insulation breakdown. IV. The fourth defect-producing mechanism (in the same deep well, the insulation between the pole electrode and the MIS electrode is broken due to the negative charging of the deep well). The mechanism for causing insulation breakdown of the gate insulating film of nMis 3〇8 which is wired inside the same deep well will be described with reference to FIG. Fig. 8 is a view showing a shallow p-type well in a deep n-type well 300 of a semiconductor device in the middle of manufacturing due to plasma discharge of a dry etching method when a connection hole is formed on an interlayer insulating film formed on a seventh layer wiring. 302 is a schematic diagram of negative charging. At this stage, all of the gate electrodes of the inverter circuit in which the 11 river 18 formed in the shallow well 302 is a component are connected to a specific portion. Therefore, the shallow p-type well 3〇2 and the shallow n-type well 301 or the deep n-type well 3〇〇 constitute a diode, and the negative electric charge flowing into the shallow p-type well 3〇2 does not discharge and accumulates. It is presumed that the connection of the wiring 3丨〇(Μ7) is at the same potential as that of the substrate 1 when the shallow p-type well 302 is charged, and at this time, the nMIS 307η is turned on. As a result, a negative potential is applied from the gate electrodes of the source, the drain, the wiring 311, and the nMIS 3〇8 of the shallow ρ-type well 3〇MinMIS 3〇7η. Since the shallow p-type well 3形成4 in which the nMIS 308 is formed is electrically connected to the substrate by the first layer wiring 305 (M1), a potential difference is generated between the insulating films between the nMISs 308, resulting in dielectric breakdown. produce. According to the analysis results described above, in order to prevent dielectric breakdown of the gate insulating film of MIS, any of the following methods (1) or (2) or a combination of the methods may be used, namely: (1) Method: (1-1) Prevention of deep well electrification (for the above-mentioned 137166.doc -20-200950059 solution for the first and second failure generating mechanisms) or (1_2) prevention of shallow wells formed in the deep well and having the same conductivity as the substrate Charge (for the third and fourth problems of the above-mentioned defective generation mechanism); or (7) & method: blocking the wiring path from the shallow well formed in the deep well or the deep well to the substrate or the portion having the substrate potential via the gate insulating film of the MIS (Remedy for the above 1st to 1st 4th defective generation mechanism). Next, the first method and the second method will be described in detail. (1) The first method: ❹ (1-1) Prevent deep wells from being charged. Forming a shallow well having the same conductivity type as the substrate in the deep well, connecting the shallow well to the substrate at an early stage of a series of wiring steps and forming Mls in the shallow well, constructing at an earlier stage of the series wiring step The inverter circuit of the element is maintained until the wiring step is completed, and the gate electrode of the mis is maintained in a floating state without being wired to other portions. Here, as the wiring for connecting the gate electrode of the MIS which constitutes the inverter circuit to the substrate or the shallow terminal, it is preferable to use a wiring which constitutes one of the layers of the multilayer wiring, and the wiring is The number of connection holes formed on the insulating film directly above the wiring is smaller than the number of connection holes formed on the insulating film directly above the lower wiring. If possible, it is desirable to perform the above wiring by wiring the top layer. In addition, the wiring of the uppermost layer described in the present embodiment means a wiring layer which is the same layer as the wiring layer which is a bonding pad. The pad is a region to which an external connection conductor such as a bonding wire or a bump electrode is connected in the subsequent step. Here, the inverter circuit having the same conductivity type as the substrate and the inverter internal circuit 137166.doc 21 200950059 = IS is used as a component to prevent charging, and does not contribute to circuit operation. In the case where the above wiring can be used by electricity, the above components can also be wired using circuit components. At this time, as long as the (4) idle electrode is in a state of eccentricity at the completion stage of the product, the (4) electrode of the MIS can be connected to any part required for the circuit configuration... having a shallow well and a substrate of the base type 7 The connection may not be made directly, but may be performed indirectly via a shallow well connected to the substrate. (1-2) Prevention of formation in a deep well and having the same conductivity as the substrate. / When a shallow well formed in a deep well and having the same conductivity as the substrate is connected to the substrate, the charging can be prevented by the earlier stage of the series-wiring step. When it is impossible to connect a shallow well formed in a deep well and having the same conductivity as the substrate to the substrate, the (4) well is not connected to the substrate and is formed inside the MIS, and is constructed at an early stage of a series of wiring steps. This is the inverter circuit of the constituent elements, and until the wiring step is completed, the gate electrode of the MIS is maintained in a floating state without being wired to other portions. Here, as the wiring for connecting the gate electrode of the MIS which constitutes the inverter circuit to the substrate or the shallow well, it is preferable to use a wiring which constitutes one of the layers of the multilayer wiring, and the wiring The number of the connection holes formed on the insulating film directly above is smaller than the number of the connection holes formed on the insulating film directly above the lower layer wiring. If possible, it is preferable to perform the above wiring by the wiring of the uppermost layer. 137166.doc -22- 200950059 Here, a shallow well having the same conductivity type as the substrate and an inverter circuit formed as the constituent element in the above (4) are produced for the purpose of preventing charging, and do not contribute to circuit operation. . In the case where the above-mentioned wiring can be used by using the circuit constituent elements, the above-mentioned wiring can also be performed using the circuit constituent elements. In this case, as long as the idle electrode of the crucible is prevented from being in a floating state at the completion stage of the product, the gate electrode of the MIS can be connected to any portion required for the circuit configuration. (7) The second method is to block the wiring path from the deep well or the shallow well formed in the deep well to the substrate or the portion having the substrate potential by the gate insulating film. At least a portion of the electrical connection between the three (four) region and the region other than the triple well region is performed by using a wire as described below, the wiring system constituting the wiring of the layer in the multilayer wiring, and the insulating film directly above the wiring The number of connection holes formed thereon is smaller than the number of connection holes formed on the insulating film directly above the lower layer wiring. If possible, it is desirable to use the uppermost wiring for the above wiring. Further, the electrical connection between the different triple-turn regions can be similarly performed by the wiring described above. This method is particularly effective when the first method is applied to one of the triple well regions and the second method is not applied to the other triple well region. Further, in the same double well region, the electrical connection between the inside and the outside of the shallow well having the same conductivity type as that of the substrate and directly or indirectly connected to the substrate can be similarly performed by the wiring. Moreover, in the triple well region, the same conductivity type as the substrate is used, and the electrical connection to the 137166.doc -23-200950059 is also performed in the same manner as the wiring between the inside and the outside of the shallow well connected by the upper substrate. . At least a part of the electrical connection between the deep n-type well and the deep n-type shallow well and the substrate which must be connected to the substrate in the circuit 5 and the circuit can be similarly performed by the wiring. The mechanism for preventing dielectric breakdown of the gate insulating film of mis by the first method and the second method will be described. Here, the relationship is 'p-type on the substrate.

When the substrate is n-type, the n-type and p-type may be replaced in the following description. (1) Method 1: 0-1) Prevent deep wells from being charged.

When the gate electrode of the pMis and nMlS in the inverter circuit formed in the deep n-type well is in a floating state, the field is formed between the shallow well formed with the p-cut and the shallow material formed with the soil 18. State (refer to Figure 4 (4) ()) Therefore, if a shallow p-type well with the same conductivity type as the p-type substrate is connected, the soil plate is not only the shallow p-type well, but also the deep p-well of the shallow p-type well The charge flowing into the shallow n-type well existing in the deep η well will discharge toward the substrate. Therefore, if the shallow p-type well and the substrate are connected by the first wiring layer, the gate electrodes of the pMIS and nMIS which constitute the inverter circuit are in a sub-moving state, and the charging of the 罙n-type well can be suppressed. As a result, insulation breakdown of the gate insulating film can be prevented. Between the gate electrode of the pMIS constituting the reverse phase benefit circuit and the nMISi gate electrode, the gate electrode itself can be used as a wiring to form a gate electrode while the wiring is formed. In this case, it is not necessary to use a wiring step. Come and pick up the line 137166.doc -24· 200950059. If the pole electrode between the pMIS and the Lang 8 forming the inverter circuit is still floating after the completion of the product, the corresponding L-well and the & well will become conductive, resulting in an increase in power consumption. Therefore, it is not good. Therefore, the pMIanMIk '^ electrode of the inverter circuit which is in a floating state is connected to the specific one in the step of the plurality of wiring steps. However, the charging suppression effect is impaired at the time of connection, so it is preferable that the above connection is made as far as possible in the subsequent steps. At this point, consider the following aspects for better results. It is considered that when a connection hole is formed on the interlayer insulating film, the positive charge accumulated in the deep n-type well mostly reaches the well and the well, and flows in from the plurality of connection holes formed. Each of the connection holes is formed at substantially the same position each time the interlayer insulating film of each layer is formed, whereby any of the wiring layers can be electrically connected to the shallow p-type well or the shallow-well with low resistance. However, in the insulating film formed on the wiring of the upper layer, the connection portion to the outside of the conductor device of the 〇I is mainly made to open, so that the connection hole to the shallow p-type well or the shallow n-type well is not substantially formed. Therefore, even without an inverter circuit having gate electrodes of PMIS and nMIS in a floating state, the deep n-type well is substantially uncharged. Therefore, it is preferable to use the uppermost layer 2 wiring for the connection of the above-described inverter circuit and the gate electrode of the nMIS to the specific portion. ‘However, it is also necessary to connect the gates of the pMis&nMis constituting the inverter circuit to a specific portion by wiring formed by the wiring of the uppermost layer, but the effect is not bad. In particular, when the number of connection holes formed on the wiring is small, the number of connection holes formed on the wiring is small, 137166.doc -25- 200950059, the number of connection holes formed on the wiring of the lower layer of the wiring By connecting the gate electrode and the specific portion of the pMIS&nMIS constituting the inverter circuit to the wiring, it is possible to obtain an effect when the connection is made by the wiring of the uppermost layer. U-2) Prevents shallow wells that are formed in deep wells and have the same conductivity as the substrate. When a shallow p-type well in a deep n-type well is connected to a p-type substrate, the charge is discharged even without special operation, so there is no problem. However, when the shallow P-type well is not connected to the p-type substrate, an inverter circuit having nMIS formed in the shallow P-type well as a constituent element is constructed at an early stage of the wiring step, and the gate electrode thereof is maintained floating. In the same state, the same as the above-mentioned countermeasures for preventing the deep well charging, the group shallow n-type well and the p 1 well are in an on state, so that the negative electric charge flowing into the shallow well is passed. The shallow well and the deep η well are discharged toward the substrate. Here, it is assumed that one of the elements constituting the inverter circuit is used, but it is also possible to form an inverter for the purpose of preventing shallow-well charging in deep-mouth wells or deep-n-type wells without using circuit components. Circuit. In this case, it is also possible to form a shallow n^L well and a G-p type well which constitute an inverter circuit in addition to other circuit elements. In any case, if the gate electrode of the MIS is still in a floating state in the state in which the semiconductor device has been completed, a large current flows between the shallow n-type well and the & type well when the semiconductor device is used, and the power consumption is reduced, This person is awkward. Therefore, it is preferable to be the same as the constituent elements of the inverter circuit system. It is preferable to connect the closed electrode to an appropriate portion, for example, a Ρ里井久 η-type well or a substrate. When the above-mentioned interpole electrode is connected to the shallow 127166.doc -26-200950059 well, shallow n-type well or substrate, the gate potential is solid, so there is no excessive current flow, and the power consumption is only slightly increased. It can also be connected to a part other than these parts, but the potential of the gate electrode fluctuates with the circuit's movement, and there is excessive current flow. Therefore, the power consumption is slightly increased. Furthermore, the method of forming a dedicated inverter circuit for the purpose of preventing the charging of a deep n-type well or a shallow p-type well is required to form the inverter circuit region, and thus there is a disadvantage that the semiconductor wafer becomes large. On the other hand, the party

The method has the advantage that there is no restriction on the layout. In particular, the advantages of the shallow well and the shallow well are made special. Therefore, it is possible to select whether or not to form a dedicated inverter circuit as needed. (7) Second method: A wiring path from a deep well or a shallow well formed in a deep well and having the same conductivity as the substrate reaches the substrate or the portion having the substrate potential via the gate insulating film of the MIS. The second method is for blocking the current path from the deep η type well through the MIS impurity insulating film substrate or the portion having the substrate potential, or from the shallow mouth in the deep n-type well during the charging step of the significant charging process. The well is broken by the insulation of the gate insulating film substrate or the current path mMISm (4) of the portion having the substrate potential. When the connection holes reaching the shallow p 1 well or the 戋n-type well are formed more, is the shallow η-type well or the deep η-type well formed shallow? The wells are significantly charged. Therefore, the shallow p-type formed between the ice n-type well and the substrate or the portion having the substrate potential or the deep well is formed by using a wiring layer having a relatively small number of connection holes formed on the insulating film directly above. Between the well and the substrate or the portion having the substrate potential, the charge amount of the deep η-type well after the connection or the charge of the 137166.doc •27·200950059 well in the deep η-type well can be reduced, thereby preventing the MIS gate Insulation damage of the pole insulating film. At this time, similarly to the above-described third method, if the wiring of the uppermost layer is used, good results can be obtained. (Embodiment 1) This embodiment will be described with reference to Figs. 9 to 12! A semiconductor device having a triple well structure will be described. Here, an example of implementing the third method for positive charging will be described. Fig. 9 is a circuit diagram showing an example of a 1/〇 (input/output) circuit unit and a logic circuit unit of the audio image processing apparatus of the present embodiment, and Fig. 10 is a configuration of the present embodiment. FIG. 11 is a cross-sectional view showing a circuit component of an inverter circuit to which the above-described second method is applied, and FIG. 12 is a schematic diagram for explaining a main portion of a region of a pMIS and an nMIS of an inverter circuit of the present invention. A schematic cross-sectional view showing a circuit element of the MIS to which the above-described second method is applied in the first embodiment. As shown in Fig. 9, in the logic circuit portion, deep n-type wells _, 3 (10) are formed in regions different from each other in the p-type substrate i. Due to the necessity of designing the circuit for supplying power voltage, please visit “Sleeve #, Λ λ ____

The pMIS 254ρ and the nMIS 254η constitute an inverter circuit 254η. These are the same. Inverter power 137166.doc -28· 200950059 The gate electrode of pMIS 254p of INV1 and the gate electrode of nMIS 254η use the 8th layer wiring 255 (Μ8) and the n-type semiconductor formed in the shallow n-type well 251. Regional connection. The wiring for constituting the inverter circuit INV1 is performed using the first layer wiring except for the gate electrode of the pMIS 254p and the gate electrode of the nMIS 254n. The wiring between the gate electrode of pMIS 254p and the gate electrode of nMIS 254n is performed while forming the gate electrode. The shallow p-type well 252 is connected to the substrate 1 by the first layer wiring 253 (Μ1). Fig. 10 is a cross-sectional view showing the essential part of a region including pMIS 254p and nMIS 254n constituting the inverter circuit INV1. The gate electrode of the pMIS 254p formed in the shallow n-type well 251 is, for example, a structure in which a polycrystalline germanium film 503 to which a p-type impurity is added and a germanide layer 505 are laminated, and a gate of nMIS 254η formed in the shallow p-type well 252 is formed. The electrode is, for example, a structure in which a polycrystalline germanium film 504 to which an n-type impurity is added and a germanide layer 505 are laminated, and a gate electrode of the pMIS 254p and a gate electrode of the nMIS 254n are connected by a lithiation layer 505. Further, the gate electrode 503 of the pMIS 254p and the gate electrode 504 of the nMIS 254n are electrically connected to the shallow n-well 251 via the first to eighth wirings M1 to Μ8. Further, the shallow p-type well 252 is electrically connected to the substrate 1 via the first layer wiring 253 (Μ1). Further, in the deep n-type well 200, pMIS 203ρ and nMIS 203n which constitute an inverter circuit which plays a specific role in the operation of the circuit are formed. The gate electrode of the pMIS 203p and the gate electrode of the nMIS 203n of the inverter circuit are the regions outside the deep n-well 200 using the third layer wiring 2 (Μ3), for example, the pMIS 103 formed on the 1/〇 circuit portion. The bungee of the bungee and the nMIS 10311 are connected. Further, in the different regions of the deep η-type well 200, shallow n 137166.doc -29-200950059 type well 204 and shallow p-type well 205 are formed, and the shallow p-type well 205 is borrowed due to the necessity of circuit. The first layer wiring 206 (M1) is electrically connected to the substrate 1. The shallow n-well 204 and the shallow well 205 include an inverter circuit composed of pMIS 207ρ and nMIS 207η, and a plurality of inverter circuits are formed, but the gate electrodes are used until the third layer. Wire any of the wires to wire a specific part of the circuit. Therefore, after the step of forming the third layer wiring, the function of preventing the deep n-type well 200 from being charged is not expected for the shallow p-type well 205. In the deep n-well 300, an inverter circuit INV2 which does not function in the circuit operation is also formed. Shallow n-type wells 351 and shallow p-type wells 352 are formed in different regions of the deep n-type well 300, and 卩1^18 3 54? is formed in the shallow n-type well 351, which is shallow? The well 3 52 is formed with 11]^18 3 5411. The inverter circuit INV2 is constituted by the pMIS 3 54p and the nMIS 3 54n. The gate electrode of the pMIS 354p and the gate electrode of the nMIS 354n of the inverter circuit INV2 are connected to the p-type semiconductor region formed in the shallow p-well 352 by using the eighth layer wiring 355 (Μ8). The wiring for constituting the inverter circuit INV2 is performed using the first layer wiring except for the gate electrode of the pMIS 3 54p and the gate electrode of the nMIS 3 54n. Further, the wiring between the gate electrode of the pMIS 354p and the gate electrode of the nMIS 354n is performed while forming the gate electrode. The shallow p-type well 352 is connected to the substrate 1 by the first layer wiring 353 (Μ1). Further, nMIS 3 08 is formed in the shallow p-type well 304 formed in the deep n-type well 300, and the gate electrode of the nMIS 3 08 is formed by using the third layer wiring 311 (M3) and the shallow n-type well 301. The pMIS 307p and the output section of the inverter circuit formed by the nMIS 307n formed in the shallow p-type well 302 are connected. The shallow P-well 304 including nMIS 308 137166.doc • 30-200950059 is electrically connected to the substrate 1 by the ith layer wiring 3 05 (M1) due to the necessity of circuit. In the shallow p-type well 3〇4, an inverter circuit having nMis 309η as a constituent element is included and a plurality of inverter circuits are formed, but the gate electrodes are all used in the wiring up to the third layer. A wire is connected to a specific part of the circuit. Therefore, after the step of forming the third layer of the wiring, it is not desirable for the shallow well 304 to prevent the deep n-type well from being charged. H Next, the effect obtained by the first method of the first embodiment will be described with reference to Fig. 11 . Fig. 。 is a schematic cross-sectional view showing a case where a deep n-type well 200 in a semiconductor device is charged in a step of forming a connection hole in an interlayer insulating film formed on a wiring of a third layer. At this stage (the step of forming a connection hole on the interlayer insulating film formed on the wiring of the third layer), the gate 4 of the pMIS 254p and the gate electrode of the nMIS 254n which constitute the inverter circuit INV1 are in a floating state. Therefore, the positive electric charge that flows into the deep n-type well 2 due to the discharge of the electric power is discharged to the substrate 1 via the inverter circuit 〇 and the 〇 wiring 253 (Μ1). Therefore, in the inverter circuit composed of the pMIS 203ρ and the nMIS 203η formed in the deep η-type well 200, regardless of whether the gate electrode 连接 is connected to the 没η of the substrate 1, the gate is insulated. There is no potential difference on the film, so there is no insulation breakage. Furthermore, as the shallow n-type well 1 〇1 is charged, sometimes one of the drains is positively charged. At this time, on the gate insulating film of pMIS 2〇3ρ and nMls 2〇3n constituting the inverter circuit. A potential difference is generated. However, since the area of the shallow n-type well ι 〇 1 is small, the amount of charge is small, and the degree of insulation damage of the gate insulating film is not obtained. For other circuit components, the insulation damage of the gate insulating film of MIS can also be suppressed in the same way. In the above-mentioned figure, the charged state in the step of forming the connection hole in the interlayer insulating film formed on the wiring of the third layer is shown, but the connection is formed on the interlayer insulating film formed on the wiring of the seventh layer. At the step of the hole, the electric charge flowing into the deep n-type well is discharged, so that the insulation breakdown of the gate insulating film of MIS can be suppressed. Further, in the step of forming the connection holes formed in the insulating film formed on the eighth layer wiring, the deep n-type well 200 has a small amount of charge, so that the MIS gate insulating film does not cause dielectric breakdown. Next, another effect obtained by the second method of the present embodiment will be described with reference to Fig. 12 . Fig. 12 is a schematic cross-sectional view showing a state in which a deep n-type well 300 in a semiconductor device is charged in a step of forming a connection hole in an interlayer insulating film formed on a third layer wiring. In this stage (the step of forming a connection hole on the interlayer insulating film formed on the third layer wiring), the gate electrode constituting the inverter circuit INV22pMIS 354p and the gate electrode of the nMIS 354n are in a floating state, and thus The positive electric charge that flows into the deep n-type well 300 by the slurry discharge is discharged toward the substrate via the inverter circuit 跗¥2 and the wiring 353 (Μ1). Thereby, all shallow n-type wells and shallow wells located in the deep n-type well can be prevented from being charged. Therefore, in the nMIS 308 formed in the deep n-type well 3, regardless of whether the pole electrode is connected to the drain of the nMIS 3〇7n formed in the other shallow P-well 302, the gate insulating film is not generated. The potential difference is so that no dielectric breakdown occurs. (Embodiment 2) A semiconductor device having a triple well structure according to the second embodiment will be described with reference to Fig. 13 . Here, another example of the first method different from the first embodiment of the above-described embodiment 137I66.doc-32-200950059 will be described. Fig. 13 is a circuit diagram showing an example of a 1/0 (input/output) circuit unit and a logic circuit unit of the second embodiment which constitutes the audio image processing apparatus of Fig. 1 described above. As shown in FIG. 13, in the deep n-type well 200, the inverter circuit INV1 composed of the pMIS 254p and the nMIS 254n which does not contribute to the circuit operation formed in the semiconductor device of the first embodiment described above is not formed, and the pMIS is included. A shallow n-type well 251 of 254p and a shallow p-type well 252 containing nMIS 254η. Instead, the shallow p-well 205 is connected to the substrate 1 by the first layer wiring 206 (Μ1), and is composed of the pMIS 207ρ and the nMIS 207n by the eighth-layer wiring 209 (Μ8) of the uppermost layer. The gate electrode of the inverter circuit INV3 is connected to a specific portion of the circuit, whereby the inverter circuit INV3 has a function of preventing the deep n-well 200 from being charged. On the other hand, in the deep n-type well 300, the inverter circuit INV2 composed of the pMIS 354p and the nMIS 354n, which is formed in the semiconductor device of the first embodiment, which does not contribute to the circuit operation, is not formed, and the pMIS 354p is included. The shallow n-type well 351 and the shallow p-type well 352 enclosing the nMI S 354η. Instead, the shallow p-well 304 is connected to the substrate by the first layer wiring 305 (Μ1), and is composed of pMIS 3 09ρ and nMIS 3 09η by the eighth layer wiring 313 (Μ8) of the uppermost layer. The gate electrode of the inverter circuit INV4 is connected to a specific portion of the circuit. Other circuit configurations and the like are the same as those in the first embodiment described above. Next, the effects obtained by the second embodiment will be described.

In the second embodiment, the gate electrode of the inverter circuit INV3 composed of pMIS 207ρ and nMIS 207n and the gate electrode of the inverter circuit INV4 composed of pMIS 309ρ and nMIS 137166.doc -33- 200950059 3 09η Both are maintained in a floating state until the formation step of the uppermost layer 8 wiring, and the shallow p well 205 including the nMIS 207n constituting the inverter circuit INV3 and the nMIS including the inverter circuit INV4 are included. The shallow p-type wells 309 η are connected to the substrate 1 using the first layer wirings 206 (Μ1) and 305 (Μ1), respectively. As a result, the positive electric charges flowing into the deep n-type wells 200 and 300 are discharged toward the substrate 1 in the same manner as in the first embodiment until the step of forming the connection holes in the interlayer insulating film formed on the seventh layer wiring. As a result, the dielectric breakdown of the gate insulating film generated on the pMIS 203p or nMIS 203n constituting the inverter circuit and the dielectric breakdown of the gate insulating film generated on the nMIS 308 can be suppressed. (Embodiment 3) A semiconductor device having a triple well structure according to Embodiment 3 will be described with reference to Figs. 14 and 15 . Here, another example of the first method different from the above-described first and second embodiments for positive charging will be described. Fig. 14 is a circuit diagram showing an example of a 1/0 (input/output) circuit unit and a logic circuit unit of the third embodiment which constitutes the audio image processing apparatus of Fig. 1, and Fig. 15 is a configuration including the configuration of the third embodiment. A cross-sectional view of a main portion of a region of pMIS and nMIS of the inverter circuit of the first method. As shown in FIG. 14, among the pMIS 254p and nMIS 254n constituting the inverter circuit INV1 for preventing the deep n-type well 200 from being charged, the nMIS 254n is different from that of the first embodiment, and is formed in the shallow layer formed in the substrate 1. Within the well 252. Further, among the pMIS 354 ρ and nMIS 354 η constituting the inverter circuit INV2 for preventing the deep n-type well 300 from being charged, the nMIS 354 η is formed in the shallow well 352 formed in the substrate 1 unlike the first embodiment. . Shallow p-type well 137166.doc • 34- 200950059 252, 352 are formed in the substrate 1 and are automatically electrically connected to the substrate 1, so that connection to the substrate 1 is not required by wiring. Other circuit configurations and the like are the same as in the first embodiment described above.

Figure 15 shows the pMIS 254p and nMIS including the inverter circuit INV1.

A cross-sectional view of the main part of the area of 254η. The gate electrode of the pMIS 254p formed in the shallow n-type well 251 is, for example, a structure in which a polycrystalline germanium film 503 to which a p-type impurity is added and a germanide layer 505 are laminated, and a gate of nMIS 254η formed in the shallow p-type well 252. The electrode electrode is, for example, a structure in which a polycrystalline ft w film 504 to which an n-type impurity is added and a vaporized layer 505 are laminated, and a gate electrode of the pMIS 254p and a gate electrode of the nMIS 254η are formed by a vaporization layer 505. And connected. Further, the gate electrode of the pMIS 254p and the gate electrode of the nMIS 254n are electrically connected to the shallow n-type well 251 by the first to eighth wirings M1 to Μ8. Further, the shallow p-type well 252 is formed in the p-type substrate 1 and is electrically connected to the substrate 1. (Embodiment 4) A semiconductor device having a triple well structure according to Embodiment 4 will be described with reference to Fig. 16 . Here, an example of implementing the first method for negative charging will be described. Fig. 16 is a circuit diagram showing an example of a 1/0 (input/output) circuit portion and a logic circuit portion of the circuit of the fourth embodiment which constitutes the audio image processing device of Fig. 1 described above. As shown in FIG. 16, since the shallow p type well 202 formed in the deep n-type well 200 and the shallow p type well 302 formed in the deep n type well 300 have a large area, if placed in the shallow p type well 202, 302 In the case of negative charging, the amount of charge will increase, which will easily cause insulation damage of MIS. Therefore, in order to prevent the negative p-type wells 202 and 302 from being negatively charged, an inverter circuit INV5 composed of pMIS 271p and nMIS 271η 137166.doc -35- 200950059 is formed in the deep n-type well 200, and is deep η-type well An inverter circuit 11'6 composed of pMIS 371p and 11]^118 3 7111 is formed in 300. In the inverter circuit 1]^¥5, the gate electrodes of 卩?418 271? and the gate electrodes of 111^18 27111 are processed while being connected, and the gate electrodes and the shallow n-type wells are connected. 201 is connected by the eighth layer wiring 272 (Μ8) of the uppermost layer. Similarly, in the inverter circuit INV6, the gate electrode of the pMIS 371p and the gate electrode of the nMIS 371 η are processed while being connected, and the gate electrode and the shallow n-well 301 are connected by the uppermost layer. The eighth layer wiring 3 72 (Μ8) is connected. The other wiring used to form the inverter circuit is performed by the first layer wiring. Other circuit configurations and the like are the same as in the above-described third embodiment. Next, the effects obtained by the fourth embodiment will be described. In the fourth embodiment, the gate electrode of the inverter circuit INV5 including the pMIS 271ρ and the nMIS 271n is maintained in a floating state until the step of forming the eighth layer wiring of the uppermost layer is performed, and thus The step of forming the connection hole in the interlayer insulating film on the seventh layer wiring is maintained between the shallow well 202 and the deep n well 200 via the shallow n-type well 201. As a result, the negative charge flowing into the shallow well 202 is discharged toward the substrate 1 via the shallow n-well 201 and the deep n-well 200. Similarly, the gate electrode of the inverter circuit INV6 composed of the pMIS 37 lp and the nMIS 37 In is maintained in a floating state until the step of forming the eighth layer wiring of the uppermost layer is performed, and thus is formed in the seventh The shallow p-type well 302 and the deep n-type well 300 are maintained in an ON state via the shallow n-type well 301 until the step of forming a connection hole in the interlayer insulating film on the layer wiring. The crucible flows into the shallow p-type 137166.doc -36- 200950059 The negative charge of well 3 02 is discharged toward the substrate 1 via the shallow n-type well 3 01 and the deep n-type well 300. Further, similarly to the above-described third embodiment, the positive charging of the deep n-type wells 200, 300 is also prevented. Thereby, the dielectric breakdown of the gate insulating film formed on the pMIS 203p or the nMIS 203n constituting the inverter circuit and the dielectric breakdown of the gate insulating film generated on the nMIS 308 can be suppressed. (Fifth Embodiment) A semiconductor device having a triple well structure according to the fifth embodiment will be described with reference to Figs. 17 to 19 . Here, an example of implementing the second method for positive charging will be described. Fig. 17 is a circuit diagram showing an example of a 1/〇 (input/output) circuit unit and a logic circuit unit of the audio image processing device of Fig. 1 of the fifth embodiment, and Fig. 18 is a view for explaining the application of the fifth embodiment. FIG. 19 is a cross-sectional view showing a circuit element of the MIS according to the second embodiment, and FIG. 19 is a schematic cross-sectional view showing the circuit element of the MIS according to the second embodiment. As shown in Fig. 17, in the deep n-type well 200, as in the second embodiment, the inverter circuit INV1 composed of the pMIS 254p and the nMIS 254n and the inclusive pMIS 254p are not formed, which does not contribute to the circuit operation. The n-type well 251 and the shallow p-type well 252 containing nMIS 254η. Instead of preventing the formation of the inverter circuit for charging, it is possible to prevent the application of a voltage to the gate insulating film of the pMIS 203p and the nMIS 203n constituting the inverter circuit even when the deep n-well 200 is charged, by the uppermost layer. The eighth layer wiring 3 (Μ8) is used to form the gate electrodes of the pMIS 203ρ and nMIS 203n constituting the inverter circuit and the gate of the nMIS 103!1 (the n-type semiconductor region formed in the shallow p-type well 102). connection. 137166.doc •37- 200950059 In the deep η-type well 300, the inverter circuit mv2 composed of PMIS 354ρ and nMIS 354η, the shallow n-type well 351 containing PMIS 354P, and the inner package nMls are not formed in the deep η-type well 300. Shallow p-well 352 of 354n. Further, the connection between the shallow p-well 304 and the substrate 进行 is performed by the eighth layer wiring 314 (M8) of the uppermost layer. Other circuit configurations and the like are the same as those in the first embodiment. Next, the effect obtained by the second method of the fifth embodiment will be described with reference to Fig. 18. Fig. 18 is a schematic cross-sectional view showing a state in which a semiconductor device is charged by plasma discharge in a step of forming a connection hole in an interlayer insulating film formed on a wiring of a seventh layer. In the stage of the manufacturing process (the step of forming a connection hole on the interlayer insulating film formed on the wiring of the seventh layer), the gate electrode of the pMIS 203p and the gate of the nMIS 2 311 constituting the inverter circuit The electrode electrode is not connected to the drain of the nMIS 103n located in the substrate 1, and the gate insulating film does not generate a potential difference, so that dielectric breakdown does not occur. In the other circuit components that are located in the deep n-type well and must be connected to the substrate 1, the eighth layer wiring is also used for wiring to the substrate 1, so that the insulation of the gate insulating film of MI s can be suppressed. damage. Further, in the step of forming the connection hole on the interlayer insulating film formed on the interlayer wiring of the seventh layer, the deep n-type well 2 is not connected to the substrate ^, thereby suppressing the gate of the MIS. Insulation damage of the insulating film. Further, in the step of forming the connection holes formed in the insulating film formed on the eighth layer wiring, the deep n-type well 200 has a small amount of charge, so that the MIS gate insulating film does not cause dielectric breakdown. Next, the effect of 137166.doc •38·200950059 obtained by the second method of the fifth embodiment will be described with reference to Fig. 19 . Fig. 19 is a schematic cross-sectional view showing the case where the deep n-well 300 is charged in the step of forming a connection hole in the interlayer insulating film formed on the wiring of the seventh layer. At this stage (the step of forming a connection on the interlayer insulating film formed on the wiring of the seventh layer), the shallow well 3〇4 is not connected to the substrate, so the deep η type well is entirely charged, and as a result, the whole is charged. The gate insulating film of nMIS 3G8 does not generate a potential difference, so that dielectric breakdown does not occur. In other circuit components φ, the dielectric breakdown of the MIS gate insulating film can also be suppressed. Further, in the step of forming the connection hole on the interlayer insulating film formed on the seventh layer wiring, the shallow p-type well 304 is also insulated from the substrate ,, thereby suppressing dielectric breakdown of the MIS gate insulating film . Further, similarly to the deep n-type well 2, in the step of forming the connection hole formed in the insulating film formed on the eighth layer wiring, the deep n-type well 300 has a small amount of charge, and thus the MIS gate insulating film No insulation damage will occur. Further, in the fifth embodiment, the case where the second method is applied to the connection between the gate electrode of the inverter circuit including the pMIS 2 and the φ nM1S 203n and the nMIS l〇3n is exemplified, and The connection between the shallow p-type well 304 in which nMls 3〇8 is formed and the substrate 1 is applied to the second method, but is not limited thereto. (Embodiment 6) A semiconductor device having a triple well structure according to Embodiment 6 will be described with reference to Fig. 20 . Here, another example of the first method different from the above-described embodiments 1, 2 and 3 for positive charging will be described. Fig. 20 is a circuit diagram showing an example of the I/O (input/output) electric power 137166.doc-39-200950059 road portion and logic circuit portion of the sixth embodiment which constitutes the audio image processing device of Fig. 1 described above. As shown in FIG. 20, among the PMIS 254p and the nMIS 254n constituting the inverter circuit INV1 for preventing the deep n-well 2〇〇 from being charged, the nMIS 25 is formed as the shallow P-well 252 is different from the above-described embodiment i. It is electrically connected to the shallow p-well 205 by the ith layer wiring 256 (M1). The shallow p-well 2〇5 is connected to the substrate 1 by the first layer wiring 206 (M1), so the shallow well 252 is indirectly connected to the substrate 1 via the shallow p-well 205. Further, among the pMIS 354P and nMIS 354n constituting the inverter circuit inv2 for preventing the deep n-well 300 from being charged, the shallow p-well 352 of #nMIS 354n is formed and the above embodiment! Differently, it is electrically connected to the shallow P-well 304 by the ith layer wiring 356 (mi). The shallow p-type well 3 is connected to the substrate 1 by the first layer wiring 305 (M1), so the shallow p-well 352 is indirectly connected to the substrate via the shallow p-well 408. Other circuit configurations and the like are the same as in the first embodiment described above. (Embodiment 7) A semiconductor device having a triple well structure according to Embodiment 7 will be described. In the above-described Embodiments i, 3 or 6, for example, the inverter circuit INV1 is used to cause the positive electric charge flowing into the well 2, the shallow n-well "I or the shallow P-well 202" toward the substrate due to the discharge of the plasma. In the seventh embodiment, the positive electric charge that has flowed into the deep n-type well is discharged to the substrate 1 by the inverter circuit INV2, but in the seventh embodiment, the inverter circuit can be obtained without using the inverter circuit. The charging response circuit having the same effects as those of the first, third or sixth embodiments will be described. Hereinafter, the fourth to thirteenth examples of the charging response circuit will be described. 'These examples are representative circuit configurations, of course, 137166 .doc • 40· 200950059 Various modifications can be made without departing from the spirit and scope of the invention. The charging response circuit of the first example of the seventh embodiment will be described. Fig. 21 is a schematic cross-sectional view showing the charging response circuit of the first example. A shallow n-type well 281 and a shallow p-type well 282 are formed in mutually different regions in the well 200, and an n-type semiconductor region 284n and a p-type semiconductor region 284p are formed in mutually different regions in the shallow n-type well 281. And The nMIS 285n is formed in the shallow p well 282. Further, the gate electrode of the nMIS 285η and the germanium semiconductor region 284ρ formed in the shallow n-well 281 are connected by the wiring 283a, and the nMIS w 285η has a drain and a shallow n-type. The n-type semiconductor region 284n formed in the well 281 is wired by the wiring 283b, and the source of the nMIS 285n is connected to the ground potential GND via the wiring 283c via the p-type semiconductor region 286 formed in the shallow p-well 282. The first wiring is used for the wirings 283a, 283b, and 283c. The charging response circuit of the first example is formed by the n-type semiconductor region 284n and the p-type semiconductor region 284p formed in the shallow n-well 281, and the shallow p-well. The nMIS 285 η formed in 282 does not have any effect in the circuit operation of the semiconductor device. For example, in the manufacturing step, when the plasma is discharged, the deep n-well 200 and the shallow n-well 281 are accumulated. When a large amount of positive charge is applied, the potential of the p-type semiconductor region 284p is substantially equal to the potential of the shallow n-type well 281 by the pn junction capacitance, etc., thereby applying a greater than the gate electrode of the nMIS 285n. Limit voltage potential When the nMIS 285 η is turned on, the positive charges flowing into the deep n-type well 200 and the shallow n-type well 281 are discharged to the ground potential GND via the wiring 283b, the nMIS 285n channel, the wiring 283c, and the p-type semiconductor region 286. The charging response circuit of the second example of 7 is explained. Fig. 22 137166.doc • 41 · 200950059 shows the schematic diagram of the charging circuit of the second example. The charging response circuit of the second example has the same circuit configuration as the charging response circuit of the first example, but differs from the charging response circuit of the first example in that the p-type semiconductor region 284p formed in the shallow n-well 281 The p-type semiconductor region 286 formed in the shallow p-type well 282 is wired by a wiring 287 which is a step subsequent to a step which may cause dielectric breakdown of the gate insulating film due to plasma discharge. Formed in the middle. This wiring is preferably carried out by wiring of the uppermost layer. By fixing the p-type semiconductor region 284p to the ground potential GND, the nMIS 285n is always turned off during the circuit operation of the semiconductor device, and the nMIS 285n is not adversely affected by leakage of other circuits. The charging response circuit of the third example of the seventh embodiment will be described. The charging response circuit of the third example has the same circuit configuration as that of the charging and discharging circuit of the first or second example described above, and the thickness of the gate insulating film of the nMIS 285n is set to a thickness of 1 〇 nm or more. For example, the thickness of the gate insulating film of the MISFET formed on the 1/0 (input/output) circuit portion may be the same. By forming the gate insulating film of the nMIS 285n to be thick, the leakage can be reduced and the operation can be reliably performed. The charging response circuit of the fourth example of the seventh embodiment will be described. 23(a) and 23(b) are a plan view and a cross-sectional view, respectively, of the charging response circuit of the fourth example. The charging response circuit of the fourth example has the same circuit configuration as the charging response circuit of the first example, but differs from the charging response circuit of the first example in that the wiring is not used for the wirings 283a, 283b, and 283c. A wiring formed of a conductor film 137166.doc • 42- 200950059 (for example, a laminated film of a polysilicon film and a germanide layer) in the same layer as the common contact and the gate electrode. That is, the gate electrode of the nMIS 285n and the p-type semiconductor region 284p formed in the shallow n-type well 281 are wired by the plug electrode PLG embedded in the connection hole CNT formed across the both. Further, the n-type semiconductor region 284n formed in the drain of the nMIS 28 5n and the shallow n-type well 281 forms a wiring 288a composed of a conductor film having the same layer as the gate electrode, and is buried by a plug electrode PLG that is inserted into the connection hole CNT formed between the drains of the wiring 288a and the nMIS 285n, and a plug that is buried inside the connection hole CNT formed between the wiring 288a and the n-type semiconductor region 284n. The electrode PLG is used for wiring. Further, the source of the nMIS 285η and the p-type semiconductor region 286 formed in the shallow p-type well 282 form a wiring 288b composed of a conductor film of the same layer as the gate electrode, and is buried therein. a plug electrode PLG inside the connection hole CNT formed across the source of the wiring 288b and the nMIS 285n, and a plug electrode buried inside the connection hole CNT formed across the wiring 288b and the p-type semiconductor region 286 PLG to wire. As described above, for example, even when the charging of the first layer wiring is caused by the plasma discharge, the wiring 283a, 283b, and 283c composed of the first layer wiring are not used in the charging countermeasure circuit, so that charging can be prevented. The charging response circuit of the fifth example of the seventh embodiment will be described. Fig. 24 is a cross-sectional view showing the charging circuit of the fifth example. The charging response circuit of the fifth example has the same circuit configuration as the charging response circuit of the first example, but differs from the charging response circuit of the first example in that the capacitive element CE formed on the shallow n-well 281 is used. Instead of the p-type semiconductor region 137166.doc -43- 200950059 284p. Similarly to the charging response circuit of the first example described above, for example, in the manufacturing step, when a large amount of positive charges are accumulated in the deep n-type well 200 and the n-type well 281 due to plasma discharge, the gate capacitance of the capacitive element CE is utilized. The potential of the gate of the capacitive element CE is substantially equal to the potential of the n-type well 28 1 . Thereby, when a potential greater than the threshold voltage is applied to the gate electrode of the nMIS 285η, the nMIS 285η is turned on, and the positive charges flowing into the deep n-well 200 and the shallow n-well 281 pass through the wiring 283b, nMIS 285η. The channel, the wiring 283c, and the p-type semiconductor region 286 are discharged toward the ground potential GND. The capacitor element CE can be composed of a shallow n-type well 281, an insulating film of the same layer as the gate insulating film of the nMIS 285n, and a conductor film of the same layer as the gate electrode of the nMIS 285n. The charging response circuit of the sixth example of the seventh embodiment will be described. Fig. 25 is a cross-sectional view showing the charging circuit of the sixth example. The charging response circuit of the sixth example has the same circuit configuration as the charging response circuit of the fifth example, but differs from the charging response circuit of the fifth example described above in the gate of the capacitive element CE formed on the shallow n-well 281. The p-type semiconductor region 286 formed in the pole and shallow p-well 282 is wired by a wiring 287 which is followed by a step which may cause dielectric breakdown of the gate insulating film due to plasma discharge. Formed in the steps. This wiring is preferably carried out by wiring of the uppermost layer. As described above, by fixing the gate of the capacitor element CE to the ground potential GND, the nMIS 285n is always turned off during the operation of the circuit, so that the nMIS 28 5n does not cause an adverse effect such as leakage of other circuits. The charging countermeasure circuit of the seventh example of the seventh embodiment will be described. Figure 137166.doc • 44- 200950059 26(a) and 26(b) respectively show a schematic cross-sectional view and an equivalent circuit diagram of the charged response circuit of the seventh example. The charging circuit of the seventh example has the same circuit configuration as the charging circuit of the fifth example, but differs from the charging circuit of the fifth example in that the gate capacitance Cc of the capacitive element CE is relative to the nMIS 285η. The gate capacitance Cg is set sufficiently large, and the input potential of the nMIS 285η (the potential applied to the gate electrode) can be followed by the coupling with respect to the potential (V(NW)) of the shallow n-well 28 1 . When the gate capacitance Cc of the capacitive element CE is smaller than the gate capacitance Cg of nMIS 285η (Cc "Cg", the voltage of the wiring 283a of the gate of the capacitive element CE and the gate electrode of the nMIS 285η (V(node_x)) Close to the ground potential GND. On the other hand, when the gate capacitance Cc of the capacitance element CE is larger than the gate capacitance Cg of the nMIS 285η (Cc "Cg), the potential of the gate of the capacitance element CE and the potential of the n-type well 281 (V(NW)) are substantially Equally, the potential of the shallow n-type well 281 (V(NW)) is applied to the gate electrode of the nMIS 285n via the wiring 283a. Thereby, the nMIS 285 η is easily turned on, and the positive charges flowing into the deep n-type well 200 and the shallow n-type well 281 are directed to the ground potential GND via the wiring of the wiring 283b, the nMIS 285n, the wiring 283c, and the p-type semiconductor region 286. Discharge. The charging response circuit of the eighth example of the seventh embodiment will be described. 27(a) and 27(b) are respectively a cross-sectional schematic view and an equivalent circuit diagram of the charging response circuit of the eighth example. The charging response circuit of the eighth example has the same circuit configuration as the charging response circuit of the fifth example, but differs from the charging response circuit of the fifth example described above in that it is complementary to the shallow n-type opposite to the capacitive element CE. The vacant layer 289 formed in the well 281 is reduced by the 137166.doc -45-200950059 gate capacitance Cc of the capacitive element CE, and the capacitive element CE in which the reduction is taken into account is designed. That is, when the depletion layer 289 is formed in the shallow n-well 281 opposite to the capacitance element CE, since the capacitance Cx of the depletion layer 289 is connected in series to the gate capacitance Cc of the capacitance element CE, the gate of the actual capacitance element CE is The pole capacitance is smaller than the gate capacitance Cc obtained according to the design size of the capacitive element CE. Therefore, the design of the capacitive element CE in which the amount of decrease in the gate capacitance Cc of the capacitive element CE due to the formation of the depletion layer 289 is taken into consideration is performed. The charging response circuit of the ninth example of the seventh embodiment will be described. 28(a) and 28(b) are respectively a cross-sectional schematic view and an equivalent circuit diagram of the charging response circuit of the ninth example. Further, 29(a) and 29(b) are respectively a schematic cross-sectional view and an equivalent circuit diagram showing a modification of the charging circuit of the ninth example. The charging response circuit of the ninth example has the same circuit configuration as the charging response circuit of the fifth example, but differs from the charging response circuit of the fifth example in that it is prevented from being shallow n-type with respect to the capacitive element CE. The depletion layer formed in the well 28 1 causes the gate capacitance Cc of the capacitive element CE to decrease, and a channel (inversion layer) is formed at a position opposite to the capacitive element CE at the shallow n-type well 281. Fig. 28 shows a charging countermeasure circuit in which a p-type semiconductor region 290 is formed in the n-type well 281 under the one side surface of the gate of the capacitor element CE. Fig. 29 shows a charging countermeasure circuit in which a p-type semiconductor region 290 is formed in the n-type well 28 1 under the side faces on both sides of the gate of the capacitor element CE. That is, when the depletion layer is formed in the shallow n-well 281 opposite to the capacitance element CE, since the capacitance of the depletion layer is connected in series to the gate capacitance Cc of the capacitance element CE, it is difficult to obtain a gate having a threshold of Nmis 285η. Capacitor 137166.doc -46- 200950059

Cg is a capacitive element CE of a sufficiently large gate capacitance Cc. Therefore, in order to prevent the formation of the depletion layer, a channel (inversion layer) is formed in advance with respect to the position of the shallow n-type well 281 opposite to the capacitive element CE, thereby preventing the gate of the capacitive element CE due to the formation of the depletion layer. The reduction of the pole capacitance Cc. The charging response circuit of the tenth example of the seventh embodiment will be described. 30(a) and 30(b) are cross-sectional views and equivalent circuit diagrams of the charging response circuit of the tenth example, respectively. The charging response circuit of the tenth example has the same circuit configuration as the charging response circuit of the first example, but differs from the charging response circuit of the first example in that the junction capacitance Cj of the p-type semiconductor region 284p is relative to the nMIS. The gate capacitance Cg of 285η is designed to be sufficiently large, and the input potential of nMIS 285η (the potential applied to the gate electrode) can be followed by the coupling with respect to the potential (V(NW)) of the shallow n-type well 281. When the junction capacitance Cj of the p-type semiconductor region 284p is larger than the gate capacitance Cg of Nmis 285η (Cj"Cg), the potential of the gate of the capacitive element CE is substantially equal to the potential of the n-type well 281 (V(NW)). The potential (V(NW)) of the shallow n-well 281 is applied to the gate electrode of Nmis 285n via wiring 283a. Thereby, the nMIS 285η is easily turned on, and the positive charges flowing into the deep n-type well 200 and the shallow n-type well 281 are directed to the ground potential via the wiring of the wiring 283b, the nMIS 285n, the wiring 283c, and the p-type semiconductor region 286. GND discharge. The charging response circuit of the eleventh example of the seventh embodiment will be described. Fig. 3 is a schematic cross-sectional view showing the charging response circuit of the eleventh example. The charged response circuit of the eleventh example is formed by a shallow n-type well 281 and a shallow p-type well 282 in a different region of the deep n-type well 200, and nMIS 285η is formed in the shallow p-type well 282, but Only the n-type semiconductor region 284n is formed in the shallow n-well 281. 137166.doc •47· 200950059 Further, the n-type semiconductor region 284η formed in the drain of the nMIS 28511 and the shallow n-type well 281 is connected by the wiring 283b, and the source of the nMIS 28 5n is connected via the wiring 283c via the shallow p-type The p-type semiconductor region 286 formed in the well 282 is connected to the ground potential GND, and a floating wiring 291 is connected to the gate electrode of the nMIS 285n. When the nMIS 285η is turned on according to the intermediate potential of the wiring 291 in the floating state, the positive charges flowing into the deep n-well 200 and the shallow n-well 281 pass through the wiring of the wiring 283b, the nMIS 285n, the wiring 283c, and the p-type semiconductor. The region 286 is discharged toward the ground potential GND. In the step of the wiring 29 1 which may cause dielectric breakdown of the gate insulating film due to plasma discharge, the potential for turning off the nMIS 285η is applied, so that the nMIS 285η does not leak to other circuits, etc. Bad effects. The charging response circuit of the twelfth example of the seventh embodiment will be described. Figure 32 is a cross-sectional view showing the charging response circuit of the twelfth example. The charging response circuit of the twelfth example has the same circuit configuration as the charging response circuit of the eleventh example, but differs from the charging response circuit of the eleventh example in that the gate electrode of the nMIS 285n and the shallow p-well 282 are The formed p-type semiconductor region 286 is wired by a wiring 292 which is formed in a step subsequent to the step of causing dielectric breakdown of the gate insulating film due to plasma discharge. This wiring is preferably carried out by the wiring of the uppermost layer. By fixing the gate electrode of the nMIS 285n to the ground potential GND, the nMIS 285η is always turned off during the operation of the circuit of the semiconductor device, and the nMIS 285η is not adversely affected by leakage to other circuits. 137166.doc -48· 200950059 The power supply circuit of the j3th example of the seventh embodiment will be described. The charging ground of the first to the twelfth examples is a response circuit for the electric power generated in the deep n-type well 200, and the response circuit for the dead body generated by the ice p-type well is also It can be formed in the same manner by inverting the polarity of the cypress. That is, on

Said the first! In the charging response circuit of the example to the twelfth example, shallow n-type wells 281 and shallow p-type wells are formed in different regions of the deep p-type wells, and the shallow p-type wells are formed in 2 to eliminate the interwells. The potential difference is -285n, and the shallow n-type well 281 is used as the charging response well', but in the charged response circuit of the third example, the shallow p-type well and the shallow n-type are formed in different regions of the deep η-type well. The well 'in the shallow n-type well forms a pms that eliminates the potential difference between wells, and the shallow P-type well is used as a charging response well. Furthermore, to explain the above! In the case of a defective generation mechanism, an inverter composed of a pMIS (not shown) formed in the shallow n-type well 101 formed on the substrate 1 and an nMIS (not shown) formed in the shallow p-type well 1〇2 is described. The circuit, in particular, refers to an inverter circuit as described below. Figure 33 is a cross-sectional view showing the inverter circuit. Shallow n-type wells 1〇1 and shallow p-type wells 2 are formed in different regions of the substrate 1, and pMIS is formed in the shallow n-type well 1〇1, and is in the shallow p-type well 1〇2 Formed with nMIS. An inverter circuit is formed by the PMIS and nMIS, and the gate electrode of the pMIS and the gate electrode of the nMIS are connected to each other and are in a floating state. The invention has been described in detail with reference to the embodiments, and the invention is not limited thereto, and various modifications can be made without departing from the spirit and scope of the invention. [Industrial Applicability] 137166.doc -49- 200950059 The present invention is applicable to, for example, an effective technique applied to a semiconductor device having a triple well structure employed in a general-purpose soc product. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram of a sound image processing apparatus used by the inventors of the present invention for analysis; Fig. 2 is a diagram showing the composition! A circuit diagram of an example of a circuit portion and a logic circuit portion of the audio image processing device; FIG. 3 is a schematic cross-sectional view showing a circuit component of a third defect generating mechanism when a positive charge is accumulated in a deep well; 4(a) and 4(b) are diagrams for explaining the flow of charges in the inverter circuit; FIG. 5 is a circuit element for explaining the second defective generation mechanism when a positive charge is accumulated in the deep well. FIG. 6 is a circuit diagram showing another example of a 1/〇 (input/output) circuit unit and a logic circuit unit constituting the audio image processing apparatus of FIG. 1. FIG. 7 is a view for explaining that it is formed in a deep well and has a substrate. A schematic cross-sectional view of a circuit element of a third defect generating mechanism in which a negative charge is accumulated in a shallow well of the same conductivity; FIG. 8 is a view showing a negative charge accumulated in a shallow well formed in a deep well and having the same conductivity as the substrate FIG. 9 is a cross-sectional view showing a circuit component of the fourth defect generating means in the first embodiment; FIG. 9 is a view showing one of the 1/〇 (input/output) circuit unit and the logic circuit unit of the audio image processing device according to the first embodiment. Fig. 10 is a cross-sectional view showing a principal part of a region including the pMIS and nMIS constituting the inverter 137166.doc-50-200950059 of the first embodiment. Fig. 11 is a view for explaining the present invention. FIG. 12 is a schematic cross-sectional view showing a circuit element of the MIS to which the first method is applied according to the first embodiment; FIG. 12 is a cross-sectional view showing the circuit element of the MIS according to the first embodiment; Fig. 14 is a circuit diagram showing an example of a 1/〇 (input/output) circuit unit and a logic circuit unit of the audio image processing device of the second embodiment; Fig. 14 is a diagram showing the response of the audio image processing device of the third embodiment. FIG. 15 is a cross-sectional view showing a principal part of a region including a pMIS and an nMIS which constitute an inverter circuit to which the first method is applied, and FIG. 15 is a cross-sectional view showing a portion of a circuit portion and a logic circuit portion of the inverter circuit according to the third embodiment; A circuit diagram of an example of a 1/◦ (input/output) circuit unit and a logic circuit unit of the audio image processing device; FIG. 17 shows a 1/〇 (input) of the audio image processing device of the fifth embodiment. FIG. 18 is a schematic cross-sectional view showing a circuit element of an inverter circuit to which the second method is applied in the fifth embodiment; FIG. 19 is a view for explaining the present embodiment. FIG. 20 is a circuit diagram showing an example of a 1/0 (input/output) circuit unit and a logic circuit unit of the audio image processing device according to the sixth embodiment; Figure 21 is a cross-sectional view showing a charging response circuit according to a first example of the seventh embodiment; and Figure 22 is a cross-sectional view showing a charging response circuit of a second example of the seventh embodiment. 137166.doc -51· 200950059

Electric response

23(a) and 23(b) are a plan view and a cross-sectional view, respectively, of a circuit with a fourth example of the seventh embodiment; and FIG. 24 is a cross-sectional view of the charging circuit of the fifth example of the seventh embodiment; FIG. 26(a) and FIG. 26(b) are respectively a schematic cross-sectional view and an equivalent circuit diagram of a circuit with a seventh example of the seventh embodiment;

27(a) and 27(b) are respectively a cross-sectional view and an equivalent circuit diagram of a tape circuit of an eighth example of the seventh embodiment; and Figs. 28(a) and 28(b) are respectively a seventh embodiment. FIG. 29(a) and FIG. 29(b) are respectively a schematic cross-sectional view and an equivalent circuit diagram of the electrical response circuit of the ninth example of the seventh embodiment;

30(a) and 30(b) are respectively a schematic cross-sectional view and an equivalent circuit diagram of a charging countermeasure circuit according to a seventh embodiment of the present invention; and FIG. 31 is a diagram showing a charging response circuit of a fifth example of the seventh embodiment; Figure 32 is a cross-sectional sound map of the charging response circuit of the twelfth example of the seventh embodiment; and the heart chart 33 is a schematic cross-sectional view for explaining the guiding circuits of the shallow n-type well and the shallow (four) well. [Main component symbol description] 137l66.doc -52· 200950059 1 Substrate 2 ' 3 Wiring 101 shallow n-well 102 shallow well 103 η channel type MIS_FET 1〇3ρ ρ channel type MIS_FET 200 deep n-well 201 shallow n-type Well w 202 shallow p type well 203η n channel type MIS_FET 203ρ ρ channel type MIS_FET 204 shallow n type well 205 shallow well type 206 wiring 207η n channel type MIS'FET 〇207Ρ ρ channel type MIS_FET 208 > 209 wiring 251 shallow η Well. 252 Shallow p type well 253 Wiring 254η η channel type MIS_FET 254ρ ρ channel type MIS_FET 255 ' 256 wiring 271η n channel type MIS_FET 137166.doc -53 -

200950059 271ρ p-channel type MIS FET 272 wiring 281 shallow n-well 282 shallow p-well 283a, 283b, 283c wiring 284n n-type semiconductor region 284p p-type semiconductor region 285n n-channel type MIS FET 286 p-type semiconductor region 287 wiring 288a, 288b Wiring 289 Depletion layer 290 P-type semiconductor region 291, 292 Wiring 300 Deep η-type well 301 Shallow η-type well 302 Shallow-p-type well 303 Shallow η-type well 304 Shallow-type well 305 Wiring 306n η-channel type MIS_FET 306p ρ-channel type MIS'FET 307n n-channel type MIS'FET 307p ρ channel type MIS'FET 137166.doc ·54- 200950059 1010 308 n channel type MIS_FET 309η n channel type MIS_FET 309ρ p channel type MISTET 310, 311, 312, wiring 313 ' 314 351 shallow n-well 352 shallow p-type well 353 wiring 354η n-channel type MIS_FET 354ρ p-channel type MIS_FET 355 ' 356 wiring 371η n-channel type MIS_FET 371ρ p-channel type MIS_FET 372 wiring 503, 504 polysilicon film (gate electrode) 505 Telluride layer C capacitor Cc gate capacitance CE capacitance element Cg gate capacitance Cj junction capacitor CNT connection hole D bungee G gate electrode 137166.doc -55- 200950059

GND

INV1, INV2, INV3, INV4, INV5, INV6 IO LSI

Ml, M2, M3, M4, M5, M6, M7, M8 n-well p-sub p-well

PLG

S Ground potential Inverter circuit I/O circuit part Sound image processing device Wiring η type well Substrate Ρ type well Plug electrode source 137166.doc -56-

Claims (1)

200950059 VII. Patent application scope: 1. A semiconductor device comprising: a first conductivity type substrate; and a second conductivity type deep well different from the first conductivity type, formed in the upper and the substrate; & a first shallow well of a first conductivity type and a second shallow well of a second conductivity type are formed in different regions of the deep well; and an inverter circuit is formed by the second conductive layer formed in the ith shallow well a second field effect transistor of the type and a first field effect transistor formed of the second conductivity type formed in the second shallow well; wherein the first gate electrode of the first field effect transistor and the second field The second gate electrode of the effect transistor is directly or indirectly connected to the substrate, the portion having the substrate potential, the shallow well of the deep well, the second conductivity type, the shallow well of the second conductivity type, or the circuit operation using the second wiring. The first shallow well is directly or indirectly connected to the substrate or a portion having a substrate potential by using the second wiring of the lower layer of the second wiring, and the first wiring is directly above the first wiring. The number of connecting holes formed in the edge of the film, the first wiring and the lower layer wiring line positive number smaller compared to the connection holes formed in the insulating film of the above. 2. The semiconductor device of claim 1, wherein the first wiring is the uppermost wiring. 3. The semiconductor device of claim 1, wherein the second wiring system is a first layer wiring 0 137166.doc 200950059. 4. The semiconductor device of the request, wherein the deep well is not wired to the substrate. 5. The semiconductor device according to claim 1, wherein the first gate electrode of the (fourth) effect transistor and the second gate electrode of the second field effect transistor form the gate electrode and the second gate electrode together The same layer of conductive material is connected. 6. The semiconductor device of the present invention, wherein the first gate electrode of the second effect transistor comprises a laminate film of a second conductivity type tantalum film and a germanide layer, and the second gate of the second % effect transistor The electrode includes a second conductivity type tantalum film and a buildup film of the same layer as the telluride layer, and a second gate electrode of the first field effect transistor and the second field effect transistor The gate electrodes are connected by the above-described telluride layer. 7. In the semiconductor device of claim 1, the inverter circuit of # does not contribute to the circuit operation. 8. The semiconductor device according to claim 1, wherein the electric charge flowing into the deep well or the second shallow well is discharged to the substrate or a portion having a substrate potential via the second shallow well and the second wiring. A semiconductor device comprising: a first conductivity type substrate; a second conductivity type deep well different from the first conductivity type formed in the substrate; and a first conductivity type first shallow well formed a second shallow well of the second conductivity type formed in the deep well; and a 137166.doc 200950059 inverter circuit formed by the second shallow well in the region other than the deep well in the substrate; a second field effect transistor of a conductivity type and a first field effect transistor of a first conductivity type formed in the second shallow well; wherein the first gate electrode of the first field effect transistor and the second The second gate electrode of the field effect transistor is directly or indirectly connected to the substrate, the portion having the substrate potential, the deep well, the shallow well of the first conductivity type, the shallow well of the second conductivity type, or the circuit operation using the first wiring. Wiring specific parts, The number of the connection holes formed in the insulating film directly above the first wiring is smaller than the number of the connection holes formed on the insulating film directly above the wiring of the lower portion of the first wiring. 10. In the semiconductor device of claim 9, the wiring of the uppermost layer of the above-mentioned first wiring is #. 11. The semiconductor device of claim 9, wherein the deep substrate does not have the above substrate wiring. 12. The semiconductor device according to claim 9, wherein the first gate electrode of the fourth effect transistor and the second gate electrode of the second field effect transistor are formed into the first and second interrogating electrodes Conductive I material of the same layer of the electrode 13. The semiconductor device of claim 9 wherein the ith field effect == the chiplet layer containing the i-th conductivity type: the layer film, the second layer of the effect transistor The closed electrode includes a film of the second conductivity type and a laminate film of the same layer as the upper layer, and the first gate electrode of the first field effect transistor and the second phase effect of the work The second gate electrode of the transistor 137166.doc 200950059 is connected by the above-described telluride layer. 14 15 16 The semiconductor device of claim 9, wherein the inverter circuit does not contribute to circuit operation. The semiconductor device of claim 9, wherein the electric charge flowing into the deep well or the second shallow well is discharged to the substrate via the shallow shallow well. A semiconductor device comprising: a substrate of a first conductivity type; a deep well of a second conductivity type different from the first conductivity type formed in the substrate; and a second shallow well of the second conductivity type formed on the substrate In the deep well; a shallow well of a first conductivity type formed in a region other than the above-mentioned shallow well in the deep well, and one or more of the four potentials having the substrate potential, the deep well, and one or more The second conductivity type shallow wells are not connected; and the reverse phase 15 circuit 'the second field effect transistor of the second conductivity type formed in the first shallow well and the second shallow well formed in the second shallow well! a first field effect transistor of a conductivity type; wherein the gate electrode of the first field effect transistor and the second electrode of the second field effect transistor are directly or indirectly connected using the ith wiring The above-mentioned substrate, the above-mentioned one or a plurality of parts having a substrate potential, the two deep wells, and the shallow well of the first conductivity type, the above! One or a plurality of shallow wells of the second conductivity type or a specific portion of the circuit operation, and the number of connection holes formed on the insulating film directly above the first wiring is directly above the wiring of the lower layer of the first wiring The number of connection holes formed by 137166.doc 200950059 on the insulating film is relatively small. 17. The semiconductor device of claim 16, wherein the ith wiring is the uppermost wiring. 18. The semiconductor device of claim 16, wherein the first gate electrode of the second field effect transistor and the second gate electrode of the second field effect transistor form the first and second gates together The conductive material of the same layer of the electrode is connected. 19. 20. The semiconductor device of claim 16, wherein the first gate electrode of the second field effect transistor comprises an interlayer film of an eta conductivity type germanium film and a germanide layer, and the second gate of the second field effect transistor The pole electrode includes a laminated film of a second conductivity type and a layered film of a layer of the above-mentioned layer of the lithiation layer (10), a first gate electrode of the first % effect transistor and the second field effect transistor The second gate electrode is connected by the telluride layer. The semiconductor device of claim 16, wherein the inverter circuit does not contribute to circuit operation. The semiconductor device according to claim 16, wherein the charge flowing into the shallow well is discharged to the substrate via the second shallow well and the deep well. A semiconductor device comprising: a substrate of a first conductivity type; a deep well of a second conductivity type different from the first conductivity type, formed in the substrate; and a first conductivity type! a shallow well and a second shallow enthalpy of a second conductivity type formed in different regions of the deep well; and an inverter circuit formed by the second conductivity type 137166.doc 200950059 formed in the ith shallow well a second field effect transistor and a first field effect transistor formed of the second conductivity type formed in the second shallow well; wherein the gate electrode of the first field effect transistor and the second field effect transistor The gate electrode is directly or indirectly connected to the substrate, the portion having the substrate potential, or the portion having the power supply potential by using the second wiring, and the number of the connection holes formed on the insulating film directly above the first wiring is The number of connection holes formed in the insulating film directly above the wiring of the lower layer of the first wiring is smaller than that of the first wiring. 23. 24. A semiconductor device comprising: a substrate of a first conductivity type; a deep well of a second conductivity type different from the first conductivity type, formed in the substrate; and a first conductivity type a shallow well and a second shallow well of a second conductivity type formed in the deep well; wherein at least one of the deep well, the first shallow well, and the second shallow well is directly or indirectly connected to the first wiring using the first wiring The substrate or the portion having the substrate potential is connected to the insulating film formed on the insulating film directly above the first wiring, and is connected to the insulating film directly above the wiring of the lower portion of the first wiring. The number is relatively small. A semiconductor device according to claim 22 or 23, wherein said i-th wiring is a wiring of an uppermost layer. A semiconductor device comprising: a first conductivity type substrate; 137166.doc 200950059 a second conductivity type deep well different from the first conductivity type, formed in the substrate; and a first shallow well of the first conductivity type And a second shallow well of the second conductivity type, which is formed in a region different from each other in the deep well; wherein a portion in the second shallow well is between the substrate or a portion having a substrate potential 1 wiring is directly or indirectly connected, and the number of the connection holes formed in the insulating film directly above the first wiring is 'the connection hole formed on the insulating film directly above the wiring below the first wiring The number is less than the number. 26. A semiconductor device comprising: a substrate of a first conductivity type; a deep well of a second conductivity type different from the first conductivity type, formed in the substrate; and a second shallow well of the second conductivity type Formed in the deep well; and φ the first shallow well of the first conductivity type formed in a region other than the second shallow well in the deep well, and one or a plurality of wells having a substrate potential, the deep well or 1 The plurality of shallow wells of the second conductivity type are not connected to each other; wherein the portion in the first shallow well and the substrate, the one or the plurality of portions having the substrate potential, or the one or more (2) The portions in the shallow wells of the conductive type are directly or indirectly connected by the first wiring, and the number of the connection holes formed on the insulating film directly above the first wiring is I37166.doc 200950059 and the first The number of connection holes formed on the insulating film directly above the wiring of the lower layer is less. The semiconductor device of claim 25 or 26, wherein the jth wiring is the uppermost wiring. A semiconductor device comprising: a substrate of a first conductivity type; a deep well of a second conductivity type different from the first conductivity type, formed in the substrate; and a first shallow well of the first conductivity type and a second conductivity type a second shallow well formed in a different region of the deep well; and a second conductivity type field effect transistor formed in the shallow well; wherein the field effect transistor has a drain The second shallow well connection, the first shallow well and the ground potential wiring, the gate electrode of the field effect transistor is directly or indirectly connected to the second shallow well, and the field effect transistor corresponds to the charge amount of the second shallow well Become in the on state or off state. (4) The semiconductor device of claim 28, wherein the ii layer wiring is used to electrically connect the gate of the field effect transistor to the second shallow well, and the shallow well is connected to the ground potential. The semiconductor device according to claim 28, wherein in the second shallow well, the first semiconductor region of the third IV type is further included, and the first semiconductor region is formed by using the second wiring and the gate electrode of the field effect transistor. Electrical connection. The semiconductor device of claim 28, wherein the i-th semiconductor region of the i-th conductivity type is further scooped in the second shallow well, and the second semiconductor region is used with the second wiring and the field effect The gate electrode of the transistor is electrically connected, and the first semiconductor region is electrically connected to the ground potential by using the first wiring of the upper layer of the second wiring. The semiconductor device of claim 28, wherein the second shallow well further comprises an i-th semiconductor region of an ith conductivity type, wherein the p-semiconductor region and the gate electrode of the field effect transistor are buried by a person And the plug electrodes formed inside the connection holes formed by the two are connected. The semiconductor device according to claim 28, further comprising a capacitor element formed of the closed well formed by the first well, the second shallow well, and the domain insulating film, and the gate of the capacitor The second wiring is used to electrically connect to the gate electrode of the field effect transistor. 34. The semiconductor device of claim 28, further comprising an insulating film formed on the second shallow well and the second shallow well, and a gate formed by forming a gate of φ on the insulating film, μ, +· The β β pen member, wherein the gate of the capacitor element is electrically connected to the gate electrode of the field effect transistor by using the second wiring, and the second layer of the capacitor element is used in the upper layer. Wiring is electrically connected to the ground potential. 35. The semiconductor device of claim 28, further comprising a capacitor element formed by the second shallow well, the insulating film formed on the second shallow well, and the gate formed on the insulating film, the capacitor The gate of the device is electrically connected to the pole electrode between the field effect transistors by using the second wiring, and the gate capacitance of the 7L device is larger than the capacitance of the field effect transistor between the electrodes 137166.doc 200950059. The semiconductor device according to claim 28, further comprising: a capacitor formed by the shallow well, the insulating yoke formed on the second shallow well, and the insulating element formed on the insulating film, wherein the capacitive element is used between the capacitors The second wiring is electrically connected to the gate electrode of the field effect transistor, and the gate capacitance of the capacitance element is connected in series with the capacitance of the depletion layer formed in the second shallow well at the closed end of the capacitance element. The capacitance obtained is greater than the gate capacitance of the field effect transistor described above. The semiconductor device according to claim 28, further comprising: a capacitor formed by the gate formed on the insulating film formed by the second shallow well and the second shallow well, and the gate of the capacitor The second wiring is electrically connected to the gate electrode of the field effect transistor, and the inversion layer is formed in the second shallow well under the gate of the capacitor element, and the gate capacitance of the capacitor element is larger than the field The gate capacitance of the effect transistor. 38. The semiconductor device according to claim 28, wherein in the second shallow well, the third semiconductor region of the first conductivity type is further included, and the first semiconductor region is connected to the gate of the field effect transistor by using the second wiring. The pole electrode is electrically connected, and a junction capacitance of the first semiconductor region and the second shallow well is greater than a gate capacitance of the field effect transistor. A semiconductor device comprising: a first conductivity type substrate; and a second conductivity type deep well different from the ith conductivity type, formed in the above-mentioned 137I66.doc •10-200950059 substrate; The first shallow well of the electric type and the second shallow well of the second conductivity type are formed in different regions in the deep well; and a field effect transistor of the second conductivity type is formed in the first well; • Where • The bungee of the above field effect transistor is connected to the above 2nd shallow well, the above! The shallow well and the ground potential wiring are connected to the gate electrode of the field effect transistor and the floating wiring. The field effect transistor is turned on or off depending on the intermediate potential of the wiring in the floating state. 40. The semiconductor device according to claim 39, wherein the gate electrode of the field effect transistor is connected to the second shallow well using the first layer wiring, and the shallow well is connected to the ground potential. In the semiconductor device of the ejection length item 39, the wiring in the floating state described above is a potential for applying the field effect transistor to the off state by the wiring of the floating (4) wiring. According to the semiconductor device of claim 39, the closed-electrode electrode of the field effect transistor is electrically connected to the ground potential by using the third wiring of the wiring in the floating state. The semiconductor device of claim 31 or 34, wherein the g-th line is the wiring of the uppermost layer. The semiconductor device according to any one of claims 3, 3, or 33 to %, wherein the second wiring is the first layer wiring. The semiconductor device of claim 42, wherein the third wiring is the uppermost wiring. 137166.doc • 11 -