TWI581372B - Nonvolatile memory device and fabricating method thereof - Google Patents

Description

Non-volatile memory element and manufacturing method thereof

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a non-volatile memory device and a method of fabricating the same.

Since the non-volatile memory element has the function of storing data in the power-off state, it has been widely used in the industry. The non-volatile memory element can be generally classified into a floating gate structure and a yttrium-yttria-yttria-yttria-yttria-ytterbium structure (hereinafter referred to as a SONOS structure).

The floating gate structure uses source-Side Injection (SSI) or tunneling effect to store the hot electrons in the floating gate structure. However, as critical dimensions are gradually reduced, the application of floating gate structures is limited due to the problem of hot electrons punching through along the select gate channel. The SONOS structure uses source implantation to store hot electrons in the tantalum nitride layer. Since the SONOS structure has a smaller critical size than the floating gate structure. Therefore, the SONOS structure has a tendency to gradually replace the floating gate structure.

However, the conventional SONOS non-volatile memory element still has considerable room for improvement in improving the writing/erasing speed of non-volatile memory, reducing voltage operation, and improving component reliability.

Therefore, there is a need to provide an advanced non-volatile memory component and its system. A method to solve the problems faced by conventional technology.

One aspect of the invention is to provide a non-volatile memory component comprising a substrate, a gate electrode, a single charge trapping wall, and a source/drain region. The gate electrode is above the substrate and is electrically isolated from the substrate. A single charge trapping wall abuts a sidewall of the gate electrode and is electrically isolated from the substrate and the gate electrode and has a non-flat angle with the substrate. The source/drain regions are located in the substrate and are adjacent to the gate electrode.

In an embodiment of the invention, a single charge trapping wall is located between the substrate and the gate electrode.

In an embodiment of the invention, the single charge trapping wall has an L-shaped or I-shaped cross section.

In an embodiment of the invention, the non-flat angle between the single charge trapping vertical wall and the substrate is substantially greater than 0° and less than or equal to 90°.

In an embodiment of the invention, the non-volatile memory device further includes a first dielectric material layer for isolating the substrate and the gate electrode, and a second dielectric material layer for isolating the gate electrode and A single charge captures the vertical wall.

In an embodiment of the invention, the single charge trapping vertical wall is made of tantalum nitride; the first dielectric material layer and the second dielectric material layer are both yttria layers.

In an embodiment of the invention, the non-volatile memory element further includes a spacer located on a sidewall of the single charge trapping wall away from the gate electrode.

Another aspect of the present invention is to provide a non-volatile memory element comprising a plurality of columns of the aforementioned non-volatile memory elements and arranged in a plurality of rows and a plurality of columns.

In an embodiment of the invention, the source/drain regions of two adjacent non-volatile memory elements are partially overlapped to form a common source/drain region.

In an embodiment of the invention, two adjacent non-volatile memory elements Two single charge trapping layers are located on opposite sides of the corresponding gate electrode.

Yet another aspect of the present invention provides a method of fabricating a non-volatile memory device comprising the steps of first forming a first dielectric material layer and a gate electrode layer on a substrate. Then, the gate electrode layer and the first dielectric material layer are patterned to form a gate structure. Then, a second dielectric material layer and a charge trapping layer are sequentially formed to cover at least one sidewall of the gate structure. A portion of the charge trapping layer and a portion of the gate structure are removed to form a single charge trapping vertical wall adjacent the sidewalls of the remaining gate structures. Subsequently, a source/drain region is formed in the substrate adjacent to the remaining gate structure.

In an embodiment of the invention, the step of patterning the gate electrode layer and the first dielectric material layer comprises: first etching the gate electrode layer to form a gate electrode; and then using the gate electrode as a mask, facing the first The dielectric material layer is isotropically etched to form an undercut at the bottom of the gate structure.

In an embodiment of the invention, the step of forming the second dielectric material layer does not fill the undercut gap; the side etch gap is filled by the subsequently formed charge trapping layer.

In an embodiment of the invention, the step of removing a charge trap layer includes: patterning the charge trap layer to form a first single charge trapping vertical wall adjacent to the first sidewall of the gate structure, and adjacent to the gate A second single charge of the second sidewall of the structure captures the riser.

In an embodiment of the invention, the step of removing a portion of the gate structure includes patterning the gate structure to distinguish it into a first portion of the gate structure including the first sidewall and the first single charge trapping vertical wall, And a second portion of the gate structure including the second sidewall and the second single charge trapping vertical wall.

In an embodiment of the invention, the method for fabricating the non-volatile memory device further includes: forming a first spacer, adjacent to the first portion of the gate structure and the first single charge trapping; and forming the second spacer Adjacent to the second part of the gate structure and Two single charges capture the vertical wall.

In an embodiment of the invention, the step of forming a source/drain region includes performing at least one ion implantation process to form a common source between the first portion of the gate structure and the second portion of the gate structure / bungee area.

According to the above embodiments, the present invention provides a programmable non-volatile memory element and a method of fabricating the same. The programmable non-volatile memory element has an asymmetrical structure that includes a single charge trapping wall adjacent one of the sidewalls of the gate electrode. Wherein, the gate electrode is located above the substrate and is electrically isolated from the substrate. A single charge captures the vertical wall, is electrically isolated from the substrate and the gate electrode, and has a non-flat angle with the substrate.

Since the non-volatile memory element has only a single charge trapping wall, when the non-volatile memory element is programmed, there is no phenomenon of leaving electrons on the side without the charge trapping layer. When reading data, you only need to give a small bias to get enough read current. It not only does not affect the reading of non-volatile memory components, but also reduces the leakage current and breakdown voltage of non-volatile memory components, and improves the problem of excessive operating voltage and current consumption during reading, and is less likely to be around Component interference can reduce component energy consumption. It also reduces source/drain doping, reduces short-channel effects and hot-carrier effects, and facilitates miniaturization of critical dimensions of components.

100‧‧‧Non-volatile memory components

100'‧‧‧ Non-volatile memory components

101‧‧‧Substrate

102‧‧‧First dielectric material layer

103‧‧‧ gate layer

104‧‧‧ gate electrode

105‧‧‧Side etching opening

106‧‧‧Second dielectric material layer

106'‧‧‧ Thin layer of cerium oxide

107‧‧‧layer of tantalum nitride

108‧‧‧ Third dielectric material layer

109‧‧‧Lightly doped region

110‧‧‧ spacer

111‧‧‧Bungee Area

112‧‧‧ source area

113‧‧‧Charge capture vertical wall

113’‧‧‧Charge capture vertical wall

114‧‧‧ gate structure

114a‧‧‧ sidewalls of the gate structure

114b‧‧‧ sidewalls of the gate structure

115‧‧‧Non-flat angle

200a‧‧‧Non-volatile memory components

200b‧‧‧ non-volatile memory components

204a‧‧ ‧ gate electrode

204a1‧‧‧ sidewall of the gate electrode

204b‧‧‧ gate electrode

204b1‧‧‧ sidewall of the gate electrode

209a‧‧‧Light 汲 polar zone

209b‧‧‧Light 汲 polar zone

210a‧‧‧ clearance

210a1‧‧ 二2 layer

210a2‧‧‧ dielectric material layer

210b‧‧‧ spacer

210b1‧‧ 二2 layer

210b2‧‧‧ dielectric material layer

211‧‧‧Shared source/bungee area

212a‧‧‧ source area

212b‧‧‧Bungee Area

213a‧‧‧Single charge capture vertical wall

213b‧‧‧Single charge capture vertical wall

214a‧‧‧The first part of the gate structure

214a1‧‧‧The first part of the gate structure exposed to the outer side wall

214b‧‧‧Second part gate structure

214b1‧‧‧The second part of the gate structure exposed to the outer side wall

215a‧‧‧Non-flat angle

215b‧‧‧Non-flat angle

The above and other objects, features, and advantages of the present invention will become more apparent and understood. In one embodiment of the invention, a schematic cross-sectional view of a process structure for fabricating a non-volatile memory device is shown.

1H' is a cross-sectional view showing the structure of a non-volatile memory element according to another embodiment of the present invention.

2A through 2B are cross-sectional views showing a process structure for fabricating a non-volatile memory element, in accordance with still another embodiment of the present invention.

The invention provides a non-volatile memory element, which solves the problems of high operating voltage and current, easy to interfere with peripheral components, and easy to cause short channel effect and hot carrier effect, resulting in component breakdown. The above and other objects, features and advantages of the present invention will become more <

1A to 1H are schematic cross-sectional views showing a process structure for fabricating a non-volatile memory device 100 according to an embodiment of the invention. The non-volatile memory device 100 is formed by the following steps: First, a first dielectric material layer 102 and a gate layer 103 are formed on the substrate 101 (as shown in FIG. 1A). In some embodiments of the invention, substrate 101 comprises a p-type well substrate. The first dielectric material layer 102 is a ruthenium dioxide layer formed on the P-type well region of the ruthenium substrate 101. The gate layer 103 is composed of polysilicon.

Thereafter, the first dielectric material layer 102 is used as an etch stop layer, and the gate layer 103 is patterned to form the gate electrode 104 (as shown in FIG. 1B ). Then, a portion of the first dielectric material layer 102 not covered by the gate electrode 104 is removed by an isotropic etching process, such as a wet etching process, and a gate structure 114 is formed with the gate electrode 104 (as shown in the figure). 1C is shown).

In some embodiments of the present invention, the isotropic etching process uses an etchant comprising hydrofluoric acid (HF) to remove a portion of the first dielectric material layer 102 of the material ceria. In this embodiment, in addition to longitudinally removing a portion of the first dielectric material layer 102 not covered by the gate electrode 104, the etchant laterally faces a portion of the first dielectric material under the gate electrode 104. Layer 102 performs side etching, and then at the gate A plurality of undercut openings 105 are formed at the bottom of the structure 114.

Then, on the exposed surface of the germanium substrate 101 and the gate electrode 104, a second dielectric material layer 106 is formed (as shown in FIG. 1D). In some embodiments of the present invention, the second dielectric material layer 106 is a thin layer of cerium oxide formed by a thermal oxidation process or a deposition process. In some embodiments of the invention, the second dielectric material layer 106 may completely fill the undercut openings 105. However, in this embodiment, the second dielectric material layer 106 does not completely fill the undercut opening 105; and the undercut opening 105 is formed by the tantalum nitride layer 107 subsequently formed on the second dielectric material layer 106. Filled up (as shown in Figure 1E). It should be noted that in other embodiments of the present invention, other material layers having trapping electron retention characteristics may be used instead of the tantalum nitride layer 107.

Subsequently, the germanium substrate 101 and the gate electrode 104 are used as an etch stop layer, and an anisotropic etching process, such as reactive ion etching, removes a portion of the tantalum nitride layer 107 and the second dielectric material layer 106, and On the sidewalls 114a and 114b of the gate structure 114, another portion of the tantalum nitride layer 107 and the second dielectric material layer 106 are left. In the present embodiment, another portion of the tantalum nitride layer 107 and the second dielectric material layer 106 filled under the gate structure 114 are also left behind (as shown in FIG. 1F).

Then, a third dielectric material layer 108 is formed on the side of the remaining tantalum nitride layer 107 away from the gate structure 114 by a deposition and patterning process to electrically isolate the substrate 101 from the tantalum nitride layer 107 ( As shown in Figure 1G). In the present embodiment, the third dielectric material layer 108 is preferably a patterned cerium oxide layer formed by a thermal deposition process and a patterning process.

Subsequently, the third dielectric material layer 108, the remaining second dielectric material layer 106, the tantalum nitride layer 107, and the gate structure 114 are used as a mask to perform at least one ion doping process to form a light on the substrate 101. Light Drain Doping (LDD) zone 109. And on the side of the third dielectric material layer 108 away from the gate structure 114, the spacer 110 is formed: the gate structure 114 and the spacer 110 are used as a mask to perform at least another ion doping. In the heterogeneous process, the drain region 111 and the source region 112 are formed in the substrate 101 to complete the non-volatile memory device 100 as shown in FIG. 1H.

In the present embodiment (see FIG. 1H), the opposite sidewalls 114a and 114b of the gate structure 114 of the non-volatile memory device 100 respectively have a second dielectric material layer 106 and a tantalum nitride layer 107 which are etched away. And the multilayer structure composed of the third dielectric material layer 108 can form two SONOS structures with the gate structure 114 and the germanium substrate 101, and symmetrically formed on the sidewalls 114a and 114b of the gate structure 114.

The remaining tantalum nitride layer 107 itself has the property of capturing the indwelling electrons, and is in the form of a vertical wall, and can be used as a charge trapping layer of the SONOS structure (hereinafter referred to as the charge trapping vertical wall 113); the third dielectric material layer 108 is combined with a part. The remaining first dielectric material layer 102 electrically isolates the channel of the substrate 101 from the charge trapping vertical wall 113 and can serve as a tunneling oxide layer of the SONOS structure; the remaining second dielectric material layer 106 is combined with another portion. The remaining first dielectric material layer 102 electrically isolates both the gate electrode 104 and the charge trapping vertical wall 113, and can be used as a resistive oxide layer of the SONOS structure.

In an embodiment of the invention, the symmetric two charge trapping walls 113 and the substrate 101 have a non-flat angle 115. In the present embodiment, the non-flat angle 115 between the single charge trapping vertical wall 113 and the substrate 101 may be an angle of 90°. However, in other embodiments of the invention, the non-flat angle 115 may also be other angles, such as an angle substantially greater than 0° and less than 90°.

In the present embodiment, the charge trapping vertical wall 113, in addition to the longitudinal upright wall portion, includes a laterally extending portion under the gate structure 114 for filling the undercut opening 105. Therefore, the charge trapping vertical wall 113 has an L-shaped cross section (as shown in FIG. 1H). However, in another embodiment of the present invention, the second dielectric material layer 106' has been completely filled due to the undercut opening 105 before the tantalum nitride layer 107 has been formed. Therefore, in the non-volatile memory element 100', the charge trapping vertical wall 113' has an I-shaped cross section (as shown in Fig. 1H').

In some embodiments of the invention, the aforementioned plurality of non-volatile memory elements 100 may be arranged in a non-volatile memory element array having a plurality of rows and a plurality of columns.

In the present embodiment, when the channel hot electron injection (CHE) mode is used to perform the write operation on the non-volatile memory element 100, the gate electrode 104 and the drain region 111 must be positively biased. The pressure generates a large lateral electric field near the drain region 112, so that the electrons in the channel are accelerated to form hot electrons, and the tunneling oxide layer is injected to inject the charge trapping vertical wall 113 of the SONOS structure. The positive bias voltage applied to the gate electrode 104 and the drain region 111 is preferably 7V and 5.5V, respectively.

When the channel initiating Secondary Electron Injection (CHISEL) mode is used to perform the write operation on the non-volatile memory element 100, the gate electrode 104 and the source region 112 must be positively biased, and The substrate 101 is biased in reverse bias so that the hot electrons generated by the secondary impact are injected into the charge trapping wall 113 of the SONOS structure. The positive bias voltage applied to the gate electrode 104 and the source region 112 is preferably 5V and 3V, respectively; and the reverse bias voltage applied to the substrate 101 is preferably -2V.

Since the charge trapping vertical wall 113 itself has the property of capturing indwelling electrons. In order to avoid read disturb caused by the action of repeatedly writing and erasing the charge trapping vertical wall 113, the non-volatile memory element 100 is read by a reverse read method. operating. In the present embodiment, for the read operation of the non-volatile memory device 100, it is preferable to apply a positive bias of 2.8 V and 0.9 V to the gate electrode 104 and the source region 112, respectively.

2A to 2B, FIG. 2A to FIG. 2B are schematic cross-sectional views showing a process structure for fabricating non-volatile memory elements 200a and 200b according to another embodiment of the present invention. Since the steps of making the non-volatile memory elements 200a and 200b are substantially similar to the steps of making the non-volatile memory element 100, the difference exists only in the subsequent steps of the process. Therefore, the repeated process steps will not be repeated, and the same components will have the same character. No.

In the present embodiment, the steps of fabricating the non-volatile memory elements 200a and 200b can be initiated by the aforementioned FIG. 1F. After the anisotropic etching process is performed, the substrate 101 is etched as an etch stop layer, thereby dividing the gate structure 114 into two first partial gate structures 214a and second partial gate structures 214b separated from each other ( As shown in Figure 2A).

The first portion of the gate structure 214a includes a gate electrode 204a (a portion of the remaining gate electrode 104), a portion of the first dielectric material layer 102, and a multilayer structure (including a portion of the second portion) on the sidewall 114a of the original gate structure 114. The dielectric material layer 106 and the charge trapping vertical wall 213a); the second partial gate structure 214b includes a gate electrode 204b, another portion of the first dielectric material layer 102, and a multilayer structure on the sidewall 114b of the original gate structure 114. (Including another portion of the second dielectric material layer 106 and the charge trapping vertical wall 213b).

Subsequently, the first partial gate structure 214a and the second partial gate structure 214b are used as masks to perform an ion doping process to form light-drain-doped regions 209a and 209b in the substrate 101, respectively; The first portion of the gate structure 214a is exposed to the outer sidewall 214a1, the second portion of the gate structure 214b is exposed to the outer sidewall 214b1, and the charge trapping walls 213a and 213b are away from the side of the first gate electrode 204a and the second gate electrode 204b. Upper, the spacers 210a and 210b are formed.

The spacers of the non-volatile memory elements 200a and 200b are preferably composed of a two-layer structure. The spacer 210a includes an L-shaped ceria layer 210a1 and a dielectric material layer 210a2 covering the ceria layer 210a1. The spacer 210b also includes an L-shaped ceria layer 210b2 and a capping layer 210b1. The upper dielectric material layer 210b2. In some embodiments of the present invention, the materials constituting the dielectric layers 210a2 and 210b2 may be tantalum nitride, hafnium oxide, hafnium oxynitride or other dielectric materials.

The first partial gate structure 214a and the second partial gate structure 214b And the spacers 210 and 210b are masks, and the substrate 101 is subjected to at least one ion doping process to form a common source/substrate in the substrate adjacent to the first partial gate structure 214a and the second partial gate structure 214b, respectively. The drain region 211 and the source region 212a and the drain region 212b. Two adjacent non-volatile memory elements 200a and 200b are depicted as shown in Figure 2B.

In some embodiments of the present invention, two adjacent non-volatile memory elements 200a and 200b respectively have a gate electrode 204a (or 204b) and a second dielectric material including a ruthenium dioxide layer 210a1 (or 210b1). The multilayer structure of the layer 106 and a portion of the charge trapping vertical wall 113 can form two SONOS structures with the tantalum substrate 101, respectively.

In an embodiment of the invention, the non-volatile memory elements 200a and 200b are identical in structure but mirror each other; and both adjacent non-volatile memory elements 200a and 200b have a single charge trapping wall 213a And 213b are respectively located on opposite sides of the corresponding gate electrodes 204a and 204b. As shown in FIG. 2B, the single charge trapping vertical wall 213a of the non-volatile memory element 200a is adjacent to the left side wall 214a1 of the first partial gate structure 214a; the single charge trapping vertical wall 213b of the non-volatile memory element 200b is adjacent to the second portion. The right side wall 214b1 of the gate structure 214b.

In addition, the single charge trapping walls 213a and 213b of the non-volatile memory elements 200a and 200b are respectively provided with a non-flat angle 215a and 215b with the substrate 101. In some embodiments of the invention, the two non-flat angles 215a and 215b are preferably equal to 90°. However, in other embodiments of the invention, the non-flat angles 215a and 215b may also be other angles, such as angles substantially greater than 0° and less than 90°.

In some embodiments of the invention, the source or drain regions of two adjacent non-volatile memory elements 200a and 200b may partially overlap, and the first portion of the gate structure 214a and the second portion of the gate structure Between 214b, a common source/drain region 211 is formed.

In some embodiments of the present invention, the aforementioned plurality of non-volatile memory elements 200a and 200b may be arranged in a non-volatile memory element having a plurality of rows and a plurality of columns. Array of parts.

In the present embodiment, when the channel write operation is performed using the channel hot electron injection mode, the non-volatile memory element 200b is exemplified, and the gate electrode 204a and the drain region 212b are preferably applied with 7V and 5.5V, respectively. Positive bias. When the channel secondary electron injection mode is employed, when the non-volatile memory element 200b is subjected to a write operation, it is preferable to apply positive 5V and 3V to the gate electrode 204b and the source region (the common source/drain region 211), respectively. The bias was applied and a reverse bias of -2 V was applied to the substrate 101. When the reverse reading method is used, the component reading operation is performed. Then, only a positive bias of 2.8 V and 0.1 to 0.3 V is applied to the gate electrode 204a and the common source/drain region 211, respectively.

Comparing the operating voltages of the non-volatile memory elements 100 and 200b, it can be found that the read operation of the non-volatile memory elements 100 and 200b, whether in the channel hot electron injection mode or the channel secondary electron injection mode, the operation of the two The voltage is approximately the same. However, when the reverse reading mode is employed, the operating voltage of the non-volatile memory element 200 is much smaller than the operating voltage of the non-volatile memory element 100 when performing a component reading operation.

Since the non-volatile memory element 100 has two symmetric charge trapping walls 113 adjacent to the source region 112 and the drain region 111, respectively. In addition, the charge trapping vertical wall 113 itself has the property of capturing indwelling electrons. Therefore, when performing the component reverse reading process, it is necessary to increase the operating voltage of the component to generate a sufficient depletion region width to cover the channel under the charge trapping layer 113 to obtain a sufficient reading current. However, this will increase the leakage current of the source region 112 adjacent to the non-reading end. Therefore, indirectly affecting or interfering with the access of peripheral components also causes current consumption to become large. In addition, in order to increase the read current, the doping concentration of the source region 112 and the drain region 111 must also increase, but it is easy to cause a short channel effect and a hot carrier effect, resulting in component breakdown, resulting in the non-volatile memory device 100. The channel length needs to be lengthened.

Conversely, taking the non-volatile memory element 200b as an example, since the non-volatile memory element 200b has only a single charge trapping vertical wall 213b adjacent to the drain region 212b. There is no charge trapping layer on the read/write side (shared source/drain region 211), there will be no indwelling electrons. The phenomenon. When reading data, you only need to give a small bias to get enough read current. The leakage current of the source region (common source/drain region 211) adjacent to the non-reading terminal can be reduced. Therefore, the reverse reading process of the non-volatile memory element 200b is not affected, and the breakdown voltage of the non-volatile memory element 200b and the operating voltage and current consumption during reading are also reduced, and the peripheral components are not interfered. . The energy consumption of the non-volatile memory element 200b can be reduced, the source/drain doping can be reduced, the short channel effect and the hot carrier effect can be reduced, and the miniaturization of the critical size of the non-volatile memory element is facilitated.

According to the above embodiments, the present invention provides a programmable non-volatile memory element and a method of fabricating the same. The programmable non-volatile memory element has an asymmetrical structure that includes a single charge trapping wall adjacent one of the sidewalls of the gate electrode. Wherein, the gate electrode is located above the substrate and is electrically isolated from the substrate. A single charge captures the vertical wall, is electrically isolated from the substrate and the gate electrode, and has a non-flat angle with the substrate.

Since the non-volatile memory element has only a single charge trapping vertical wall, when the non-volatile memory element is programmed, there is no phenomenon of leaving electrons on the side without the charge trapping layer. When reading data, you only need to give a small bias to get enough read current. It not only does not affect the reading of components, but also reduces the leakage current and breakdown voltage of non-volatile memory components, and improves the problem of excessive operating voltage and current consumption during reading, and does not interfere with peripheral components. It can reduce the energy consumption of components. It also reduces source/drain doping, reduces short-channel effects and hot-carrier effects, and facilitates miniaturization of critical dimensions of components.

While the invention has been described above in the preferred embodiments, it is not intended to limit the invention. Anyone having ordinary knowledge in the field can make some changes and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

101‧‧‧Substrate

106‧‧‧Second dielectric material layer

200a‧‧‧Non-volatile memory components

200b‧‧‧ non-volatile memory components

204a‧‧ ‧ gate electrode

204a1‧‧‧ sidewall of the gate electrode

204b‧‧‧ gate electrode

204b1‧‧‧ sidewall of the gate electrode

209a‧‧‧Light 汲 polar zone

209b‧‧‧Light 汲 polar zone

210a‧‧‧ clearance

210a1‧‧ 二2 layer

210a2‧‧‧ dielectric material layer

210b‧‧‧ spacer

210b1‧‧ 二2 layer

210b2‧‧‧ dielectric material layer

211‧‧‧Shared source/bungee area

212a‧‧‧ source area

212b‧‧‧Bungee Area

213a‧‧‧Single charge capture vertical wall

213b‧‧‧Single charge capture vertical wall

214a‧‧‧The first part of the gate structure

214a1‧‧‧The first part of the gate structure exposed to the outer side wall

214b‧‧‧Second part gate structure

214b1‧‧‧The second part of the gate structure exposed to the outer side wall

215a‧‧‧Non-flat angle

215b‧‧‧Non-flat angle

Claims (15)

A non-volatile memory component comprising: a substrate; a first portion and a second portion of the gate electrode above the substrate and corresponding to each other and electrically isolated from the substrate, wherein the first portion and the second portion Each of the gate electrodes has at least two sidewalls; two single charge trapping walls are respectively located on opposite sides of the first portion and the second portion of the gate electrode, and are adjacent only to the at least two sidewalls of each of the first portion and the second portion of the gate electrode One of them is electrically isolated from the substrate and the first portion and the second portion of the gate electrode, and is respectively disposed at a non-flat angle with the substrate; and a plurality of source/drain regions are located on the substrate And respectively adjacent to the first portion and the second portion of the gate electrode, wherein the source/drain regions partially overlap to form a common source/drain region between the first portion and the second portion of the gate electrode. The non-volatile memory element of claim 1, wherein the two single charge trapping walls are respectively located between the substrate and the first portion and the second portion of the gate electrode. The non-volatile memory element of claim 2, wherein the two single charge trapping walls have a cross section of an L shape or an I shape. The non-volatile memory element of claim 1, wherein the non-flat angle is substantially greater than 0° and less than or equal to 90°. The non-volatile memory component of claim 1, further comprising: a first dielectric material layer for isolating the substrate and the first portion and the second portion of the gate An electrode; and a second dielectric material layer for isolating the first portion and the second portion of the gate electrode and the two single charge trapping walls. The non-volatile memory device of claim 5, wherein the two single charge trapping walls are made of tantalum nitride; the first dielectric material layer and the second dielectric material layer are both Oxide layer. The non-volatile memory element of claim 1, further comprising two spacers respectively located on a side of the two single charge trapping vertical walls away from the first portion and the second partial gate electrode. A non-volatile memory element array comprising a plurality of the non-volatile memory elements as described in claim 1 and arranged in a plurality of rows and a plurality of columns. A method for fabricating a non-volatile memory device includes: forming a first dielectric material layer and a gate electrode layer on a substrate; patterning the gate electrode layer and the first dielectric material layer to form a gate a second dielectric material layer and a charge trapping layer are formed on the at least one sidewall of the gate structure; a portion of the charge trapping layer and a portion of the gate structure are removed to form a single charge Capturing the standing wall and remaining a first portion and a second portion of the gate structure, wherein the two single charge trapping walls are respectively adjacent to the at least one sidewalls of the first portion and the second portion of the gate structure that are not adjacent to each other; Forming a plurality of source/drain regions in the substrate, respectively adjacent to the first portion and the second portion of the gate structure, and partially weighing between the first portion and the second portion of the gate structure Stacked to form a common source/drain region. The method of fabricating the non-volatile memory device of claim 9, wherein the step of patterning the gate electrode layer and the first dielectric material layer comprises: etching the gate electrode layer to form a gate electrode And using the gate electrode as a mask to perform an isotropic etching on the first dielectric material layer, thereby forming a side undercut at the bottom of the gate structure. The method for fabricating the non-volatile memory device of claim 9, wherein the step of forming the second dielectric material layer does not fill the undercut gap; the undercut is formed by the subsequent formation The charge trapping layer is filled. The method for fabricating a non-volatile memory device according to claim 9, wherein the step of removing a portion of the charge trap layer comprises: patterning the charge trap layer to form a gate structure adjacent to the first portion a first single charge trapping wall of a first sidewall and a second single charge trapping wall adjacent to a second sidewall of the second portion of the gate structure. The method of fabricating a non-volatile memory device according to claim 12, wherein the step of removing a portion of the gate structure comprises patterning the gate structure to thereby distinguish the first sidewall and the The first partial charge captures the first portion of the gate structure of the riser wall and the second portion of the gate structure including the second sidewall and the second single charge trapping riser. The method for fabricating the non-volatile memory element according to claim 13 of the patent application scope further includes: Forming a first spacer adjacent to the first portion of the gate structure and the first single charge trapping sidewall; and forming a second spacer adjacent to the second portion of the gate structure and the second single charge trapping wall. The method of fabricating the non-volatile memory device of claim 13, wherein the step of forming the plurality of source/drain regions comprises performing at least one ion implantation process to form the common source/汲Polar zone.