TWI445165B - Non-volatile memory, manufacturing method thereof and operating method of memory cell - Google Patents

Description

Non-volatile memory, manufacturing method thereof and operating method of memory cell

The present invention relates to a non-volatile memory, a method for fabricating the same, and a method for operating a memory cell, and more particularly to a non-volatile method capable of avoiding a second bit effect. Memory and its manufacturing method and method of operating memory cells.

Non-volatile memory has the advantage that it does not disappear after power-off, so many electrical products must have such memory to maintain the normal operation of the electrical products when they are turned on. In particular, flash memory has become a memory component widely used in personal computers and electronic devices because it has operations such as storing, reading, and erasing data.

Charge-trapped flash memory is a commonly used flash memory. In a charge trapping flash memory, a two-bit data can be stored using a charge trapping structure (i.e., a well-known ONO layer) composed of an oxide layer-nitride layer-oxide layer. In general, the two-bit data can be stored separately on the left side (ie, the left bit) or the right side (ie, the right bit) of the nitride layer in the charge trapping structure.

However, there is a second bit effect in the charge trapping flash memory, that is, when the left bit is read, it is affected by the right bit, or when the right bit is read, Will be affected by the left bit. In addition, as the size of the memory shrinks, the second bit effect is more significant, thus affecting the operation window and component performance of the memory.

Embodiments of the present invention provide a non-volatile memory that avoids the generation of a second bit effect during operation.

Embodiments of the present invention further provide a method of fabricating a non-volatile memory that can produce a non-volatile memory having a large operational margin.

Embodiments of the present invention further provide a method of operating a memory cell that can effectively improve component performance.

Embodiments of the present invention provide a non-volatile memory including a substrate, a plurality of strip-shaped first doped regions, a plurality of strip-shaped second doped regions, a charge trapping structure, and a plurality of strip-shaped first a gate, a plurality of strip-shaped second gates, and an inter-gate insulating layer. The first doped region is disposed in the substrate and extends in the first direction. The second doped region is disposed in the substrate and extends in the first direction, and the second doped region is alternately arranged with the first doped region. The charge trapping structure is disposed on the substrate. The first gate is disposed on the charge trapping structure and extends in the first direction, and each of the first gates is located on one of the first doped regions. The second gate is disposed on the charge trapping structure and extends in the second direction and is located on the second doped region, wherein the second direction is staggered with the first direction. The gate insulating layer is disposed between the first gate and the second gate. The first first doped region and the second doped region and the first gate, the second gate and the charge trapping structure between the adjacent first doped region and the second doped region define a memory cell .

According to the non-volatile memory of the embodiment of the invention, the width of the first gate is greater than the width of the first doped region, for example.

In a non-volatile memory according to an embodiment of the invention, the substrate has, for example, a plurality of trenches, each of the first doped regions being located below one of the trenches, each of the first gates being located in the trenches The bottom of one of them, and in the second direction, these second gates fill the trenches.

According to the non-volatile memory of the embodiment of the invention, the charge trapping structure is, for example, a composite structure composed of a bottom oxide layer, a charge trap layer and a top oxide layer.

According to the non-volatile memory of the embodiment of the invention, the material of the charge trapping layer is, for example, a nitride or a high dielectric constant material.

According to the non-volatile memory of the embodiment of the invention, the high dielectric constant material is, for example, HfO ₂ , TiO ₂ , ZrO ₂ , Ta ₂ O ₅ or A _{1 2} O ₃ .

Embodiments of the present invention further provide a method of fabricating a non-volatile memory by first providing a substrate. Then, a charge trapping structure is formed on the substrate. Next, a plurality of strip-shaped first insulating layers are formed on the charge trapping structure, and the first insulating layers extend in the first direction. Then, conductor spacers are formed on the sidewalls of each of the first insulating layers, and the conductor spacers extend in the first direction. Then, the first insulating layer and the conductor spacers are used as masks to perform an ion implantation process to form a plurality of strip-shaped doped regions in the substrate, and the doped regions extend in the first direction. Subsequently, a first conductor layer is formed on the charge trapping structure, the first conductor layer covering the conductor spacers and exposing the first insulating layer. Next, a second insulating layer is formed on the first conductor layer and the first insulating layer, the second insulating layer exposing a portion of the first conductor layer in the first direction. Then, a second conductor layer is formed on the second insulating layer and the first conductor layer. Thereafter, the second conductor layer and the first conductor layer exposed by the second insulating layer are patterned to form a plurality of strip-shaped third conductor layers in the second direction, wherein the second direction is staggered with the first direction.

According to the manufacturing method of the non-volatile memory of the embodiment of the present invention, each of the first insulating layer and the conductor spacer has a total width, and the width of each of the first insulating layers is, for example, greater than four points of the total width. One and less than one-half of this total width.

According to a method of manufacturing a non-volatile memory according to an embodiment of the invention, the first conductor layer is formed by, for example, forming a conductor material layer on the charge trapping structure and covering the first insulating layer and the conductor spacer. Thereafter, a planarization process is performed to remove a portion of the layer of conductor material until the first insulating layer is exposed.

According to a method of manufacturing a non-volatile memory according to an embodiment of the invention, the method for forming the second insulating layer is, for example, forming an insulating material layer on the first conductor layer and the first insulating layer. Thereafter, a patterning process is performed to remove a portion of the insulating material layer in the first direction.

Embodiments of the present invention further provide a method of fabricating a non-volatile memory by first providing a substrate. Then, a plurality of trenches are formed in the substrate, and the trenches extend in the first direction. Next, a charge trapping structure is formed on the substrate. A plurality of doped regions are then formed in the trenches and in the substrate at the bottom of the trenches, and the doped regions extend in the first direction. Then, a first conductor layer is formed at the bottom of the trenches, and the first conductor layer extends in the first direction. Subsequently, an insulating layer is formed on the first conductor layer. Thereafter, in the second direction, a plurality of strip-shaped second conductor layers are formed on the charge trapping structure, and the second conductor layers fill the trenches, wherein the second direction is staggered with the first direction.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the first conductor layer is formed by, for example, forming a layer of a conductor material on the charge trapping structure and filling the trenches. Thereafter, an etching process is performed to remove a portion of the conductor material layer and retain a portion of the conductor material layer at the bottom of the trench.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the method for forming the insulating layer is, for example, forming a layer of insulating material on the charge trapping structure and filling the trenches. Thereafter, an etching process is performed to remove a portion of the insulating material layer and retain a portion of the conductive material layer on the first conductor layer.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the second conductor layer is formed by, for example, forming a layer of a conductor material on the charge trapping structure and filling the trenches. Thereafter, a patterning process is performed to remove a portion of the layer of conductor material in the second direction.

Embodiments of the present invention further provide a method of operating a memory cell, the method of providing a memory cell as described above, applying a first voltage to a first gate when performing a program operation, and applying a second voltage to a second gate a voltage; applying a third voltage to the first doped region; applying a fourth voltage to the second doped region; applying a fifth voltage to the substrate.

According to the method for operating a memory cell according to an embodiment of the present invention, when the program operation is performed by, for example, channel hot electrons (CHE) injection, the first voltage is substantially the same as the second voltage, wherein the first voltage is Between 9 volts and 13 volts; the second voltage is between 9 volts and 13 volts; one of the third voltage and the fourth voltage is 0 volts, and the third voltage and the fourth voltage are the other Between 3.5 volts and 5.5 volts; the fifth voltage is 0 volts.

According to the method of operating a memory cell according to an embodiment of the invention, when the staging operation is performed, for example, by enhanced channel hot electron injection, one of the first voltage and the second voltage is between 9 volts and 13 volts, and One of the voltage and the second voltage is between 1.5 volts and 3 volts; one of the third voltage and the fourth voltage is 0 volts, and the third voltage and the fourth voltage are the other ones between 3.5 volts and 5.5 volts The fifth voltage is 0 volts.

According to the operation method of the memory cell according to the embodiment of the present invention, after the stylization operation, the erase operation may be performed, and when the erase operation is performed, the sixth voltage is applied to the first gate; A seventh voltage is applied to the pole; an eighth voltage is applied to the first doped region; a ninth voltage is applied to the second doped region; and a tenth voltage is applied to the substrate.

According to the method of operating a memory cell according to an embodiment of the invention, when the erasing operation is performed, for example, by a band-to-band hot hole (BBHH), the sixth voltage and the seventh voltage are One is 0 volts, floating or between -11 volts and -15 volts, and the sixth voltage and the seventh voltage are between -11 volts and -15 volts; the eighth voltage and the first One of the nine voltages is 0 volts or floating, and the eighth voltage and the ninth voltage are between 4 volts and 5 volts; the tenth voltage is 0 volts.

According to the operation method of the memory cell according to the embodiment of the present invention, after the stylization operation, a read operation may be performed, and when the read operation is performed, the eleventh voltage is applied to the first gate; The gate applies a twelfth voltage; a thirteenth voltage is applied to the first doped region; a fourteenth voltage is applied to the second doped region; and a fifteenth voltage is applied to the substrate.

According to the method for operating a memory cell according to an embodiment of the invention, one of the eleventh voltage and the twelfth voltage is between 5 volts and 9.5 volts, and the eleventh voltage and the twelfth voltage are Between 0 volts and 6 volts; one of the thirteenth voltage and the fourteenth voltage is between 0.7 volts and 1.6 volts, and the thirteenth voltage and the fourteenth voltage voltage of the other is 0 volts; The voltage is 0 volts.

Embodiments of the present invention further provide a method of fabricating a non-volatile memory that provides a substrate first. Then, a plurality of strip-shaped first doped regions and a plurality of strip-shaped second doped regions are formed in the substrate. The first doped region and the second doped region extend in the first direction, and the first doped region and the second doped region are alternately arranged. Next, a charge trapping structure is formed on the substrate. Then, a plurality of strip-shaped first gates are formed on the charge trapping structure. The first gate extends in the first direction, and each of the first gates is located on one of the first doped regions. Then, a plurality of strip-shaped second gates are formed on the charge trapping structure. The second gate extends in the second direction and is located on the second doped region, wherein the second direction is staggered with the first direction. Thereafter, an inter-gate insulating layer is formed between the first gate and the second gate.

According to the method for manufacturing a non-volatile memory according to the embodiment of the present invention, the method for forming the first gate, the second gate, and the inter-gate insulating layer is formed by, for example, forming a plurality of strips on the charge trapping structure. a first insulating layer, and the first insulating layers extend in the first direction. Then, conductor spacers are formed on the sidewalls of each of the first insulating layers, and the conductor spacers extend in the first direction. Next, a first conductor layer is formed on the charge trapping structure, the first conductor layer covering the conductor spacers and exposing the first insulating layer. And forming a second insulating layer on the first conductive layer and the first insulating layer, the second insulating layer exposing a portion of the first conductive layer in the first direction, and then, in the second insulating layer and the first conductive layer A second conductor layer is formed thereon. Thereafter, the second conductor layer and the first conductor layer exposed by the second insulating layer are patterned to form a plurality of strip-shaped third conductor layers in the second direction, wherein the third conductor layer and the underlying layer The first conductor layer constitutes a second gate.

According to the method for fabricating a non-volatile memory according to the embodiment of the present invention, the method for forming the first doped region and the second doped region is performed by, for example, using a first insulating layer and a conductor spacer as a mask to perform ion Implantation process.

Based on the above, the non-volatile memory of the embodiment of the present invention has a plurality of first gates and a plurality of second gates arranged in a staggered manner, so that each memory cell has two gates, so when performing a program operation, Channel hot electron injection or enhanced channel hot electron injection can be performed by applying appropriate voltages to the two gates to increase stylized efficiency and thereby improve component performance. Further, when a read operation is performed, the second bit effect can be suppressed by applying a high voltage to the gate located on the non-read side to increase the operation margin. In addition, when the read operation is performed, since the second bit effect is suppressed by applying a high voltage to the gate on the non-read side, it is not necessary to apply a high voltage to the doped region under the gate on the non-read side. To suppress the second bit effect, the problem of read disturb can be alleviated.

The above general description and the following detailed description are exemplary and are not intended to limit the invention.

The above described features and advantages of the present invention will be more apparent from the following description.

First embodiment

FIG. 1A is a top view of a non-volatile memory according to an embodiment of the invention. 1B is a schematic cross-sectional view of the memory cell taken along line II' of FIG. 1A. Referring to FIG. 1A and FIG. 1B simultaneously, the non-volatile memory 10 includes a substrate 100, a plurality of strip-shaped first doped regions 102, a plurality of strip-shaped second doped regions 104, a charge trapping structure 106, and a plurality of A strip-shaped first gate 108, a plurality of strip-shaped second gates 110, and an inter-gate insulating layer 112. The substrate 100 is, for example, a germanium substrate or a silicon on insulator (SOI) substrate. The first doping region 102 and the second doping region 104 are disposed in the substrate 100 and extend along the first direction Y. The first doping region 102 and the second doping region 104 are alternately arranged. The first doping region 102 and the second doping region 104 serve as a source and a drain, respectively. Alternatively, the first doping region 102 and the second doping region 104 may also serve as a drain and a source, respectively. The charge trapping structure 106 is disposed on the substrate 100. The charge trapping structure 106 is, for example, a composite structure composed of a bottom oxide layer, a charge trapping layer, and a top oxide layer, wherein the bottom oxide layer functions as a tunneling dielectric layer and the top oxide layer functions as a charge blocking layer. The material of the charge trap layer is, for example, a nitride or a high dielectric constant material (for example, HfO ₂ , TiO ₂ , ZrO ₂ , Ta ₂ O ₅ or Al ₂ O ₃ ). The thickness of the bottom oxide layer is, for example, 40 To 50 between. The thickness of the charge trap layer is, for example, 60 To 100 between. The thickness of the top oxide layer is, for example, 70 To 110 between.

The first gate 108 is disposed on the charge trapping structure 106 and extends along the first direction Y, and each of the first gates 108 is located on a first doping region 102. The width of the first gate 108 is, for example, greater than the width of the first doped region 102. The second gate 110 is disposed on the charge trapping structure 106 and extends along the second direction X and is located on the second doping region 104. The first direction Y is interlaced with the second direction X. In the present embodiment, the first direction Y is perpendicular to the second direction X. The material of the first gate 108 and the second gate 110 is, for example, polysilicon. The inter-gate insulating layer 112 is disposed between the first gate 108 and the second gate 110. The inter-gate insulating layer 112 is composed of, for example, an inter-gate insulating layer 112a on the top surface of the first gate 108 and an inter-gate insulating layer 112b on the sidewall of the first gate 108.

In this embodiment, the adjacent first doping region 102 and the second doping region 104 and the first gate 108 between the adjacent first doping region 102 and the second doping region 104, The two gates 110 and the charge trapping structure 106 define a memory cell 10a, that is, a region surrounded by block B in FIG. 1A. In the memory cell 10a, a portion of the first gate 108 is above the first doped region 102 and a portion of the second gate 110 is above the second doped region 104. In addition, the second gate 110 covers the top of the first gate 108 in addition to the charge trapping structure 106. The first gate 108 and the second gate 110 are separated from each other by the inter-gate insulating layer 112a and the inter-gate insulating layer 112b.

Hereinafter, a method of manufacturing the non-volatile memory 10 will be described by the cross section I-I' in Fig. 1A.

2A to 2D are cross-sectional views showing the manufacturing process of the non-volatile memory taken along the line I-I' in Fig. 1A. In FIGS. 2A to 2D, the same elements as those in FIGS. 1A and 1B will be denoted by the same reference numerals and will not be described herein. First, referring to FIG. 2A, a substrate 100 is provided. Then, a charge trapping structure 106 is formed on the substrate 100. Next, a strip-shaped first insulating layer 200 is formed on the charge trapping structure 106. The first insulating layer 200 extends along the first direction Y in FIG. 1A. The first insulating layer 200 is the inter-gate insulating layer 112a in FIG. 1B. The first insulating layer 200 is formed by, for example, forming a layer of insulating material on the charge trapping structure 106 and then performing a patterning process.

Then, referring to FIG. 2B, a conductor spacer 202 is formed on the sidewall of the first insulating layer 200. The conductor spacer 202 extends in a first direction Y in FIG. 1A. The material of the conductor spacer 202 is, for example, polysilicon. In the present embodiment, the first insulating layer 200 has a total width W1 with the conductor spacers 202 on the sidewalls thereof, and the width W2 of the first insulating layer 200 is greater than a quarter of the total width W1 and less than the total width W1. one. Thereafter, an ion implantation process is performed with the first insulating layer 200 and the conductor spacers 202 as masks to form strip-shaped first doping regions 102 and strip-shaped second doping regions 104 in the substrate 100. The first doped region 102 and the second doped region 104 extend along a first direction Y in FIG. 1A.

Next, referring to FIG. 2C, a first conductor layer 204 is formed on the charge trapping structure 106. The first conductor layer 204 covers the conductor spacers 202 and exposes the first insulating layer 200. The material of the first conductor layer 204 is, for example, polysilicon. The first conductor layer 204 is formed by, for example, forming a conductor material layer on the charge trapping structure 106 and covering the first insulating layer 200 and the conductor spacers 202. Thereafter, a planarization process is performed to remove a portion of the conductor material layer until the first insulating layer 200 is exposed.

Thereafter, referring to FIG. 2D, a second insulating layer 206 is formed on the first conductor layer 204 and the first insulating layer 200. The second insulating layer 206 exposes a portion of the first conductor layer 204 in the first direction Y in FIG. 1A. The second insulating layer 206 is the inter-gate insulating layer 112b in FIG. 1B. The second insulating layer 206 is formed by, for example, forming an insulating material layer on the first conductive layer 204 and the first insulating layer 200. Thereafter, a patterning process is performed to remove a portion of the insulating material layer in the first direction Y. Then, a second conductor layer 208 is formed on the second insulating layer 206 and the first conductor layer 204. The material of the second conductor layer 208 is, for example, polycrystalline germanium. Thereafter, the second conductor layer 208 and the first conductor layer 204 exposed by the second insulating layer 206 are patterned to form a strip-shaped third conductor layer (by the pattern in the second direction X in FIG. 1A) The second conductor layer 208 and the first conductor layer 204 below it are formed, and the charge trapping structure 106 is exposed between the adjacent two third conductor layers.

In the present embodiment, the conductor spacer 202 and the first conductor layer 204 covered by the first insulating layer 200 and the second insulating layer 206 (ie, the conductor spacer 202 on the right side of the first insulating layer 200 in FIG. 2D and the first The conductor layer 204) constitutes the first gate 108 in FIGS. 1A and 1B. In addition, the patterned second conductor layer 208 and the first conductor layer 204 below it (ie, the first conductor layer 204 and the second conductor layer 208 on the left side of the first insulating layer 200 in FIG. 2D) constitute FIG. 1A and FIG. The second gate 110 in 1B.

Second embodiment

FIG. 3A is a top view of a non-volatile memory according to another embodiment of the invention. Fig. 3B is a schematic cross-sectional view of the memory cell taken along the line II-II' in Fig. 3A. Referring to FIG. 3A and FIG. 3B simultaneously, the non-volatile memory 30 includes a substrate 300, a plurality of strip-shaped first doped regions 302, a plurality of strip-shaped second doped regions 304, a charge trapping structure 306, and a plurality of A strip-shaped first gate 308, a plurality of strip-shaped second gates 310, and an inter-gate insulating layer 312. The substrate 300 is, for example, a germanium substrate or a germanium substrate with an insulating substrate. The substrate 300 has a plurality of trenches 301 extending in a first direction Y. The first doping region 302 and the second doping region 304 are disposed in the substrate 300 and extend along the first direction Y. Each of the first doping regions 302 is located below a trench 301. The second doped region 304 is alternately arranged with the trench 301. The first doping region 302 and the second doping region 304 serve as a source and a drain, respectively. Alternatively, the first doping region 302 and the second doping region 304 may also serve as a drain and a source, respectively. The charge trapping structure 306 is conformally disposed on the substrate 300. The charge trapping structure 306 is the same as the charge trapping structure 106 of the first embodiment and will not be described herein.

Each of the first gates 308 is located at the bottom of one of the trenches 301 and is disposed on the charge trapping structure 306 and extends in the first direction Y. The second gate 310 is disposed on the charge trapping structure 306 and extends along the second direction X and is located on the second doping region 304. The first direction Y is interlaced with the second direction X. In the present embodiment, the first direction Y is perpendicular to the second direction X. Further, in the second direction X, the second gate 310 is filled in the trench 301. The material of the first gate 308 and the second gate 310 is, for example, polysilicon. The inter-gate insulating layer 312 is disposed in the trench 301 and between the first gate 308 and the second gate 310 for isolating the first gate 308 and the second gate 310.

In this embodiment, the adjacent first doping region 302 and the second doping region 304 and the first gate 308 between the adjacent first doping region 302 and the second doping region 304, The two gates 310 and the charge trapping structure 306 define a memory cell 30a, that is, a region surrounded by a broken line in FIG. 3B.

Hereinafter, a method of manufacturing the non-volatile memory 30 will be described by a cross section II-II' in Fig. 3A.

4A to 4C are cross-sectional views showing the manufacturing process of the non-volatile memory taken along the line II-II' in Fig. 3A. In FIGS. 4A to 4D, the same elements as those in FIGS. 3A and 3B will be denoted by the same reference numerals and will not be described herein. First, referring to FIG. 4A, a substrate 300 is provided. Then, a plurality of trenches 301 extending in the first direction Y are formed in the substrate 300. Next, a charge trapping structure 306 is conformally formed on the substrate 300.

Then, referring to FIG. 4B, an ion implantation process is performed to form a first doping region 302 extending in the first direction Y in the substrate 300 at the bottom of the trench 301, and a formation along the substrate 300 between the trenches 301. A second doped region 304 extending in a direction Y. Next, a first conductor layer 400 extending in the first direction Y is formed at the bottom of the trench 301. The first conductor layer 400 is formed by, for example, forming a layer of a conductor material on the charge trapping structure 306 and filling the trench 301. Then, an etching process is performed to remove the conductive material layer outside the trench 301 and a portion of the conductive material layer in the trench 301, leaving the conductive material layer at the bottom of the trench 301. The first conductor layer 400 is the first gate 308 in FIGS. 3A and 3B. Then, an insulating layer 402 is formed on the first conductor layer 400. The insulating layer 402 is formed by, for example, forming a layer of insulating material on the charge trapping structure 306 and filling the trench 301. Then, an etching process is performed to remove the insulating material layer outside the trench 301 and a portion of the insulating material layer in the trench 301, leaving the insulating material layer on the first conductive layer 400. The insulating layer 402 is the inter-gate insulating layer 312 in FIGS. 3A and 3B.

Thereafter, referring to FIG. 4C, in the second direction X, a plurality of strip-shaped second conductor layers 404 are formed on the charge trapping structure 306, and the second conductor layer 404 is filled in the trenches 301. The second conductor layer 404 is formed by, for example, forming a layer of a conductor material on the charge trapping structure 306 and filling the trench 301. Then, a patterning process is performed in which a portion of the conductor material layer outside the trench 301 and in the trench 301 is removed to form a strip-shaped second conductor layer 404. The second conductor layer 404 is the second gate 310 in FIGS. 3A and 3B.

The operation method of the memory cell of the embodiment of the present invention will be described below by taking the memory cell 10a of FIG. 1B as an example.

FIG. 5A is a schematic diagram of a stylized operation of a memory cell according to an embodiment of the invention. Referring to FIG. 5A, when the memory cell 10a is programmed, a voltage V _{1 is} applied to the first gate 108; a voltage V _{2 is} applied to the second gate 110; and a voltage V _{3 is} applied to the first doping region 102; A voltage V _{4 is} applied to the second doped region 104; a voltage V _{5 is} applied to the substrate 100.

In detail, when channel hot electron injection is used to perform a programmatic operation on the right bit R of the memory cell 10a (ie, electrons are stored in the charge trapping structure 106 below the first gate 108), the voltages V ₁ , V ₂ Is substantially the same relatively high voltage, and for example between 9 volts and 13 volts, such that the channel between the first doped region 102 and the second doped region 104 is relatively strongly turned on (strongly turn-on The voltage V _{3 is,} for example, between 3.5 volts and 5.5 volts; the voltage V _{4 is,} for example, 0 volts; and the voltage V _{5 is,} for example, 0 volts. Thus, electrons can be accelerated by a lateral electric field to be injected into the charge trapping structure 106 below the first gate 108. Similarly, when using channel hot electron injection to be left bit L to perform operations on the programmable memory cell 10a (the second gate is about 110 electrons into the charge trapping structure 106 below), the voltage V _1, V ₂ is substantially the same relatively high voltage, for example between 9 and 13 volts to V, so that the passage between the second doped region 102 and the first doped region 104 is relatively strongly on; for example, the voltage V ₃ 0 volts; voltage V _{4 is,} for example, between 3.5 volts and 5.5 volts; voltage V _{5 is,} for example, 0 volts. Thus, electrons can be accelerated by the lateral electric field to be injected into the charge trapping structure 106 below the second gate 110.

Further, to be enhanced using channel hot electron injection for the memory cell 10a stylized operation is performed, voltage V ₁ is for example between 9 volts to 13 volts right bit R, so that the electrode 108 below the first gate passage To be relatively strong; the voltage V _{2 is,} for example, between 1.5 volts and 3 volts such that the channel below the second gate 110 is weakly turn-on; the voltage V _{3 is,} for example, 3.5 volts Between 5.5 volts; voltage V _{4 is,} for example, 0 volts; voltage V _{5 is,} for example, 0 volts. A higher vertical electric field can be obtained by applying a relatively high voltage to the first gate 108, and a relatively high voltage can be obtained by applying a relatively low voltage to the second gate 110, so that Make stylized operations more efficient. Similarly, to be enhanced using channel hot electron injection on the left bit memory cell L stylized operation is performed, for example, voltage V ₁ is interposed between 10a 1.5 volts to 3 volts, so that under the first gate 108 The channel is relatively weakly open; the voltage V _{2 is,} for example, between 9 volts and 13 volts such that the channel below the second gate 110 is relatively strongly turned on; the voltage V _{3 is,} for example, 0 volts; the voltage V _{4 is,} for example, between 3.5 volts to 5.5 volts; the voltage V ₅ is, for example 0 volts. A relatively high electric field can be obtained by applying a relatively low voltage to the first gate 108, and a relatively high voltage can be applied by applying a relatively high voltage to the second gate 110, thereby enabling a more stylized operation. Efficient.

After the above-described stylization operation, the data stored in the memory cell 10a can be further erased.

FIG. 5B is a schematic diagram of an erase operation of a memory cell according to an embodiment of the invention. Referring to FIG. 5B, when the programmed memory cell 10a is erased, a voltage V _{6 is} applied to the first gate 108; a voltage V _{7 is} applied to the second gate 110; and the first doping region 102 is applied. Voltage V ₈ ; voltage V _{9 is} applied to second doped region 104; voltage V _{10 is} applied to substrate 100.

In detail, when an energy band can be used to erase the right bit R of the programmed memory cell 10a, the voltage V _{6 is,} for example, between -11 volts and -15 volts; V _{7 is,} for example, 0 volts, floating or between -11 volts and -15 volts; voltage V _{8 is,} for example, between 4 volts and 5 volts; voltage V _{9 is,} for example, 0 volts or floating; voltage V ₁₀ For example, it is 0 volts. Therefore, a hole is injected into the charge trapping structure 106 under the first gate 108 to be combined with electrons to erase the data stored in the right bit R of the memory cell 10a. Similarly, to use a band-to-band thermal hole to erase the left bit L of the programmed memory cell 10a, the voltage V _{6 is,} for example, 0 volts, floating or between -11 volts to - Between 15 volts; voltage V _{7 is,} for example, between -11 volts and -15 volts; voltage V _{8 is,} for example, 0 volts or floating; voltage V _{9 is,} for example, between 4 volts and 5 volts; voltage V _{10 is} for example It is 0 volts. Therefore, a hole is injected into the charge trapping structure 106 under the second gate 110 to be combined with electrons to erase the data stored in the left bit L of the memory cell 10a.

After the above-described stylization operation, the data stored in the memory cell 10a can be further read.

FIG. 5C is a schematic diagram of a read operation of a memory cell according to an embodiment of the invention. Referring to Figure 5C, when the memory cell for read operation has been stylized 10a, a voltage V ₁₁ is applied to the first gate 108; the applied voltage V ₁₂ to the second gate 110; 102 applied to the first doped region Voltage V ₁₃ ; voltage V _{14 is} applied to second doped region 104; voltage V _{15 is} applied to substrate 100.

When a read operation is performed on the right bit R of the memory cell 10a, the voltage V _{11 is,} for example, between 0 volts and 6 volts; the voltage V _{12 is,} for example, between 5 volts and 9.5 volts; and the voltage V _{13 is,} for example, 0. Volt; voltage V _{14 is,} for example, between 0.7 volts and 1.6 volts; voltage V _{15 is,} for example, 0 volts. Since the second gate 110 at the left bit L is applied with a relatively high voltage when reading the data stored in the right bit R, the second bit effect is suppressed, thereby increasing the operation margin. Further, when the read operation is performed on the right bit R of the memory cell 10a, since the second bit effect is suppressed by applying a high voltage to the second gate 110 on the non-read side, it is not required to be as in the prior art. Applying a high voltage to the second doping region 104 suppresses the second bit effect, thereby alleviating the problem of read disturb. Similarly, when a read operation is performed on the left bit L of the memory cell 10a, the voltage V _{11 is,} for example, between 5 volts and 9.5 volts; the voltage V _{12 is,} for example, between 0 volts and 6 volts; the voltage V ₁₃ For example, between 0.7 volts and 1.6 volts; voltage V _{14 is,} for example, 0 volts; voltage V _{15 is,} for example, 0 volts. Since the first gate 108 at the right bit R is applied with a relatively high voltage when reading the data stored in the left bit L, the second bit effect is suppressed, thereby increasing the operation margin. Further, when the read operation is performed on the left bit L of the memory cell 10a, since the high voltage is applied to the first gate 108 on the non-read side to suppress the second bit effect, it is not necessary to be as in the prior art. Applying a high voltage to the first doping region 102 suppresses the second bit effect, thereby alleviating the problem of read disturb.

In particular, the above-described method of operating the memory cell 10a can also be applied to the memory cell 30a. Those skilled in the art can achieve stylized, erased, and read operations on the memory cell 30a in accordance with the above-described stylization, erasing, and reading operations on the memory cell 10a. Therefore, the present specification will not be described herein.

In summary, the non-volatile memory of the embodiment of the present invention has a plurality of first gates and a plurality of second gates arranged in a staggered manner, so that each memory cell has two gates, and thus is programmed. Channel hot electron injection or enhanced channel hot electron injection can be performed by applying an appropriate voltage to the first gate and the second gate of the memory cell to increase the stylization efficiency and thereby improve the component performance.

Further, when a read operation is performed on the memory cell, the second bit effect can be suppressed by applying a high voltage to the gate on the non-read side to increase the operation margin.

In addition, when a read operation is performed on the memory cell, since the second bit effect is suppressed by applying a high voltage to the gate on the non-read side, it is not necessary to have the gate on the non-read side as in the prior art. The lower doped region applies a high voltage to suppress the second bit effect, so that read disturb can be effectively alleviated.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 30. . . Non-volatile memory

10a, 30a. . . Memory cell

100, 300. . . Base

102, 302. . . First doped region

104, 304. . . Second doped region

106, 306. . . Charge trapping structure

108, 308. . . First gate

110, 310. . . Second gate

112, 112a, 112b, 312. . . Inter-gate insulation

200. . . First insulating layer

202. . . Conductor spacer

204, 400. . . First conductor layer

206. . . Second insulating layer

208, 404. . . Second conductor layer

301. . . ditch

402. . . Insulation

B. . . Square

L. . . Left bit

R. . . Right bit

V ₁ ~ V ₁₅ . . . Voltage

W1. . . Total width

W2. . . width

X. . . Second direction

Y. . . First direction

FIG. 1A is a top view of a non-volatile memory according to an embodiment of the invention.

Fig. 1B is a schematic cross-sectional view of the memory cell taken along the line I-I' in Fig. 1A.

2A to 2D are cross-sectional views showing the manufacturing process of the non-volatile memory taken along the line I-I' in Fig. 1A.

FIG. 3A is a top view of a non-volatile memory according to another embodiment of the invention.

Fig. 3B is a schematic cross-sectional view of the memory cell taken along the line II-II' in Fig. 3A.

4A to 4C are cross-sectional views showing the manufacturing process of the non-volatile memory taken along the line II-II' in Fig. 3A.

FIG. 5A is a schematic diagram of a stylized operation of a memory cell according to an embodiment of the invention.

FIG. 5B is a schematic diagram of an erase operation of a memory cell according to an embodiment of the invention.

FIG. 5C is a schematic diagram of a read operation of a memory cell according to an embodiment of the invention.

10a. . . Memory cell

100. . . Base

102. . . First doped region

104. . . Second doped region

106. . . Charge trapping structure

108. . . First gate

110. . . Second gate

112, 112a, 112b. . . Inter-gate insulation

Claims (27)

A non-volatile memory comprising: a substrate; a plurality of strip-shaped first doped regions disposed in the substrate and extending along a first direction; a plurality of strip-shaped second doped regions disposed on the And extending in the first direction, and the second doped regions are alternately arranged with the first doped regions; a charge trapping structure disposed on the substrate; a plurality of strip-shaped first gates, Disposed on the charge trapping structure and extending along the first direction, and each first gate is located on one of the first doped regions; a plurality of strip-shaped second gates are disposed on the charge The capture structure extends along a second direction and is located on the second doped regions, wherein the second direction is staggered with the first direction; and a gate insulating layer is disposed on the first gates Between the second gates; wherein the first first doped region and the second doped region and the first one between the adjacent first doped region and the second doped region The gate, the second gate and the charge trapping structure define a memory cell. The non-volatile memory of claim 1, wherein the width of the first gates is greater than the width of the first doped regions. The non-volatile memory of claim 1, wherein the substrate has a plurality of trenches, each of the first doped regions is located under one of the trenches, and each of the first gates is located The bottom of one of the trenches, and in the second direction, the second gates fill the trenches. The non-volatile memory of claim 1, wherein the charge trapping structure comprises a composite structure composed of a bottom oxide layer, a charge trapping layer and a top oxide layer. The non-volatile memory of claim 4, wherein the material of the charge trapping layer comprises a nitride or a high dielectric constant material. The non-volatile memory of claim 5, wherein the high dielectric constant material comprises HfO ₂ , TiO ₂ , ZrO ₂ , Ta ₂ O ₅ or Al ₂ O ₃ . A method for fabricating a non-volatile memory, comprising: providing a substrate; forming a charge trapping structure on the substrate; forming a plurality of strip-shaped first insulating layers on the charge trapping structure, and the first insulating layers Extending along a first direction; forming a conductor spacer on a sidewall of each first insulating layer, and the conductor spacers extend along the first direction; and the first insulating layer and the conductor spacers are a masking process, wherein an ion implantation process is performed to form a plurality of strip-shaped doping regions in the substrate, and the doping regions extend along the first direction; forming a first conductor layer on the charge trapping structure, The first conductive layer covers the conductive spacers and exposes the first insulating layers; a second insulating layer is formed on the first conductive layer and the first insulating layers, and the second insulating layer is a portion of the first conductor layer is exposed in a first direction; a second conductor layer is formed on the second insulating layer and the first conductor layer; and the second conductor layer and the second insulating layer are exposed The first conductor layer is patterned to be in a second A plurality of third conductive layer is formed up strip, wherein the second direction is interleaved with the first direction. The method for manufacturing a non-volatile memory according to claim 7, wherein each of the first insulating layers has a total width of the conductor spacers on the sidewalls thereof, and the width of each of the first insulating layers is greater than the total width. One quarter and less than one-half of the total width. The method for manufacturing a non-volatile memory according to claim 7, wherein the method for forming the first conductor layer comprises: forming a conductor material layer on the charge trapping structure and covering the first insulating layer And the conductive spacers; and performing a planarization process to remove a portion of the conductive material layer until the first insulating layers are exposed. The method for manufacturing a non-volatile memory according to the seventh aspect of the invention, wherein the method for forming the second insulating layer comprises: forming a layer of insulating material on the first conductor layer and the first insulating layers; And performing a patterning process to remove a portion of the layer of insulating material in the first direction. A method of manufacturing a non-volatile memory, comprising: providing a substrate; forming a plurality of trenches in the substrate, wherein the trenches extend in a first direction; forming a charge trapping structure on the substrate; A plurality of doped regions are formed in the substrate at the bottom of the trenches, and the doped regions extend along the first direction; a first conductor layer is formed at the bottom of the trenches, and the first conductor layer is along Extending in the first direction; forming an insulating layer on the first conductor layer; and forming a plurality of strip-shaped second conductor layers on the charge trapping structure in a second direction, and the second conductor layers Filling the trenches, wherein the second direction is interlaced with the first direction. The method for fabricating a non-volatile memory according to claim 11, wherein the method for forming the first conductor layer comprises: forming a layer of a conductor material on the charge trapping structure and filling the trenches; An etching process is performed to remove a portion of the layer of conductive material and retain a portion of the layer of conductive material at the bottom of the trenches. The method for fabricating a non-volatile memory according to claim 11, wherein the method for forming the insulating layer comprises: forming a layer of insulating material on the charge trapping structure, filling the trenches; and performing etching The process removes a portion of the layer of insulating material and retains a portion of the layer of insulating material on the first layer of conductor. The method for fabricating a non-volatile memory according to claim 11, wherein the method for forming the second conductive layer comprises: forming a layer of a conductive material on the charge trapping structure and filling the trenches; And performing a patterning process to remove a portion of the layer of conductive material in the second direction. A method for operating a memory cell, comprising: providing a memory cell, as described in claim 1 or 3, applying a first voltage to the first gate when performing a stylization operation Applying a second voltage to the second gate, applying a third voltage to the first doped region, applying a fourth voltage to the second doped region, and applying a fifth voltage to the substrate. The method of operating a memory cell according to claim 15, wherein the first voltage is substantially the same as the second voltage when the stylizing operation is performed by channel hot electron injection, wherein the first voltage is between Between 9 volts and 13 volts; the second voltage is between 9 volts and 13 volts; one of the third voltage and the fourth voltage is 0 volts, and the third voltage and the fourth voltage are One is between 3.5 volts and 5.5 volts; the fifth voltage is 0 volts. The method of operating a memory cell according to claim 15, wherein when the stylizing operation is performed by the enhanced channel hot electron injection, one of the first voltage and the second voltage is between 9 volts and 13 volts. Between the first voltage and the second voltage, wherein the other is between 1.5 volts and 3 volts; one of the third voltage and the fourth voltage is 0 volts, and the third voltage and the fourth voltage The other of the voltages is between 3.5 volts and 5.5 volts; the fifth voltage is 0 volts. The method for operating a memory cell according to claim 15 , wherein after performing the stylizing operation, further comprising performing an erasing operation, and applying a first gate to the erasing operation a voltage of six; applying a seventh voltage to the second gate; applying an eighth voltage to the first doping region; applying a ninth voltage to the second doping region; and applying a tenth voltage to the substrate. The method for operating a memory cell according to claim 18, wherein when the erasing operation is performed by an energy band capable band thermal hole, one of the sixth voltage and the seventh voltage is 0 volts. Or between -11 volts and -15 volts, and the sixth voltage and the seventh voltage of the other one is between -11 volts and -15 volts; one of the eighth voltage and the ninth voltage It is 0 volts or floating, and the eighth voltage and the ninth voltage are between 4 volts and 5 volts; the tenth voltage is 0 volts. The method of operating a memory cell according to claim 15 , wherein after performing the stylizing operation, further comprising performing a read operation, and applying a read operation to the first gate An eleventh voltage; applying a twelfth voltage to the second gate; applying a thirteenth voltage to the first doping region; applying a fourteenth voltage to the second doping region; applying to the substrate A fifteenth voltage. The method of operating a memory cell according to claim 20, wherein one of the eleventh voltage and the twelfth voltage is between 5 volts and 9.5 volts, and the eleventh voltage and the tenth One of the two voltages is between 0 volts and 6 volts; one of the thirteenth voltage and the fourteenth voltage is between 0.7 volts and 1.6 volts, and the thirteenth voltage and the fourteenth voltage are The other is 0 volts; the fifteenth voltage is 0 volts. A method for manufacturing a non-volatile memory, comprising: providing a substrate; forming a plurality of strip-shaped first doped regions and a plurality of strip-shaped second doped regions in the substrate, the first doped regions And the second doped regions extend along a first direction, and the first doped regions and the second doped regions are alternately arranged; a charge trapping structure is formed on the substrate; and the charge trapping structure is formed on the substrate Forming a plurality of strip-shaped first gates, the first gates extending along the first direction, and each first gate is located on one of the first doped regions; the charge trapping structure Forming a plurality of strip-shaped second gates, the second gates extending along a second direction and located on the second doped regions, wherein the second direction is interlaced with the first direction; An inter-gate insulating layer is formed between the first gates and the second gates. The method for manufacturing a non-volatile memory according to claim 22, wherein the method of forming the first gate, the second gates, and the inter-gate insulating layer comprises: on the charge trapping structure a plurality of strip-shaped first insulating layers are formed, and the first insulating layers extend along the first direction; a conductor spacer is formed on sidewalls of each of the first insulating layers, and the conductive spacers are along the first Extending in a direction; forming a first conductor layer on the charge trapping structure, the first conductor layer covering the conductor spacers and exposing the first insulating layers; and the first conductor layer Forming a second insulating layer on the insulating layer, the second insulating layer exposing a portion of the first conductive layer in the first direction; forming a second conductive layer on the second insulating layer and the first conductive layer; And patterning the second conductor layer and the first conductor layer exposed by the second insulating layer to form a plurality of strip-shaped third conductor layers in the second direction, wherein the third conductor layers And the first conductor layer located below it constitutes the first Gate. The method of manufacturing a non-volatile memory according to claim 23, wherein each of the first insulating layers has a total width of a conductor spacer on a sidewall thereof, and a width of each of the first insulating layers is greater than the total width. One quarter and less than one-half of the total width. The method for fabricating a non-volatile memory according to claim 23, wherein the method for forming the first conductor layer comprises: forming a conductor material layer on the charge trapping structure and covering the first insulating layer And the conductive spacers; and performing a planarization process to remove a portion of the conductive material layer until the first insulating layers are exposed. The method for manufacturing a non-volatile memory according to claim 23, wherein the method for forming the second insulating layer comprises: forming a layer of insulating material on the first conductor layer and the first insulating layers; And performing a patterning process to remove a portion of the layer of insulating material in the first direction. The method for fabricating a non-volatile memory according to claim 23, wherein the forming of the first doping region and the second doping regions comprises using the first insulating layer and the conductors The spacer is a mask for the ion implantation process.