TWI493660B - Non-volatile memory and manufacturing method thereof - Google Patents

Description

Non-volatile memory and manufacturing method thereof

The present invention relates to a non-volatile memory and a method of fabricating the same, and more particularly to a non-volatile memory capable of avoiding a second bit effect and a method of fabricating the same.

Non-volatile memory has the advantage that it does not disappear after power-off, so many electrical products must have such memory to maintain the normal operation of the electrical products when they are turned on. In particular, flash memory has become a memory component widely used in personal computers and electronic devices because it has operations such as storing, reading, and erasing data.

Nitrile-based flash memory is a commonly used non-volatile memory. In a nitride flash memory, a two-bit data can be stored using a charge trapping structure composed of an oxide layer-nitride layer-oxide layer (i.e., a well-known ONO layer). In general, the two-bit data can be stored separately on the left side (ie, the left bit) or the right side (ie, the right bit) of the nitride layer in the charge trapping structure.

However, there is a second bit effect in the nitride flash memory, that is, when the left bit is read, it is affected by the right bit, or when the right bit is read, Will be affected by the left bit. In addition, as the memory size shrinks, the length of the channel is also shortened, causing the second bit effect to be more significant, thus affecting The operation window and component performance of the memory.

Embodiments of the present invention provide a non-volatile memory that avoids the generation of a second bit effect during operation.

Embodiments of the present invention further provide a method of fabricating a non-volatile memory that can produce a non-volatile memory having a large operational margin.

Embodiments of the present invention provide a non-volatile memory that includes a gate structure, a doped region, a charge storage layer, and a first dielectric layer. The gate structure is disposed on the substrate. There are recesses in the substrate on both sides of the gate structure. The gate structure includes a gate dielectric layer and a gate. The gate dielectric layer is disposed on the substrate, and the gate dielectric layer has an interface with the substrate. The gate is disposed on the gate dielectric layer. The doped region is disposed in the substrate surrounding the recess. The charge storage layer is disposed in the recess, and the top surface of the charge storage layer is higher than the above interface. The first dielectric layer is disposed between the charge storage layer and the substrate and between the charge storage layer and the gate structure.

According to the non-volatile memory of the embodiment of the invention, the distance is, for example, between 0.005 μm and 0.01 μm.

According to the non-volatile memory of the embodiment of the invention, the thickness of the charge storage layer is, for example, between 100 Å and 150 Å.

According to the non-volatile memory of the embodiment of the invention, the recess has, for example, a slanted side wall.

According to the non-volatile memory of the embodiment of the invention, the material of the charge storage layer is, for example, a nitride or a high dielectric constant material.

The non-volatile memory according to the embodiment of the invention further includes a second dielectric layer disposed on the charge storage layer, and a top surface of the second dielectric layer is coplanar with a top surface of the gate structure.

The non-volatile memory according to the embodiment of the invention further includes a conductor layer disposed on the second dielectric layer and the gate structure.

According to the non-volatile memory of the embodiment of the present invention, the doped region has a distance from the interface, and the recess has a bottom surface and at least one sidewall, and the doped region is disposed in the substrate below the bottom surface and surrounds the sidewall portion.

Embodiments of the present invention further provide a method of fabricating a non-volatile memory by forming a gate structure on a substrate. The gate structure includes a gate dielectric layer and a gate. The gate dielectric layer is on the substrate and has an interface between the gate dielectric layer and the substrate. The gate is located on the gate dielectric layer. Then, a recess is formed in the substrate on both sides of the gate structure. Next, a first dielectric layer is formed on the substrate and the gate structure. Then, a doped region is formed in the substrate around the recess. Thereafter, a charge storage layer is formed in the recess, and a top surface of the charge storage layer is higher than the above interface.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the distance is, for example, between 0.005 μm and 0.01 μm.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the thickness of the charge storage layer is, for example, between 100 Å and 150 Å.

According to the method of fabricating a non-volatile memory according to an embodiment of the invention, the recess has, for example, a slanted sidewall.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the material of the charge storage layer is, for example, a nitride or a high dielectric constant material.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, after forming the charge storage layer, the method further includes forming a second dielectric layer on the charge storage layer.

According to the method for fabricating a non-volatile memory according to the embodiment of the present invention, after forming the second dielectric layer, the method further includes performing a planarization process to remove a portion of the first dielectric layer and a portion of the second dielectric layer. Until the gate is exposed.

According to the method for fabricating a non-volatile memory according to the embodiment of the invention, after the planarization process is performed, the conductor layer is further formed on the second dielectric layer and the gate structure.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the doped region has a distance from the interface, and the recess has a bottom surface and at least one sidewall, and the doped region is formed in the substrate below the bottom surface and A part of the side wall.

Based on the above, in the non-volatile memory of the embodiment of the present invention, the charge storage layers for storing charges are respectively disposed on opposite sides of the gate structure, thereby increasing the channel length of the memory and avoiding the operation process. Produces a second bit effect and increases the operating margin.

The above general description and the following detailed description are exemplary and are not intended to limit the invention.

In order to make the above features and advantages of the present invention more apparent, the following The embodiments are described in detail with reference to the accompanying drawings.

1A-1D are cross-sectional views showing a process of fabricating a non-volatile memory according to an embodiment of the invention. First, referring to FIG. 1A, a substrate 100 is provided. The substrate 100 is, for example, a germanium substrate or a silicon on insulator (SOI) substrate. Then, a gate dielectric material layer (not shown) and a gate material layer (not shown) are sequentially formed on the substrate 100. The gate dielectric material layer is, for example, an oxide layer having a thickness of, for example, between 170 Å and 190 Å, and is formed by, for example, thermal oxidation or chemical vapor deposition. The gate material layer is, for example, a polysilicon layer, and the formation method thereof is, for example, a chemical vapor deposition method. The gate material layer and the gate dielectric material layer are then patterned to form the gate 104 and the gate dielectric layer 102. The width W1 of the gate 104 is, for example, between 0.05 μm and 0.1 μm. Gate dielectric layer 102 and gate 104 form a gate structure 106.

Then, referring to FIG. 1B, a recess 108 is formed in the substrate 100 on both sides of the gate structure 106. The formation of the recess 108 is, for example, an anisotropic etching process to remove a portion of the substrate 100. In the present embodiment, the recess 108 has inclined side walls, but the present invention is not limited thereto. In other embodiments, the recess 108 can also have vertical sidewalls. Next, a dielectric layer 110 is formed on the substrate 100 and the gate structure 106. The dielectric layer 110 is, for example, an oxide layer having a thickness of, for example, between 50 Å and 100 Å, and is formed by, for example, thermal oxidation or chemical vapor deposition.

Next, please refer to FIG. 1C, in the substrate 100 around the recess 108. A doped region 112 is formed. In detail, the recess 108 has a bottom surface 108a and at least one side wall 108b, and the doping region 112 is formed in the substrate 100 below the bottom surface 108a and surrounds a portion of the side wall 108b. The method of forming the doping region 112 is, for example, performing an ion implantation process. The depth of the doped region 112 is, for example, between 0.05 μm and 0.09 μm. What is important is that there is an interface 113 between the gate dielectric layer 102 and the substrate 100, and the doped region 112 does not contact the interface 113, that is, there is a distance D1 therebetween. The distance D1 is, for example, between 0.005 μm and 0.01 μm. The doped regions 112 on both sides of the gate structure 106 serve as the source and drain regions of the non-volatile memory, respectively. Then, the charge storage layer 114 is formed in the recess 108 to complete the fabrication of the non-volatile memory of the embodiment, and the dielectric layer 110 between the charge storage layer 114 and the substrate 100 functions as a tunneling dielectric layer. use. The top surface of the charge storage layer 114 is higher than the interface 113. The material of the charge storage layer 114 is, for example, a nitride or a high dielectric constant material, and has a thickness of, for example, between 100 Å and 150 Å. The charge storage layer 114 is formed by, for example, depositing a charge storage material layer in the recess 108 and then performing an etch back process to remove a portion of the charge storage material layer.

Thereafter, referring to FIG. 1D , after the charge storage layer 114 is formed, the dielectric layer 116 may also be formed on the charge storage layer 114 . Dielectric layer 116 is, for example, an oxide layer. The dielectric layer 116 is formed by, for example, depositing a layer of dielectric material on the charge storage layer 114, and then performing a planarization process to remove portions of the dielectric layer 116 and the dielectric layer 110 until the gate 104 is exposed. Next, a conductor layer 118 is formed over the dielectric layers 116, 110 and the gate structure 106. Conductor layer 118 can be used to place the non-volatile memory of the present embodiment The gate 104 is connected to the gate of an adjacent non-volatile memory (not shown), that is, the conductor layer 118 is used as a word line.

In the non-volatile memory of the embodiment, the charge storage layers 114 for storing charges are respectively disposed on opposite sides of the gate structure 106, so that the channel length of the memory can be effectively prevented from being too short during the operation process. The second bit effect is generated and the operation margin is increased.

Further, in the non-volatile memory of the present embodiment, since the doping region 112 and the interface 113 have a distance D1 instead of being interconnected, the charge can be effective when the non-volatile memory of the embodiment is operated. The charge storage layer 114 is implanted.

Moreover, since the top surface of the charge storage layer 114 is higher than the interface 113, it is possible to prevent charges from being directly injected into the dielectric layer 116 above the charge storage layer 114 through the dielectric layer 110.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Base

102‧‧‧gate dielectric layer

104‧‧‧ gate

106‧‧‧ gate structure

108‧‧‧ dent

108a‧‧‧ bottom

108b‧‧‧ sidewall

110, 116‧‧‧ dielectric layer

112‧‧‧Doped area

113‧‧‧ interface

114‧‧‧Charge storage layer

118‧‧‧Conductor layer

D1‧‧‧ distance

W1‧‧‧Width

1A-1D are cross-sectional views showing a process of fabricating a non-volatile memory according to an embodiment of the invention.

100‧‧‧Base

102‧‧‧gate dielectric layer

104‧‧‧ gate

106‧‧‧ gate structure

108‧‧‧ dent

108a‧‧‧ bottom

108b‧‧‧ sidewall

110‧‧‧ dielectric layer

112‧‧‧Doped area

113‧‧‧ interface

114‧‧‧Charge storage layer

D1‧‧‧ distance

Claims (17)

A non-volatile memory comprising: a gate structure disposed on a substrate, wherein the substrate has a recess in two sides of the gate structure, the gate structure comprising: a gate dielectric layer disposed on the substrate An interface between the gate dielectric layer and the substrate; and a gate disposed on the gate dielectric layer; a doped region disposed in the substrate around the recess; and a charge storage layer Disposed in the recess, and a top surface of the charge storage layer is higher than the interface; and a first dielectric layer disposed between the charge storage layer and the substrate and the charge storage layer and Between the gate structures. The non-volatile memory of claim 1, wherein the charge storage layer has a thickness of between 100 Å and 150 Å. The non-volatile memory of claim 1, wherein the recess has a sloped sidewall. The non-volatile memory of claim 1, wherein the material of the charge storage layer comprises a nitride or a high dielectric constant material. The non-volatile memory of claim 1, further comprising a second dielectric layer disposed on the charge storage layer, and a top surface of the second dielectric layer and the gate structure The top surface is coplanar. The non-volatile memory of claim 5, further comprising a conductor layer disposed on the second dielectric layer and the gate structure on. The non-volatile memory of claim 1, wherein the doped region has a distance from the interface, the recess has a bottom surface and at least one sidewall, and the doped region is disposed in the A portion of the substrate below the bottom surface and surrounding the sidewall. The non-volatile memory of claim 7, wherein the distance is between 0.005 μm and 0.01 μm. A method of fabricating a non-volatile memory, comprising: forming a gate structure on a substrate, the gate structure comprising: a gate dielectric layer on the substrate, between the gate dielectric layer and the substrate Having an interface; and a gate on the gate dielectric layer; forming a recess in the substrate on both sides of the gate structure; forming a first dielectric layer on the substrate and the gate structure; A doped region is formed in the substrate around the recess; a charge storage layer is formed in the recess, a top surface of the charge storage layer being higher than the interface. The method for fabricating a non-volatile memory according to claim 9, wherein the charge storage layer has a thickness of between 100 Å and 150 Å. The method of fabricating the non-volatile memory of claim 9, wherein the recess has a sloped sidewall. The method for fabricating a non-volatile memory according to claim 9, wherein the material of the charge storage layer comprises a nitride or a high medium. Electrical constant material. The method of fabricating a non-volatile memory according to claim 9, wherein after forming the charge storage layer, a second dielectric layer is further formed on the charge storage layer. The method for fabricating a non-volatile memory according to claim 13 , wherein after forming the second dielectric layer, further comprising performing a planarization process to remove a portion of the first dielectric layer and a portion The second dielectric layer until the gate is exposed. The method for fabricating a non-volatile memory according to claim 14, wherein after the planarizing process is performed, a conductor layer is further formed on the second dielectric layer and the gate structure. The method for fabricating a non-volatile memory according to claim 14, wherein the doped region has a distance from the interface, the recess has a bottom surface and at least one sidewall, and the doped region Formed in the substrate below the bottom surface and surrounding a portion of the sidewall. The method for fabricating a non-volatile memory according to claim 16, wherein the distance is between 0.005 μm and 0.01 μm.