TWI499041B - Non-volatile memory and manufacturing method thereof - Google Patents

Description

Non-volatile memory and method of manufacturing same

The present invention relates to a non-volatile memory and a method of fabricating the same, and more particularly to a non-volatile memory having a germanium/yttria/tantalum nitride/yttria/ytterbium (SONOS) structure and a method of fabricating the same .

A non-volatile memory has the advantage of allowing multiple data to be stored, read, or erased, and the stored data does not disappear after power is turned off. Conventional non-volatile memory is mainly a polycrystalline germanium material as a charge storage layer.

Since tantalum nitride has the property of trapping electrons, in the prior art, tantalum nitride is mostly used as a charge trapping layer to replace the polysilicon floating gate. A layer of yttrium oxide is usually present on the tantalum nitride charge trapping layer to form a charge tunneling layer and a charge blocking layer, respectively, to form an oxide-nitride-oxide (ONO) composite layer. . Such non-volatile memory components are commonly referred to as germanium/yttria/tantalum nitride/yttria/germanium (SONOS) memory components.

The SONOS memory element includes a planar type structure and a sidewall type structure depending on the arrangement position of the tantalum nitride charge trapping layer. The tantalum nitride charge trapping layer of the planar SONOS memory device is sandwiched between the tantalum oxide layers, and two tantalum layers are disposed above and below the tantalum oxide layer, which are respectively polysilicon gates (control gates) and矽 substrate. However, the planar SONOS memory component replaces the gate oxide layer with an ONO structure, so it is incompatible with the current logic process, and will cause an increase in process complexity, thereby affecting the performance of the logic component.

In addition, the tantalum nitride charge trapping layer of the sidewall type SONOS memory device is disposed on the sidewall of the gate or on the sidewall of the gate and a portion of the germanium substrate. Therefore, when operating a sidewall type SONOS memory device, electrons are driven into the tantalum nitride charge trapping layer, which is susceptible to electron drift and affects the operating speed and charge storage capability of the device.

The object of the present invention is to provide a non-volatile memory and a manufacturing method thereof, which can avoid the problem of encountering electronic drift without affecting component performance, and in particular, can be compatible with current logic processes without causing process complication.

The present invention provides a non-volatile memory comprising: a substrate, a gate dielectric layer, a gate conductive layer, a nitride layer, a first oxide layer, and a second oxide layer. Wherein, the gate dielectric layer is disposed on the substrate, and the side edges of the two ends of the gate dielectric layer have grooves. The gate conductive layer is disposed on the gate dielectric layer, and the bottom width thereof is greater than the width of the gate dielectric layer, and the gate conductive layer, the substrate and the gate dielectric layer form a symmetric opening. The nitride layer is located on the sidewall of the gate conductive layer and extends in the opening. The first oxide layer is located at the sidewall and the bottom of the gate conductive layer, and is disposed between the gate conductive layer, the nitride layer and the gate dielectric layer. ‧ the second oxide layer is located on the substrate, and is disposed on the gate Between the electrical layer, the nitride layer and the substrate.

In a preferred embodiment of the present invention, the non-volatile memory includes a second lightly doped region, a spacer, and a source/drain region. Wherein, the two lightly doped regions are symmetrically disposed in the substrate adjacent to both sides of the nitride layer. The spacer is disposed on the nitride layer of the sidewall of the gate conductive layer and is located on the substrate. The source/drain regions are disposed in the substrate on both sides of the spacer.

In a preferred embodiment of the present invention, the non-volatile memory includes a second lightly doped region, a spacer, and a source/drain region. The two lightly doped regions are respectively disposed in a substrate adjacent to one side of the nitride layer, and are disposed under the nitride layer and extending in a substrate adjacent to the other side of the nitride layer. The spacer is disposed on the nitride layer of the sidewall of the gate conductive layer and is located on the substrate. The source/drain regions are disposed in the substrate on both sides of the spacer.

In a preferred embodiment of the invention, the material of the gate conductive layer is, for example, polysilicon or doped polysilicon.

In a preferred embodiment of the invention, the gate dielectric layer has a thickness of 150 to 180 angstroms ( )between.

In a preferred embodiment of the invention, the opening has a horizontal depth of 100 to 500 angstroms ( )between.

In a preferred embodiment of the present invention, the first oxide layer and the second oxide layer have the same thickness and a thickness of 60 to 70 angstroms ( )between.

In a preferred embodiment of the present invention, the thickness of the portion of the nitride layer disposed in the opening is 30 to 40 angstroms ( )between.

The invention further provides a method of manufacturing a non-volatile memory. First, a gate structure is formed on the substrate, the gate structure including a gate dielectric layer and a gate conductive layer. Then, a portion of the gate dielectric layer is removed, a symmetric opening is formed between the pole conductive layer, the substrate and the gate dielectric layer, and a recess is formed at a side of both ends of the gate dielectric layer. Thereafter, a first oxide layer is formed on the sidewall and the bottom of the gate conductive layer, and a second oxide layer is formed on the surface of the substrate. Subsequently, a nitride material layer is formed to cover the gate structure, the first oxide layer, the second oxide layer and the substrate, and is filled in the opening. Then, an etching process is performed to remove a portion of the nitride material layer to form a nitride layer on the sidewall of the gate conductive layer, and the nitride layer extends in the opening.

In a preferred embodiment of the invention, the method of removing a portion of the gate dielectric layer is, for example, a wet etching process or a dry etching process.

In a preferred embodiment of the present invention, the method of forming the first oxide layer and the second oxide layer described above is, for example, an oxidation process.

In a preferred embodiment of the invention, the method of forming the nitride material layer is, for example, a low pressure vapor deposition method.

In a preferred embodiment of the invention, after the formation of the nitride layer, a second lightly doped region may also be formed in the substrate below the nitride layer. Then, a spacer is formed on the sidewall of the gate structure to cover the nitride layer. Next, a source/drain region is formed in the substrate on both sides of the spacer. In one embodiment, the two lightly doped regions are symmetrically formed in a substrate adjacent to both sides of the nitride layer. In another embodiment, the two lightly doped regions are respectively formed in a substrate adjacent to one side of the nitride layer, and formed under the nitride layer and extending into the substrate adjacent to the other side of the nitride layer.

In a preferred embodiment of the invention, the material of the gate conductive layer is, for example, polysilicon or doped polysilicon.

In a preferred embodiment of the invention, the gate dielectric layer has a thickness of 150 to 180 angstroms ( )between.

In a preferred embodiment of the invention, the opening has a horizontal depth of 100 to 500 angstroms ( )between.

In a preferred embodiment of the present invention, the first oxide layer and the second oxide layer have the same thickness and a thickness of 60 to 70 angstroms ( )between.

In a preferred embodiment of the invention, the portion of the nitride layer formed in the opening has a thickness of 30 to 40 angstroms ( )between.

Since the present invention does not replace the gate dielectric layer with an ONO structure, it is compatible with current logic processes and does not affect the performance of logic elements. In addition, in the non-volatile memory of the present invention, a part of the nitride layer (charge trapping layer) is formed between the gate conductive layer and the substrate, so that the problem of encountering electron drift can be avoided without affecting the component. Operating speed and charge storage capability, and high stylization/erasing performance at low operating voltages. Moreover, the method of the present invention does not increase the number of masks and complicates the process.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1 is a schematic cross-sectional view of a non-volatile memory according to an embodiment of the present invention.

Referring to FIG. 1 , the non-volatile memory 100 includes a substrate 101 , a gate dielectric layer 102 , a gate conductive layer 104 , a first oxide layer 106 , a nitride layer 110 , and a second oxide layer 108 . Among them, the substrate 101 is, for example, a germanium substrate. The gate dielectric layer 102 is disposed on the substrate 101, and the sides of the gate dielectric layer 102 have grooves 103. The gate dielectric layer 102 is, for example, an oxide layer made of, for example, tantalum oxide, and the gate dielectric layer 102 has a thickness of, for example, 150 to 180 angstroms ( )between.

The gate conductive layer 104 is disposed on the gate dielectric layer 102, and the bottom width of the gate conductive layer 104 is greater than the bottom width of the gate dielectric layer 102. Moreover, a symmetric opening 105 is formed between the gate conductive layer 104, the substrate 101 and the gate dielectric layer 102. The horizontal depth of the opening 105 is, for example, 200 angstroms ( ), preferably, for example, 100 to 500 angstroms ( )between. The material of the gate conductive layer 104 is, for example, polysilicon or doped polysilicon, which serves as a control gate.

In addition, the nitride layer 110 of the non-volatile memory 100 is a charge trapping layer as a memory element to store charge. The nitride layer 110 is located on the sidewall of the gate conductive layer 104 and extends in the opening 105. The material of the nitride layer 110 is, for example, tantalum nitride, and the thickness of the portion of the nitride layer 110 in the extended configuration is, for example, 30 to 40 angstroms ( )between.

The first oxide layer 106 is disposed between the gate conductive layer 104, the nitride layer 110, and the gate dielectric layer 102, and is located at the sidewall and the bottom of the gate conductive layer 104. The material of the first oxide layer 106 is, for example, ruthenium oxide, and its thickness is, for example, 60 to 70 angstroms ( )between. In addition, the second oxide layer 108 is disposed between the substrate 101, the gate dielectric layer 104 and the nitride layer 110, and is located on the substrate 101. The material of the second oxide layer 108 is, for example, ruthenium oxide, and its thickness is, for example, 60 to 70 angstroms ( )between.

In the above, the second oxide layer 108 and the first oxide layer 106 of the non-volatile memory 100 serve as a charge tunneling layer and a charge blocking layer, respectively, and the nitride layer 110 constitutes an ONO structure. The gate conductive layer 104, the above-described ONO structure and the substrate 101 are referred to as SONOS memory.

In particular, the ONO structure of the present invention does not affect the fabrication of the gate dielectric layer, as compared to the conventional planar SONOS memory, which replaces the gate dielectric layer with an ONO structure. Relatively reduce the complexity of the process.

On the other hand, in the non-volatile memory of the present invention, a part of the nitride layer 110 is disposed between the gate conductive layer 104 and the substrate 101. Therefore, the structure of the present invention can avoid the problem of encountering electronic drift compared to the conventional sidewall type SONOS memory, and does not affect the operating speed and charge storage capability of the element.

In addition, please refer to FIG. 2, which is a cross-sectional view of a non-volatile memory according to another embodiment of the present invention.

The non-volatile memory 100 of the present embodiment further includes two lightly doped regions 112, 114, a spacer 117, and a source/drain region 120. The lightly doped region 114 is disposed in the substrate 101 adjacent to the side of the nitride layer 110. The lightly doped region 112 is located in the substrate 101 below the nitride layer 110 and extends in the substrate 101 adjacent to the other side of the nitride layer 110.

The spacer 117 is disposed on the nitride layer 110 on the sidewall of the gate conductive layer 104 and is located on the substrate 101. The spacer 117 is, for example, a composite layer composed of a ruthenium oxide layer 116 and a tantalum nitride layer 118. The source/drain regions 120 are disposed in the substrate 101 on both sides of the spacer 117, respectively.

The lightly doped region 112 and the lightly doped region 114 of the non-volatile memory 100 of the present embodiment form an asymmetric lightly doped region, the structure of which is capable of storing unit data.

In addition, please refer to FIG. 3, which is a cross-sectional view of a non-volatile memory according to still another embodiment of the present invention. The non-volatile memory 100a of the present embodiment is different from the non-volatile memory 100 of FIG. 2 in that the lightly doped region 112a of the non-volatile memory 100a and the lightly doped region 114a are symmetrically disposed adjacent to each other. The nitride layer 110 is in the substrate 101 on both sides, and its structure is capable of storing double-bit data.

Next, a method of producing the non-volatile memory of the present invention will be described. 4A to 4H are cross-sectional views showing the flow of a method of manufacturing a non-volatile memory according to an embodiment of the present invention.

First, referring to FIG. 4A, a substrate 400 is provided. This substrate 400 is, for example, a crucible substrate. A gate dielectric material layer 402 is then formed over the substrate 400. The gate dielectric material layer 402 is, for example, an oxide layer made of, for example, ruthenium oxide, and the gate dielectric material layer 402 is formed by, for example, a thermal oxidation method. The thickness of the gate dielectric material layer 402 is, for example, 150 to 180 angstroms ( )between.

Thereafter, referring to FIG. 4A, a gate conductive material layer 404 is formed on the gate dielectric material layer 402. The material of the gate conductive material layer 404 is, for example, polysilicon or doped polysilicon. The method for forming the gate conductive material layer 404 is formed by, for example, forming an undoped polysilicon layer by chemical vapor deposition, performing an ion implantation step, or forming a chemical vapor phase by using a field implant dopant. The deposition method is formed.

Next, referring to FIG. 4B, the gate conductive material layer 404 and the gate dielectric material layer 402 are patterned to form the gate structure 406. The gate structure 406 includes a gate conductive layer 405 and a gate dielectric layer 403. The gate conductive layer 405 serves as a control gate. The patterning method described above is, for example, forming a patterned photoresist layer (not shown) on the gate conductive material layer 404. Then, the etching process is performed by using the patterned photoresist layer as a mask, and a portion of the gate conductive material layer 404 and the gate dielectric material layer 402 are removed to form a gate conductive layer 405 and a gate dielectric layer 403. Gate structure 406. The patterned photoresist layer is then removed.

Next, referring to FIG. 4C, a portion of the gate dielectric layer 403 is removed to form a recess 408 at the sides of the gate dielectric layer 403. Moreover, after removing a portion of the gate dielectric layer 403, a symmetric opening 410 is also formed between the gate conductive layer 405, the substrate 400, and the gate dielectric layer 403. The horizontal depth of the opening 410 is, for example, 200 angstroms ( ), preferably, for example, 100 to 500 angstroms ( )between. The method of removing the gate dielectric layer 403 of the above portion is, for example, a wet etching process or a dry etching process.

Then, referring to FIG. 4D, a first oxide layer 412 is formed on the sidewall and the bottom of the gate conductive layer 405, and a second oxide layer 414 is formed on the surface of the substrate 400. The first oxide layer 412 and the second oxide layer 414 are formed by, for example, performing an oxidation process 411 to simultaneously form a first oxide layer 412 and a second oxide on the surface of the gate conductive layer 405 and the substrate 400. Object layer 414. The oxidation process 411 is, for example, a thermal oxidation process, and the process temperature thereof is, for example, less than 800 °C. The material of the first oxide layer 412 and the second oxide layer 414 is, for example, ruthenium oxide, and the thickness thereof is, for example, 60 to 70 angstroms ( )between.

Subsequently, referring to FIG. 4E, a layer of nitride material 416 is formed to cover the gate structure 406, the first oxide layer 412, the second oxide layer 414, and the substrate 400. Moreover, a nitride material layer 416 is also filled into the opening 410. The method of forming the nitride material layer 416 is, for example, a low pressure vapor deposition method, and the material thereof is, for example, tantalum nitride.

Next, referring to FIG. 4F, an etching process is performed to remove a portion of the nitride material layer 416 to form a nitride layer 418. In particular, the nitride layer 418 is formed on the sidewall of the gate conductive layer 405, and the nitride layer 418 is extended in the opening 410. The thickness of the partial nitride layer 110 of the above extended configuration is, for example, 30 to 40 angstroms ( )between.

Thereafter, referring to FIG. 4G, a doping process is performed to form two lightly doped regions 420, 422 in the substrate 400. The lightly doped region 420 is formed in the substrate 400 adjacent to the nitride layer 418, and the lightly doped region 422 is formed under the nitride layer 418 and extends on the substrate 400 adjacent to the other side of the nitride layer 418. in. The method of forming the lightly doped region 422 is, for example, using a tilt-angle implant after the doping process to extend the lightly doped region portion into the channel below the nitride layer 418.

In addition, the above-mentioned two lightly doped regions may be symmetrically disposed, for example, in the substrate 400 adjacent to both sides of the nitride layer 418 (not shown).

Next, referring to FIG. 4H, after the lightly doped regions 420, 42 are formed, the process of fabricating the spacers 427 and the source/drain regions 428 can be continued. The spacer 427 is, for example, a composite layer composed of a ruthenium oxide layer 424 and a tantalum nitride layer 426. The method of forming the spacers 427 and the source/drain regions 428 is well known to those of ordinary skill in the art and will not be described again.

As can be seen from the above, the method of the present invention does not replace the gate dielectric layer with an ONO structure, and thus is compatible with current logic processes without affecting the performance of the logic elements.

Moreover, in the method of the present invention, a gate dielectric layer is etched such that a portion of the nitride layer can be formed between the gate conductive layer and the substrate, and oxidation is formed simultaneously above and below the nitride layer by an oxidation process. The layer is formed to form an ONO structure. Therefore, the method of the present invention does not increase the number of masks, which complicates the process, and does not have the problem of being susceptible to electron drift.

Next, the integrated manufacturing process of the non-volatile memory of the present invention and the current logic process will be further described.

5A-5E are cross-sectional views showing the flow of a current logic process according to another embodiment of the present invention.

First, referring to FIG. 5A, a gate dielectric material layer 506 and a gate conductive material layer 508 are sequentially formed on the logic element region 502 and the memory region 504 of the substrate 500.

Then, referring to FIG. 5B, a capping layer (not shown) is formed on the gate conductive material layer 508 of the logic element region 502 of the substrate 500. Then, the gate conductive material layer 508 and the gate dielectric material layer 506 of the memory region 504 are patterned to form the gate conductive layer 508a and the gate dielectric layer 506a.

Then, referring to FIG. 5C, after the gate conductive material layer 508 and the gate dielectric material layer 506 of the memory region 504 are patterned, the gate dielectric layer 506b and the first oxide layer 510 may be further formed. The process of the second oxide layer 512, the nitride layer 514, and the lightly doped regions 516, 518. The method for forming the gate dielectric layer 506b, the first oxide layer 510, the second oxide layer 512, the nitride layer 514, and the two lightly doped regions 516 is non-volatile with an embodiment of the present invention. The method of manufacturing the memory is the same and will not be described here.

Of course, after the above process of forming the non-volatile memory, the subsequent general logic process can be continued. Next, the overlay (not shown) of the logic element region 502 is removed. Then, another cover layer (not shown) is formed in the memory region 504. Subsequently, the gate conductive material layer 508 and the gate dielectric material layer 506 of the logic element region 502 are patterned to form a gate conductive layer 508b and a gate dielectric layer 506c (as shown in FIG. 5D).

Thereafter, referring to FIG. 5E, the overlay (not shown) of the memory region 504 is removed. Next, the spacer 516 and the source/drain region 518 are simultaneously fabricated on the logic element region 502 and the memory region 504.

Next, the operation of the non-volatile memory of the present invention will be described by taking the structure of FIG. 2 as an example.

Referring again to FIG. 2, the non-volatile memory 100 is operated by applying a bias voltage of, for example, +3 to +5 volts to the source/drain region 114 during a program operation; The /pole region 112 is applied with a bias voltage of, for example, 0 volts; the gate conductive layer 104 is applied with a bias voltage of, for example, +6 volts; and the substrate 101 is applied with a bias voltage of, for example, 0 volts or -1 to -2 volts. In this way, electrons can be implanted into the nitride layer (charge trapping layer) 110 on the source/drain region 113 side by channel hot electron injection.

When an erase operation is performed, a bias voltage of, for example, +3 to +5 volts may be applied to the source/drain region 114; a source/drain region 112 is applied with a bias voltage of, for example, 0 volts; and the gate is electrically conductive; Layer 104 is applied, for example, at a bias of -6 volts; substrate 101 is applied, for example, at a bias of 0 volts to utilize the FN tunneling effect or band-to-band hot hole injection to store the original Data erase.

In addition, a bias voltage of, for example, 0 volts may be applied to the source/drain region 114 during the read operation; a bias voltage of, for example, 1.5 volts is applied to the source/drain region 112; and the gate conductive layer 104 is applied. The substrate 101 is biased, for example, at a voltage of 0 volts to read information stored in the non-volatile memory 100.

Since, in the structure of the non-volatile memory of the present invention, a part of the nitride layer (charge trapping layer) is formed between the gate conductive layer and the substrate. Therefore, compared to conventional non-volatile memory, a strong vertical electric field can be generated on the ONO structure, which can achieve higher stylization/erasing performance at low operating voltages.

In summary, the non-volatile memory of the present invention and the method of manufacturing the same have at least the following advantages:

1. The present invention is compatible with current logic processes and can relatively reduce the complexity of the process without affecting the performance of the logic components.

2. The present invention is capable of avoiding the problem of encountering electronic drift without affecting the operating speed and charge storage capability of the component.

3. The method of the present invention does not increase the number of masks, which complicates the process.

4. The non-volatile memory of the present invention is capable of achieving high stylization/erasing performance at low operating voltages.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100. . . Non-volatile memory

101, 400, 500. . . Base

102, 403, 506a, 506b, 506c. . . Gate dielectric layer

103,408. . . Groove

104, 405, 508a, 508b. . . Gate conductive layer

105, 410. . . Opening

106, 412, 510. . . First oxide layer

108, 414, 512. . . Second oxide layer

110, 118, 418, 514. . . Nitride layer

112, 114, 112a, 114a, 420, 422, 516. . . Lightly doped area

116. . . Cerium oxide layer

117, 516. . . Clearance wall

120, 428, 518. . . Source/bungee area

402, 506. . . Gate dielectric material layer

404, 508. . . Gate conductive material layer

406. . . Gate structure

411. . . Oxidation process

416. . . Nitride material layer

502. . . Logic component area

504. . . Memory area

1 is a schematic cross-sectional view of a non-volatile memory according to an embodiment of the present invention.

2 is a schematic cross-sectional view of a non-volatile memory according to another embodiment of the present invention.

3 is a cross-sectional view showing a non-volatile memory according to still another embodiment of the present invention.

4A to 4H are cross-sectional views showing the flow of a method of manufacturing a non-volatile memory according to an embodiment of the present invention.

5A-5E are cross-sectional views showing the flow of a current logic process according to another embodiment of the present invention.

100. . . Non-volatile memory

101. . . Base

102. . . Gate dielectric layer

103. . . Groove

104. . . Gate conductive layer

105. . . Opening

106. . . First oxide layer

108. . . Second oxide layer

110, 118. . . Nitride layer

112, 114. . . Lightly doped area

116. . . Cerium oxide layer

117. . . Clearance wall

120. . . Source/bungee area

Claims (20)

A non-volatile memory comprising: a substrate; a gate dielectric layer disposed on the substrate, a side of the gate dielectric layer having a recess; a gate conductive layer disposed on the gate And a bottom dielectric layer having a width greater than a width of the gate dielectric layer, and the gate conductive layer, the substrate and the gate dielectric layer form a symmetric opening; a nitride layer a vertical portion is disposed on the sidewall of the gate conductive layer, and a horizontal portion extending in the opening; a first oxide layer is located at a sidewall and a bottom of the gate conductive layer, and is disposed at the gate conductive a layer, between the nitride layer and the gate dielectric layer; and a second oxide layer on the substrate and disposed between the gate dielectric layer, the nitride layer and the substrate. The non-volatile memory of claim 1, further comprising: a lightly doped region symmetrically disposed in the substrate adjacent to both sides of the nitride layer; a spacer disposed with the gate The nitride layer on the sidewall of the conductive layer is located on the substrate; and a source/drain region is disposed in the substrate on both sides of the spacer. The non-volatile memory of claim 1, further comprising: a lightly doped region disposed in the substrate adjacent to one side of the nitride layer, and located below the nitride layer and extending In the substrate adjacent to the other side of the nitride layer; a spacer wall on the nitride layer on the sidewall of the gate conductive layer and on the substrate; and a source/drain region disposed on the substrate In the substrate on both sides of the spacer. The non-volatile memory of claim 1, wherein the material of the gate conductive layer comprises polycrystalline germanium or doped polysilicon. The non-volatile memory of claim 1, wherein the gate dielectric layer has a thickness of between 150 and 180 Å. The non-volatile memory of claim 1, wherein the opening has a horizontal depth of between 100 and 500 angstroms (Å). The non-volatile memory of claim 1, wherein the first oxide layer and the second oxide layer have the same thickness and a thickness of between 60 and 70 Å. The non-volatile memory of claim 1, wherein a portion of the nitride layer disposed in the opening has a thickness of between 30 and 40 Å. A method of fabricating a non-volatile memory, comprising: forming a gate structure on a substrate, the gate structure comprising a gate dielectric layer and a gate conductive layer; removing a portion of the gate dielectric layer Forming a symmetrical opening between the gate conductive layer, the substrate and the gate dielectric layer, and forming a recess at a side of the gate dielectric layer; forming a sidewall and a bottom of the gate conductive layer a first oxide layer, and a second oxide layer formed on the surface of the substrate; forming a nitride material layer to cover the gate structure, the first oxide layer, the second oxide layer and the substrate And filling in the opening; and performing an etching process to remove a portion of the nitride material layer to form a nitride layer on the sidewall of the gate conductive layer, and the nitride layer has a vertical portion located at the gate A sidewall of the pole conductive layer, and a horizontal portion extending in the opening. The method of manufacturing a non-volatile memory according to claim 9, wherein the method of removing a portion of the gate dielectric layer comprises performing a wet etching process or a dry etching process. The method for producing a non-volatile memory according to claim 9, wherein the method of forming the first oxide layer and the second oxide layer comprises performing an oxidation process. The method for producing a non-volatile memory according to claim 9, wherein the method for forming the nitride material layer comprises a low pressure vapor deposition method. The method of manufacturing a non-volatile memory according to claim 9, wherein after forming the nitride layer, further comprising: forming a lightly doped region in the substrate below the nitride layer; A sidewall of the gate structure forms a spacer to cover the nitride layer; and a source/drain region is formed in the substrate on both sides of the spacer. The method of manufacturing a non-volatile memory according to claim 13, wherein the two lightly doped regions are symmetrically formed in the substrate adjacent to both sides of the nitride layer. The method of manufacturing a non-volatile memory according to claim 13, wherein the two lightly doped regions are respectively formed in the substrate adjacent to one side of the nitride layer, and are formed under the nitride layer. And extending into the substrate adjacent to the other side of the nitride layer. The method for manufacturing a non-volatile memory according to claim 9, wherein the material of the gate conductive layer comprises polycrystalline germanium or doped polysilicon. The method of manufacturing a non-volatile memory according to claim 9, wherein the gate dielectric layer has a thickness of 150 to 180 angstroms ( )between. The method of manufacturing a non-volatile memory according to claim 9, wherein the opening has a horizontal depth of 100 to 500 angstroms ( )between. The method for producing a non-volatile memory according to claim 9, wherein the first oxide layer and the second oxide layer have the same thickness and a thickness of 60 to 70 angstroms ( )between. The method of manufacturing a non-volatile memory according to claim 9, wherein a portion of the nitride layer formed in the opening has a thickness of 30 to 40 angstroms ( )between.