TWI438655B - Backside illuminated imaging sensor and method of making a backside illuminated imaging sensor with a seal ring support - Google Patents

Description

Backside illuminated imaging sensor and method of making a backside illuminated imaging sensor with a seal ring support

The present invention relates generally to imaging sensors, and more particularly, but not exclusively, to backside illumination ("BSI") imaging sensors.

A semiconductor wafer or die, such as an image sensor die, is fabricated on a single semiconductor wafer along with hundreds, and in some cases thousands, of the same die. The cutting used to separate a semiconductor wafer into individual dies can be performed with a die saw, such as a diamond saw. The dicing is performed along a region (referred to as a scribe line) separating the non-functional semiconductor material of each of the dies. The use of a diamond saw introduces mechanical stress into the semiconductor wafer and can cause cracking at the edge of the die and compromises the integrity and reliability of the integrated circuit. One structure for making the crystal grains less susceptible to mechanical stress from the grain saw is a seal ring. A sealing ring in the die is formed in or on an outer region of one or more of the dielectric layers to protect the integrated circuit from contaminants (eg, sodium) and to make the die less susceptible to the die saw The mechanical stress caused.

Today, many semiconductor imaging sensors are front-illuminated. That is, it includes an imaging array fabricated on the front side of the semiconductor wafer, wherein the light system is received from the same front side at the imaging array. However, frontal illumination imaging sensors have a number of disadvantages, one of which is a limited fill factor.

The backside illuminated imaging sensor is an alternative to a frontal illumination imaging sensor that addresses the fill factor problem associated with frontal illumination. The backside illuminated imaging sensor includes an imaging array fabricated on a front surface of the semiconductor wafer, but receives light through the back surface of the wafer. Color filters and microlenses may be included on the back surface of the wafer to improve the sensitivity of the backlighting sensor. However, in order to detect light from the back side, the wafer must be extremely thin. The thickness of the wafer can also be reduced to improve sensitivity. However, the thinner the wafer, the more susceptible it is to physical damage during various stages of manufacture. That is, as semiconductor wafers become thinner, semiconductor wafers become weaker, making back-illuminated imaging sensor wafers even more susceptible to mechanical stress from the die saw.

In one embodiment, a backside illumination imaging sensor includes: an epitaxial layer having an imaging array formed in a front side of the epitaxial layer, wherein the imaging array is adapted to receive one of the epitaxial layers a light on the back side; a metal stack coupled to the front side of the epitaxial layer, wherein the metal stack includes a seal ring formed in an edge region of one of the imaging sensors; an opening from the epitaxial layer The back side extends to one of the metal rings of the seal ring to expose the metal pad; and a seal ring support disposed on the metal pad and disposed within the opening to structurally support the seal ring.

In another embodiment, a backside illumination imaging sensor includes: an epitaxial layer having an imaging array formed in a front side of the epitaxial layer, wherein the imaging array is adapted to receive from the epitaxial layer a light on the back side; a metal stack coupled to the front side of the epitaxial layer, wherein the metal stack includes a seal ring formed in an edge region of one of the image sensors; an opening from the bar The back side of the crystal layer extends to one of the metal pads of the seal ring to expose the metal pad; and a member disposed on the metal pad and disposed in the opening for structurally supporting the seal ring.

In another embodiment, a method of fabricating a backlight illumination imaging sensor includes: providing a backside illumination imaging sensor, the imaging sensor comprising: an epitaxial layer having a layer formed on the epitaxial layer An imaging array in a front surface, wherein the imaging array is adapted to receive light from a back side of the epitaxial layer; a metal stack coupled to the front side of the epitaxial layer, wherein the metal stack includes a photo formation a sealing ring in one of the edge regions of the sensor; etching an opening extending from the back surface of the epitaxial layer to a metal pad of the sealing ring to expose the metal pad; depositing a material on the epitaxial layer The back side of the layer is deposited in the opening; and the material is etched to form a seal ring support on the metal pad and within the opening to structurally support the seal ring.

The non-limiting and non-exhaustive embodiments of the present invention are described with reference to the accompanying drawings, wherein, unless otherwise indicated,

Embodiments of a backside illuminated sensor having a seal ring support structure are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. It will be appreciated by those skilled in the art, however, that the technology described herein may be practiced or practiced in other methods, components, materials, etc. without one or more of the specific details. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

The reference to "an embodiment" in this specification means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, appearances of the phrase "in an embodiment" Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Directional terms (such as "top", "bottom", "above" and "below") are used with reference to the orientation of the depicted figures.

FIG. 1A is a diagram illustrating a semiconductor wafer 100 including a plurality of dies 111 to 119. Semiconductor wafer 100 may comprise germanium or gallium arsenide or other semiconductor materials. FIG. 1B is a diagram illustrating the semiconductor wafer 100 and the dies 111 to 119 in more detail. The scribe lines 150 and 151 separate adjacent dies. The kerf zone 152 shows the area where the scribe lines 150 and 151 intersect. The grain regions near the scribe lane region 152 are generally more susceptible to mechanical stress caused by the die saw because the die saw traverses the semiconductor wafer 100 twice in this region, once along the scribe line 150 and another system Along the cutting path 151. This situation is in contrast to zones 153 and 154, where the die saw is typically only passed once.

2A is a plan or bottom plan view of a backside illuminated image sensor 200 having a seal ring support 260A, in accordance with an embodiment of the present invention. A seal ring support 260A is formed on the back side of the seal ring, which in turn is formed in or on the outer region 205 of the image sensor 200 and surrounds the integrated circuit region 220. In an embodiment, the outer region 205 includes only non-functional semiconductor materials. That is, in an example, the outer region 205 may not include any integrated circuitry, and the integrated circuit region 220 may include one or more pixel arrays, readout circuitry, control circuitry, and other functional logic. Moreover, the outer region 205 can extend from the integrated circuit region 220 to the outer edge 207 of the image sensor 200.

The sealing ring can protect the integrated circuit region 220 from contaminants (eg, sodium), and can make the metal interconnect of the BSI image sensor 200 and the dielectric layer of the semiconductor substrate less susceptible to the die saw or Mechanical stress caused by other processes that separate a plurality of grains formed on a semiconductor wafer into individual dies. In FIG. 2A, the seal ring support 260A has a width w and is disposed within the outer region 205 between the integrated circuit region 220 and the outer edge 207 of the image sensor 200. In an embodiment, the seal ring support 260A has a width such that the seal ring support 260A extends to the outer edge 207. The seal ring support 260A may comprise an oxide, a nitride or an alloy of a metal such as aluminum or tungsten or other metal. The seal ring may have the same width as the width w of the seal ring support 210, or the seal ring may have a width greater than or less than w.

2B is a plan or bottom plan view of a BSI image sensor 200 having a seal ring support 260B in accordance with another embodiment of the present invention. The seal ring support 260B has two widths w ₁ and w ₂ . BSI image sensors in the corner regions around the corner 225, the seal ring support member 215 has a width W of 200 _1, w ₁ is greater than the width of the side regions along the seal ring support member 215 of BSI image sensors 200 230 width w ₂ . In the illustrated embodiment of FIG. 2B embodiment, the seal ring support member 225 in the corner region of the larger width w 260B at the intersection of _two scribe line to the sealing ring provides a larger support (Referring back to Figure 1B, where the intersection of the scribe lines such as The corners of the grains 112, 113, 115 and 116 in the zone are more susceptible to mechanical stresses due to the die saw than the scribe lane zones 153 and 154). The seal ring may have / the same width as the width of the support member 215 and the sealing rings, or sealing ring may have a greater or smaller than w ₁ or w ₂ and the.

3 is a cross-sectional view of a BSI image sensor 300 having a seal ring support 360 taken along section line 3-3' of FIG. 2A, in accordance with an embodiment of the present invention. The BSI image sensor 300 includes a device layer 310 and a carrier substrate 320. Device layer 310 includes an epitaxial layer 330 and a metal stack 340. Components such as a photosensitive region, a source region of the transistor, and a drain region are included in the imaging array 331. The imaging array 331 and the peripheral circuit 332 are disposed in an epitaxial (epi) layer 330. A metal stack 340 is formed on the front side of the epitaxial layer 330.

Dielectric layer 341 separates adjacent metal interconnect layers of metal stack 340 and separates the metal interconnect layers from epitaxial layer 330 and carrier substrate 320. In this embodiment, metal stack 340 includes three metal interconnect layers. In other embodiments of the invention, metal stack 340 may have more or fewer metal layers. In some embodiments, the metal interconnect layers M1, M2, and M3 can comprise tungsten, aluminum, copper, aluminum copper alloys, or other alloys.

Imaging array 331 is formed in the front side of epitaxial layer 330 and is configured to receive light from the back side of epitaxial layer 330, which may also be the back side of device layer 310. Imaging array 331 can include an array of imaging pixels configured in a plurality of columns and rows. Peripheral circuitry 332 can include readout circuitry, functional logic, and control circuitry. A color filter (not shown) is optionally included in the BSI image sensor 300 to implement a color imaging sensor, and the microlens 333 is optionally included in the BSI image sensor 300 to focus the light onto the imaging array. On the array of imaging pixels in 331. An optional color filter and microlens 333 can be disposed on the back side of the device layer 310.

Carrier substrate 320 is coupled or bonded to the front side of device layer 310 to provide structural support to BSI image sensor 300. Please note that the illustrated embodiment of BSI image sensor 300 is not drawn to scale. That is, the carrier substrate 320 may have a thickness that is much larger than the thickness of the device layer 310. For example, carrier substrate 320 can be approximately 100 times thicker than device layer 310. In some embodiments, the carrier substrate 320 is fabricated separately and then bonded to the front side of the device layer 310 by methods such as press bonding.

The sealing ring 343 is formed in the outer edge region of the dielectric layer 341 and surrounds the integrated circuit region. The integrated circuit region includes the peripheral circuit 332 and the imaging array 331. The metallization layer of the seal ring 343 is connected to the upper metal M3 from the lower metal M1 by via holes. The opening 350 is formed to etch the metal pad 342 of the metal interconnect M1 by etching the back side of the epitaxial layer 330 through the entire depth of the epitaxial layer 330 and through the dielectric layer 341. The opening 350 may have a width 311 of 3 μm to 50 μm and a depth of 0.5 μm to 5 μm. The seal ring support 360 may comprise an oxide, a nitride or an alloy of a metal such as aluminum or tungsten or other metal, and has a thickness of tens or hundreds of nanometers. In an embodiment, the seal ring support 360 includes a metal, wherein the seal ring support 360 and the seal ring 343 function as and serve as a signal busbar for the imaging sensor 300. For example, the seal ring support 360 and the seal ring 343 can be used as a ground bus or as a power bus for the imaging sensor 300. In the present embodiment, the seal ring 343 (like the metal interconnect layer) includes three metal layers, and in other embodiments, the seal ring 343 can include a smaller number of metal layers than the number of metal interconnect layers.

As shown in FIG. 3, the seal ring support 360 includes a first horizontal portion 351, a vertical portion 353, and a second horizontal portion 355. The support width of the seal ring support 360 can be adjusted by adjusting the width 311 of the opening 350 and/or by masking more or less the second horizontal portion 355 on the back side of the epitaxial layer 330. For example, the seal ring support 360 can be formed by masking the support material such that the seal ring support 360 extends over the back side of the epitaxial layer 330 to the outer edge 307. Passivation layer 370 provides planarization on the back side of device layer 310. A microlens 333 is formed on the back surface of the passivation layer 370.

4 is a flow chart illustrating an embodiment of a process 400 for fabricating a BST image sensor wafer 500 having a seal ring support 560 (see FIGS. 5A-5D). The order in which some or all of the process blocks appear in each process should not be considered as limiting. In fact, it will be understood by those skilled in the art having the benefit of this disclosure that some of the process blocks can be performed in various sequences not illustrated.

In process block 405, carrier wafer 520 is wafer bonded to the front side of device wafer 510 to provide structural support to the imaging sensor prior to thinning the back side of device wafer 510, as seen in Figure 5A. In one embodiment, carrier wafer 520 is bonded to device wafer 510 by methods such as press bonding. The back side of device wafer 510 or epitaxial layer 530 is then thinned in process block 407. The epitaxial layer 530 can be thinned to a thickness in the range of from about 1 μm to about 10 μm.

In process block 410, any mixed backside processing can be performed. For example, any back implant or anneal can be performed in process block 410. In process block 415, seal ring support opening 550 is etched down through the back side of epitaxial layer 530 into dielectric layer 541 to expose metal pad 542 of metal interconnect layer M1, as seen in FIG. 5B. The seal ring support opening 550 may have a width of 3 μm to 50 μm and a depth of 0.5 μm to 5 μm. In process step 420, a seal ring support material is deposited onto the back side of the epitaxial layer 530 and the seal ring support material is etched away in areas where the seal ring support material is not required. These regions include at least the region directly above the imaging array 531 of each BSI image sensor die 501 and 502 on the back side of the device wafer 510. In some embodiments, the seal ring support 560 in the region directly above the peripheral circuit 532 on the back side of the device wafer 510 can be etched away. Seal ring support 560 can comprise an oxide, a nitride, or an alloy of a metal such as aluminum or tungsten or other metal. The seal ring support 560 may have a thickness of several tens to several hundreds of nanometers.

In process block 425, a passivation material 570 is deposited on the back side of device wafer 510 to provide planarization, as seen in Figure 5D. In process block 435, the fabrication of BSI image sensor dies 501 and 502 is accomplished by steps such as forming microlenses 533 and dicing the dies from the semiconductor wafer along scribe lines 503.

FIG. 6 is a block diagram illustrating a backlight illumination imaging sensor 600 in accordance with an embodiment of the present invention. The illustrated embodiment of imaging sensor 600 includes imaging array 605, readout circuitry 610, functional logic 615, and control circuitry 620.

Imaging array 605 is a two-dimensional ("2D") array of backlighting imaging sensors or pixels (eg, pixels P1, P2, ..., Pn). In one embodiment, each pixel is an active pixel sensor ("APS"), such as a complementary metal oxide semiconductor ("CMOS") imaging pixel. As illustrated, each pixel is configured into columns (eg, columns R1 through Ry) and rows (eg, rows C1 through Cx) to obtain image data for a person, place, or object, which image data can then be used to present people, places, Or 2D image of the object.

After each pixel has acquired its image data or image charge, the image data is read by readout circuit 610 and transmitted to function logic 615. Readout circuitry 610 can include an amplification circuit, an analog to digital ("ADC") conversion circuit, or other circuitry. The function logic 615 can store only image data or even by applying post-image effects (eg, trimming, spinning) Turn image, turn red eye, adjust brightness, adjust contrast, or other operations to manipulate image data. Control circuit 620 is coupled to pixel array 605 to control the operational characteristics of pixel array 605.

7 is a circuit diagram illustrating an embodiment of two four-electrode ("4T") pixel pixel circuits 700 within a BSI imaging array in accordance with an embodiment of the present invention. Pixel circuit 700 is one possible pixel circuit architecture for implementing each pixel within pixel array 605 of FIG. 6, but it should be understood that embodiments of the invention are not limited to 4T pixel architecture; in fact, benefit from the present invention Those of ordinary skill in the art will appreciate that the teachings of the present invention are also applicable to 3T designs, 5T designs, and various other pixel architectures. In FIG. 7, the BSI pixels Pa and Pb are arranged in two columns and one row. The illustrated embodiment of each pixel circuit 700 includes a photodiode PD, a transfer transistor T1, a reset transistor T2, a source follower ("SF") transistor T3, and a select transistor T4. During operation, the transfer transistor T1 receives a transfer signal TX that transfers the charge accumulated in the photodiode PD to the floating diffusion node FD. In an embodiment, the floating diffusion node FD can be coupled to a storage capacitor for temporarily storing image charges. The reset transistor T2 is coupled between the power rail VDD and the floating diffusion node FD to be reset (eg, discharging or charging the FD to a preset voltage) under the control of the reset signal RST. The floating diffusion node FD is coupled to control the gate of the SF transistor T3. The SF transistor T3 is coupled between the power rail VDD and the selection transistor T4. The SF transistor T3 is used as a source follower that provides a high impedance output from the pixel. Finally, the select transistor T4 selectively couples the output of the pixel circuit 700 to the readout row line under the control of the select signal SEL. In one embodiment, the TX signal, the RST signal, and the SEL signal are generated by control circuit 620.

The above description of the illustrated embodiments of the invention, including the description of the invention, is not intended to be It will be appreciated by those skilled in the art that the present invention may be described in the context of the present invention, and various modifications are possible within the scope of the invention.

The present invention may be modified in accordance with the above detailed description. The terms used in the following claims should not be construed as limiting the invention to the specific embodiments disclosed in the specification. The scope of the invention is to be determined by the scope of the following claims, and the scope of the following claims will be understood in accordance with the defined principles of the claims.

100. . . Semiconductor wafer

111-119. . . Grain

150. . . cutting line

151. . . cutting line

152. . . Cutting road area

153. . . Area

154. . . Area

200A. . . Back lighting image sensor

200B. . . Back lighting image sensor

205. . . External area

207. . . Outer edge

220. . . Integrated circuit area

225. . . Corner area

230. . . Side area

260A. . . Seal ring support

260B. . . Seal ring support

300. . . BSI image sensor

307. . . Outer edge

310. . . Device layer

311. . . width

320. . . Carrier substrate

330. . . Epitaxial layer

331. . . Imaging array

332. . . Peripheral circuit

333. . . Microlens

340. . . Metal stack

341. . . Dielectric layer

342. . . Metal pad

343. . . Sealing ring

350. . . Opening

351. . . First horizontal part

353. . . Vertical part

355. . . Second horizontal part

360. . . Seal ring support

370. . . Passivation layer

500. . . BST image sensor wafer

501. . . BSI image sensor die

502. . . BSI image sensor die

503. . . cutting line

510. . . Device wafer

520. . . Carrier wafer

530. . . Epitaxial layer

531. . . Imaging array

532. . . Peripheral circuit

541. . . Dielectric layer

542. . . Metal pad

550. . . Seal ring support opening

560. . . Seal ring support

600. . . Back lighting imaging sensor

605. . . Pixel array

610. . . Readout circuit

615. . . Functional logic

620. . . Control circuit

700. . . Pixel circuit

C1-Cx. . . Row

FD. . . Floating diffusion node

M1. . . Metal interconnect layer

M2. . . Metal interconnect layer

M3. . . Metal interconnect layer

P1-Pn. . . Pixel

Pa. . . BSI pixel

Pb. . . BSI pixel

PD. . . Light diode

R1-Ry. . . Column

SF. . . Source follower

T1. . . Transfer transistor

T2. . . Reset transistor

T3. . . Source follower transistor

T4. . . Select transistor

VDD. . . Power rail

1A is a diagram illustrating a semiconductor wafer having integrated circuit dies as shown;

1B is a diagram illustrating the integrated circuit die shown in FIG. 1A in more detail;

2A is a plan or bottom plan view of a backside illuminated image sensor having a seal ring support in accordance with an embodiment of the present invention;

2B is a plan or bottom plan view of a backside illuminated image sensor having a seal ring support in accordance with another embodiment of the present invention;

3 is a cross-sectional view of a backside illuminated image sensor having a seal ring support taken along section line 3-3' of FIG. 2A, in accordance with an embodiment of the present invention;

4 is a flow chart illustrating a method of fabricating a backside illuminated imaging sensor having a seal ring support in accordance with an embodiment of the present invention;

5A is a cross-sectional view illustrating an embodiment of a partially fabricated backside illuminated image sensor wafer;

5B is a cross-sectional view showing an embodiment of a partially fabricated backside illuminated image sensor wafer having an opening for a seal ring support;

5C is a cross-sectional view of an embodiment of a partially fabricated backside illuminated image sensor wafer after deposition of a seal ring support material lining the seal ring support opening;

5D is a cross-sectional view illustrating an embodiment of a partially fabricated backside illuminated image sensor wafer after deposition of a passivation material;

6 is a block diagram illustrating an embodiment of a BSI image sensor die; and

7 is a circuit diagram illustrating pixel circuits of two four-electrode ("4T") pixels within an embodiment of a BSI imaging array.

300. . . BSI image sensor

307. . . Outer edge

310. . . Device layer

311. . . width

320. . . Carrier substrate

330. . . Epitaxial layer

331. . . Imaging array

332. . . Peripheral circuit

333. . . Microlens

340. . . Metal stack

341. . . Dielectric layer

342. . . Metal pad

343. . . Sealing ring

350. . . Opening

351. . . First horizontal part

353. . . Vertical part

355. . . Second horizontal part

360. . . Seal ring support

370. . . Passivation layer

M1. . . Metal interconnect layer

M2. . . Metal interconnect layer

M3. . . Metal interconnect layer

Claims (15)

A backside illuminated imaging sensor comprising: an epitaxial layer having an imaging array formed in a front side of the epitaxial layer, wherein the imaging array is adapted to receive light from a back side of the epitaxial layer a metal stack coupled to the front side of the epitaxial layer, wherein the metal stack includes a seal ring formed in an edge region of one of the imaging sensors; an opening from the back of the epitaxial layer Extending to one of the metal rings of the seal ring to expose the metal pad; and a seal ring support disposed on the metal pad and disposed within the opening to structurally support the seal ring, wherein the seal ring support is The back illumination imaging sensor has a first width in a corner region, and wherein the seal ring support has a second in the side region of the back illumination imaging sensor different from the first width width. A backside illumination imaging sensor of claim 1, wherein the imaging array is disposed in an integrated circuit region of the backside illumination imaging sensor, and wherein the sealing ring surrounds the integrated circuit region. A backside illuminated imaging sensor of claim 1, wherein the seal ring support has a width that is greater than a width of one of the openings. A backside illumination imaging sensor of claim 1, wherein the first width is greater than the second width. A backside illuminated imaging sensor of claim 1, wherein the seal ring support comprises: a first horizontal portion disposed on the metal pad; a second horizontal portion disposed on the back surface of the epitaxial layer; and a vertical portion disposed in the first horizontal portion and the second horizontal portion between. A backside illuminated imaging sensor of claim 5, wherein the second horizontal portion extends to an outer edge of the one of the backside illuminated imaging sensors. The backlight illumination imaging sensor of claim 1, wherein the metal stack comprises a metal interconnect layer and a dielectric layer disposed between the front surface of the epitaxial layer and the metal interconnect layer, wherein A metal pad is included in the metal interconnect layer. A backside illuminated imaging sensor of claim 1, wherein the seal ring support is a metal, a nitride or an oxide. A backside illuminated imaging sensor of claim 1, wherein the imaging array is a complementary metal oxide semiconductor ("CMOS") imaging array. A method of fabricating a backside illuminated imaging sensor having a seal ring support, the method comprising: providing a backside illumination imaging sensor, the imaging sensor comprising: an epitaxial layer having a protrusion formed thereon An imaging array in a front side of one of the crystal layers, wherein the imaging array is adapted to receive light from a back side of the epitaxial layer; a metal stack coupled to the front side of the epitaxial layer, wherein the metal stack includes formation a sealing ring in one of the edge regions of the imaging sensor; etching an opening extending from the back surface of the epitaxial layer to the Sealing a metal pad to expose the metal pad; depositing a material on the back surface of the epitaxial layer and depositing in the opening; and etching the material to form a seal ring support on the metal pad and within the opening To structurally support the seal ring, wherein the seal ring support has a first width in a corner region of the back illumination imaging sensor, and wherein the seal ring support is at the back illumination imaging sensor One of the side regions has a second width that is different from the first width. The method of claim 10, wherein etching the material to form the seal ring support comprises removing the material from a region of the backside of the epitaxial layer that is directly above the imaging array. The method of claim 10, further comprising masking the material prior to etching the material. The method of claim 10, wherein depositing the material comprises depositing a metal, nitride or oxide on the back side of the epitaxial layer. The method of claim 10, further comprising depositing a planarization layer on the back side of the epitaxial layer and the seal ring support. The method of claim 10, further comprising separating the backside illuminated imaging sensor from an adjacent backside illuminated imaging sensor along a scribe line after forming the seal ring support.