HK1172152B - Wafer dicing using scribe line etch - Google Patents

Description

Wafer dicing using scribe line etching

Technical Field

The present invention relates to wafer-level chip scale packaging and, more particularly, but not exclusively, to enhancing the reliability of die separation of semiconductor chips fabricated from low-k dielectric materials.

Background

Semiconductor chips or dies, such as image sensor chips, are typically fabricated on a single semiconductor wafer along with hundreds (and in some cases, several) copies of the same die. The dicing required to separate individual dies from a semiconductor wafer, a process known as "dicing" or "wafer dicing," may be performed by a die saw, such as a diamond saw. Dicing is performed along non-functional areas of the semiconductor material, called scribe lines, which separate the dies on the wafer from each other. The use of a diamond saw introduces mechanical stress to the semiconductor wafer and can lead to cracking at the die edge, compromising the integrity and reliability of the devices on the die. An alternative to diamond saws are laser scribing, which involves scanning a laser beam over the scribe lanes of a semiconductor wafer, but this solution has low throughput and the equipment required is expensive.

The ever increasing demand for image sensors with faster processing speeds and better image quality while reducing the physical size of the image sensor chip has resulted in smaller pixel cell sizes and smaller photosensitive areas or photodiodes. Advances in CMOS technology, such as the use of materials with low dielectric constants k (referred to as low-k dielectrics) that reduce cross-coupling and parasitic capacitance between the metal layers making up the metal interconnects, are used to keep pace with ever decreasing image sensor chip sizes. However, low-k dielectrics are brittle due to their porous nature, which makes image sensors with low-k dielectrics prone to flaking and cracking when diamond saws are used to separate dies on semiconductor wafers.

Another way to increase the size of the photodiode in a pixel cell, in addition to using low-k dielectrics, is to use a backside illuminated ("BSI") image sensor. BSI image sensors include an array of pixels fabricated on the front side of a semiconductor wafer, but receive light through the back surface of the image sensor. During the fabrication of BSI image sensors, image sensor chips or devices are first fabricated on a semiconductor wafer. When all necessary elements have been formed in or on the device wafer, the device wafer is bonded to a carrier wafer for further processing. Bond strength may be maximized due to trade-offs in parameters such as bond strength and wafer deformation, but this may cause weakening at the bond interface. This combination of low-k dielectric and weak bond interface in the device wafer can increase the incidence of flaking and cracking when a diamond saw is used to dice BSI dies from the combined wafer (device wafer plus carrier wafer).

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

Fig. 1A is a plan view illustrating a semiconductor wafer.

Fig. 1B is a plan view illustrating in more detail the spacing between individual dies formed on the semiconductor wafer in fig. 1A.

Fig. 2A is a cross-sectional view of a backside illuminated (BSI) image sensor after separating the dies from the wafer.

Fig. 2B is a cross-sectional view of a Front Side Illuminated (FSI) image sensor after separating the dies from the wafer.

Fig. 3 is a flow chart illustrating an embodiment of a process for separating BSI image sensor dies from a semiconductor wafer.

Fig. 4A is a cross-sectional view of a fully fabricated embodiment of a BSI image sensor wafer.

Fig. 4B is a cross-sectional view of a fully fabricated embodiment of a BSI image sensor wafer having a mask to expose scribe lines.

Fig. 4C is a cross-sectional view of a fully fabricated embodiment of a BSI image sensor wafer after etching is used to remove the street portions of the exposed device wafer.

Fig. 4D is a cross-sectional view of a fully fabricated embodiment of a BSI image sensor after a die saw is used to remove exposed semiconductor material of the carrier wafer.

Fig. 5 is a flow chart illustrating an embodiment of a process for separating FSI image sensor dies from a semiconductor wafer.

Fig. 6A is a cross-sectional view of a fully fabricated embodiment of an FSI image sensor wafer.

Fig. 6B is a cross-sectional view of a fully fabricated embodiment of an FSI image sensor wafer with a mask to expose dicing streets.

Fig. 6C is a cross-sectional view of a fully fabricated embodiment of an FSI image sensor wafer after etching is used to remove the street portions of the exposed device wafer.

Fig. 6D is a cross-sectional view of a fully fabricated embodiment of the FSI image sensor after using a die saw to remove exposed semiconductor material of the carrier wafer.

Fig. 7 is a block diagram illustrating an embodiment of an image sensor die, which may be a BSI image sensor die or an FSI image sensor die.

Fig. 8 is a circuit diagram illustrating pixel circuitry for two four-transistor ("4T") pixels within an embodiment of a BSI or FSI imaging array.

Detailed Description

Embodiments of methods for separating dies comprising low dielectric constant (i.e., low-k) dielectric materials from a wafer on which the dies are formed are described below. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the technology described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Directional terminology, such as "top," "down," and "below …," is used with reference to the orientation of the figures being described.

Fig. 1A is a diagram illustrating a semiconductor wafer 100 including a plurality of individual dies 110, 120, 130, and 140. The term "die" is a generic term that refers to devices formed in the wafer 100 or formed on the wafer 100. In one embodiment, one or more individual dies on the wafer 100 may be Front Side Illuminated (FSI) or Back Side Illuminated (BSI) Complementary Metal Oxide Semiconductor (CMOS) image sensors. In other embodiments, the die formed in the wafer 100 or on the wafer 100 may be one or more other electronic, optical, or hybrid electronic/optical devices in addition to CMOS sensors. In various embodiments, the semiconductor wafer 100 may be composed of silicon or gallium arsenide or other semiconductor materials.

Fig. 1B is a diagram illustrating semiconductor wafer 100 and dies 110, 120, 130, and 140 in more detail. The individual dies 110, 120, 130, and 140 are formed on the wafer 100 such that non-functional wafer spaces exist between the dies. In the illustrated embodiment, non-functional space 150 is between dies 110 and 120 and between dies 130 and 140, and non-functional space 151 is between dies 110 and 130 and between dies 120 and 140. Often, individual dies are formed on the wafer 100 such that these non-functional spaces together form lines separating all of the individual dies formed on the wafer. These non-functional areas of the wafer 100 are referred to as streets, and individual dies, such as dies 110, 120, 130, and 140, are diced from the wafer 100 along the streets (when the dies are completed).

Fig. 2A is a cross-sectional view of a backside illuminated (BSI) image sensor 200 after die separation. BSI image sensor 200 includes a device layer 210 bonded to a carrier substrate 220. Device layer 210 includes an epitaxial ("epi") layer 230 and a metal stack 240. The optical components of the image sensor, such as the photosensitive regions, and the electronic components of the integrated circuit containing the image sensor, such as the source and drain regions that make up the transistors, may be found in epi layer 230. The optical and electronic components of the image sensor are typically formed on or near the front side 232 of the epi layer.

Metal stack 240 is formed on front side 232 of epi layer 230, with microlens array 211 formed on back side 234 of epi layer 230. Within metal stack 240, low-k dielectric 242 separates adjacent metal interconnect layers 246 and vias 248 of metal stack 240. In the illustrated embodiment, low-k dielectric 242 is shown as a single, uniform layer, but in other embodiments low-k dielectric 242 may comprise multiple layers of dielectric. In one embodiment where low-k dielectric 242 has multiple layers, all of the layers may be low-k dielectrics, but in other multi-layer embodiments, low-k dielectric 242 may include both low-k and non-low-k dielectric layers. For example, embodiments may use low-k dielectrics in lower metal layers (layers closer to front surface 232), where cross-coupling between metal layers is more likely to be a problem, and non-low-k dielectrics for higher metal layers (layers farther from front surface 232). Dielectric layer 244 covers low-k dielectric layer 242 to complete the metal stack; in one embodiment, the dielectric layer 244 is a material such as silicon dioxide (named SiO)₂) Although the dielectric layer 244 may be a low-k dielectric in other embodiments. In the illustrated embodiment, the metal stack240 include three metal layers (three interconnect layers 246), but in other embodiments, metal stack 240 may have more or fewer metal layers.

The carrier substrate 220 is bonded to the dielectric layer 244, and thus to the metal stack 240 and to the device layer 210. During fabrication of a wafer of BSI image sensors, epi layer 230 is thinned using processes such as grinding and/or chemical-mechanical polishing (CMP) so that radiation incident on back surface 234 can better reach photosensitive elements formed closer to front surface 232. The primary function of carrier substrate 220 is to support device layer 210 during backside thinning or other operations performed on epi layer 230.

Fig. 2B illustrates an embodiment of a front-side illuminated (FSI) image sensor 250. FSI image sensor 250 is similar in most respects to BSI image sensor 200. As with BSI image sensor 200, FSI image sensor 250 includes an epitaxial ("epi") layer 252 and a metal stack 240. Optical components of the image sensor, such as the photosensitive regions, and electronic components of the integrated circuit containing the image sensor, such as the source and drain regions that make up the transistors, may be found in epi layer 252. The optical and electronic components of the image sensor are typically formed on or near the front side 254 of the epi layer.

The primary structural differences between BSI image sensor 200 and FSI image sensor 250 are the location of microlens array 211, the thickness of epi layer 252, and the presence of carrier substrate 220. In FSI image sensor 250, light is incident on front side 254 of epi layer 252 via metal stack 240, and thus microlens array 211 is formed on top of metal stack 240, and in particular dielectric layer 244 in the illustrated embodiment. Because radiation is incident on the front side of FSI image sensor 250, epi layer 252 need not be thinned to improve the transmission of light to the photosensitive elements. Thus, epi layer 252 of FSI image sensor 250 is substantially thicker than epi layer 230 of BSI image sensor 200. This lack of need to thin epi layer 252 results in the final major structural differences: BSI image sensor 200 includes carrier substrate 220 and FSI image sensor 250 does not include carrier substrate 220.

Fig. 3 and 4A-4D together illustrate an embodiment of a process for cutting BSI image sensor dies from a wafer. Fig. 3 is a flow chart illustrating a process 300, and fig. 4A-4D show a process application for separating (dicing) BSI image sensor dies 401 and 402 from a semiconductor wafer 400. The order in which some or all of the process blocks appear in each process should not be construed as limiting. Conversely, those skilled in the art having the benefit of the present disclosure will appreciate that the process blocks may be performed in a variety of orders not illustrated. For example, in the illustrated embodiment, etching is performed first, followed by sawing, but in other embodiments, the relevant portions may be sawed first, and the remaining portions etched later.

In process block 305, the fabrication of BSI image sensor dies 401 and 402 is completed. The optical and electronic components of the BSI image sensor, including diffusion regions (not shown), implant regions (not shown), and pixel circuitry (not shown), have been formed in epi layer 430 or on epi layer 430, following conventional techniques. As seen in fig. 4A, a color filter (not shown) and microlens array 411 are formed on the back surface 434 of epi layer 430, and a metal stack 440 is formed on the front surface 432. Low-k dielectric 442 separates adjacent metal layers of metal stack 440, while dielectric 444 separates low-k dielectric layer 442 from carrier wafer 420. Carrier wafer 420 is bonded to dielectric layer 444 and thus device wafer 410 to form wafer 400. On wafer 400, BSI image sensor dies 401 and 402 are separated by dicing streets 403.

In process block 310, mask 450 is formed on back surface 434 of epi layer 430 (and thus on the back surface of device wafer 410), but with openings therein that expose back surface 434 in areas substantially aligned with streets 403 of device wafer 410, as shown in fig. 4B. In one embodiment, mask 450 is formed by depositing a layer of photoresist on back surface 434 and photolithographically patterning and etching the photoresist to expose portions of back surface 434 that are substantially aligned with streets 403. In other embodiments, other methods and materials may be used to form mask 450.

In process block 315, as shown in FIG. 4C, an etch is used to remove device wafer material not masked by mask 450. The semiconductor material of the device wafer 410 may be removed (starting at the back side 434, through the thickness of the device wafer 410 down to the carrier wafer 420) using either a dry reactive etch or a wet etch. The etch stops at an intermediate position between the two surfaces of the wafer 400; in the illustrated embodiment, the intermediate position is in the carrier wafer 420 proximate to the bonding interface between the device wafer 410 and the carrier wafer 420. By using etching to remove the low-k dielectric material of device wafer 410 at scribe line 403 instead of using a die saw, the incidence of peeling and cracking of device wafer 410 due to the mechanical stress of the die saw may be reduced or eliminated. Also, by extending the etch through at least the bonding interface between the device wafer 410 and the carrier wafer 420, problems caused by sawing across the bonding interface are eliminated.

In process block 320, as shown in fig. 4D, a die saw is used to remove the remaining semiconductor material of carrier wafer 420 at scribe line 403. The result is that dies 401 and 402 are cut out of the wafer and separated from each other. Because the device wafer material of device wafer 410 at scribe line 403 has been removed in the etching step, the mechanical stress introduced by the die saw will not affect the low-k dielectric layer in device wafer 410 or the bonding interface between device wafer 410 and carrier wafer 420.

The introduction of this two-step die separation technique adds to the cost of the manufacturing sequence, but an increase in the number of good dies per wafer will offset that additional cost. Additional benefits also derive from a reduction in stress cracking on the sides of the die metallization stack, which is known to lead to reliability failures over time.

Fig. 5 and 6A-6D together illustrate an embodiment of a process for cutting FSI image sensor dies from a wafer. Fig. 5 is a flow chart illustrating process 500, while fig. 6A-6D show an application of the process for separating (dicing) FSI image sensor dies 601 and 602 from semiconductor wafer 600. The order in which some or all of the process blocks appear in each process should not be construed as limiting. Rather, those skilled in the art, having the benefit of the present disclosure, will appreciate that the process blocks may be performed in a variety of sequences not illustrated. For example, in the illustrated embodiment, etching is performed first, followed by sawing, but in other embodiments, the relevant portions may be sawed first, and the remaining portions etched later.

In process block 505, the fabrication of FSI image sensor die 601 and 602 is completed. The optical and electronic components of the FSI image sensor, including diffusion regions (not shown), implant regions (not shown), and pixel circuitry (not shown), have been formed in epi layer 630 or on epi layer 630, following conventional techniques. Low-k dielectric 642 separates adjacent metal layers of metal stack 640 and dielectric 644 is formed over low-k dielectric 642. As seen in fig. 6A, a color filter (not shown) and a microlens array 611 are formed on a dielectric layer 644. On wafer 600, FSI image sensor dies 601 and 602 are separated by dicing streets 603.

In process block 510, a mask 650 is formed over dielectric layer 644 (and thus over the front side of device wafer 610), but with openings therein that expose dielectric layer 644 in regions substantially aligned with streets 603 of device wafer 610, as shown in fig. 6B. In one embodiment, mask 650 is formed by depositing a layer of photoresist on dielectric layer 644 and photolithographically patterning and etching the photoresist to expose portions of dielectric layer 644 that are substantially aligned with scribe line 603. In other embodiments, other methods and materials may be used to form mask 650.

In process block 515, as shown in fig. 6C, an etch is used to remove device wafer material not masked by mask 650. A dry reactive etch or a wet etch may be used to remove the dielectric layer in metal stack 640 (from the front side of device wafer 610, through the thickness of the metal stack down to epi layer 630). The etch stops after it passes through an intermediate position between the surfaces of the wafer 600; in the illustrated embodiment, the intermediate location is in the epi layer, near the interface between the metal stack 640 and the epi layer 630. By using etching to remove the low-k dielectric material of device wafer 610 at scribe line 603 instead of using a die saw, the incidence of flaking and cracking of device wafer 610 due to the mechanical stress of the die saw may be reduced or eliminated. Also, by extending the etch through at least the interface between low-k dielectric 642 and epi layer 630, problems caused by sawing across the interface are eliminated.

In process block 520, a die saw is used to remove the semiconductor material of epi layer 630 at scribe line 603, as shown in fig. 6D. Because the dielectric material of device wafer 610 at scribe line 603 has been removed in the etching step, the mechanical stress introduced by the die saw will not affect the low-k dielectric material in metal stack 640.

The introduction of this two-step die separation technique adds to the cost of the manufacturing sequence, but an increase in the number of good dies per wafer will offset that additional cost. Additional benefits also derive from a reduction in stress cracking on the sides of the die metallization stack, which is known to lead to reliability failures over time.

Fig. 7 is a block diagram illustrating an embodiment of a BSI or FSI imaging system 700. The illustrated embodiment of imaging system 700 includes a pixel array 705, readout circuitry 710, functional logic 715, and control circuitry 720.

Pixel array 705 is a two-dimensional ("2D") array of back-illuminated imaging sensors or pixels (e.g., pixels P1, P2 … Pn). In one embodiment, each pixel is a complementary metal oxide semiconductor ("CMOS") imaging pixel, and at least one pixel in the array may be one of the BSI pixel embodiments shown in fig. 6. As illustrated, each pixel in the array is arranged in rows (e.g., rows R1-Ry) and columns (e.g., columns C1-Cx) to acquire image data of a person, place, or object, which can then be used to render a 2D image of the person, place, or object.

After each pixel has acquired its image data or image charge, the image data is read out by readout circuitry 710 and transferred to function logic 715. The readout circuitry 710 may include amplification circuitry, analog-to-digital ("ADC") conversion circuitry, or other circuitry. The function logic 715 may simply store the image data or even manipulate the image data by applying post-image effects (e.g., crop, rotate, remove red-eye, adjust brightness, adjust contrast, or other operations). The control circuit 720 is coupled to the pixel array 705 to control the operating characteristics of the pixel array 705.

Fig. 8 is a circuit diagram illustrating an embodiment of a pixel circuit 800 for two four-transistor ("4T") pixels within a BSI imaging array, according to an embodiment of the invention. Pixel circuit 800 is one possible pixel circuit architecture for implementing each pixel within pixel array 705 of fig. 7, but it should be understood that embodiments of the invention are not limited to 4T pixel architectures; rather, those skilled in the art having the benefit of this disclosure will appreciate that the teachings of this disclosure are applicable to 3T designs, 5T designs, and various other pixel architectures. In fig. 8, BSI pixels Pa and Pb are arranged in two rows and one column. The illustrated embodiment of each pixel circuit 800 includes a photodiode PD, a transfer transistor T1, a reset transistor T2, a source follower ("SF") transistor T3, and a select transistor T4. During operation, the transfer transistor T1 receives a transfer signal TX that transfers the charge accumulated in the photodiode PD to the floating diffusion node FD. In one embodiment, the floating diffusion node FD may be coupled to a storage capacitor for temporarily storing image charges. Reset transistor T2 is coupled between power rail VDD and floating diffusion node FD to reset (e.g., discharge FD to a preset voltage or charge FD to a preset voltage) under control of a reset signal RST. Floating diffusion node FD is coupled to control the gate of SF transistor T3. SF transistor T3 is coupled between power rail VDD and select transistor T4. SF transistor T3 operates as a source follower providing a high impedance output from the pixel. Finally, select transistor T4 selectively couples the output of pixel circuit 800 to a readout column line under control of a select signal SEL. In one embodiment, the TX signal, the RST signal, and the SEL signal are generated by control circuitry 720.

The above description of illustrated embodiments of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. These modifications can be made to the invention in light of the above detailed description.

The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (12)

1. A method for separating dies from a wafer having a first side and a second side, the method comprising:

masking the first side of the wafer using a mask that includes openings therein to expose portions of the first side that are substantially aligned with streets of the wafer;

etching from the exposed portion of the first side of the wafer up to an intermediate position between the first side and the second side; and

sawing the remaining portion of the wafer starting from the intermediate position until the second side is reached;

wherein the wafer comprises:

a semiconductor layer having a front side and a back side;

a metal stack formed on the front side of the semiconductor layer; and

a carrier wafer having a free surface and a bonding surface, the bonding surface bonded to the metal stack, wherein the back surface of the semiconductor layer is the first side of the wafer, the free surface of the carrier wafer is the second side of the wafer, and the intermediate position is in the carrier wafer, proximate to the bonding surface.

2. The method of claim 1, wherein the etching is a dry reactive etching.

3. The method of claim 1, wherein the etching is wet etching.

4. The method of claim 1, wherein the semiconductor layer is an epitaxial layer.

5. The method of claim 4, wherein the die is a backside illuminated image sensor.

6. The method of claim 1, wherein sawing comprises using a diamond saw.

7. A method for separating dies from a wafer having a first side and a second side, the method comprising:

masking the first side of the wafer using a mask that includes openings therein to expose portions of the first side that are substantially aligned with streets of the wafer;

etching from the exposed portion of the first side of the wafer up to an intermediate position between the first side and the second side; and

sawing the remaining portion of the wafer starting from the intermediate position until the second side is reached;

wherein the wafer comprises:

a semiconductor layer having a front side and a back side; and

a metal stack formed on the front side of the semiconductor layer, wherein a surface of the metal stack is the first side of the wafer, the back side of the semiconductor layer is the second side of the wafer, and the intermediate position is in the semiconductor layer proximate to the front side of the semiconductor layer.

8. The method of claim 7, wherein the etching is a dry reactive etching.

9. The method of claim 7, wherein the etching is wet etching.

10. The method of claim 7, wherein the semiconductor layer is an epitaxial layer.

11. The method of claim 10, wherein the die is a front-side illuminated image sensor.

12. The method of claim 7, wherein sawing comprises using a diamond saw.