HK1183161B - Pad design for circuit under pad in semiconductor devices - Google Patents

Abstract

The invention relates to pad design for circuit under pad in semiconductor devices. Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via.

Description

Pad design for under-pad circuitry in semiconductor devices

Technical Field

The present invention relates generally to semiconductor devices and particularly, but not exclusively, to pad structures for integrated circuits.

Background

A semiconductor device, such as an integrated circuit ("IC") or chip, is formed from a plurality of bond pads on a surface, and an on-chip interface is provided to electrically couple signals on the semiconductor device to external off-chip pins. As the size of ICs decreases with ever advancing technology, the size and spacing of pads does not decrease at the same rate. As a result, the bond pads and structures associated with the bond pads occupy a greater percentage of the area on the IC.

Fig. 1A is a bottom plan view of a conventional IC100 including bond pads 125. Fig. 1B is a cross-sectional view of a portion of IC100 and one bond pad 125. IC100 includes bond pads 125, semiconductor substrate 130, and metal stack 140. The metal stack 140 includes metal interconnect layers M1, M2, M3, and M4 formed within the dielectric layer 150. The contact 160 couples one metal interconnect layer of the metal stack 140 to another metal interconnect layer. An interlayer dielectric ("ILD") 170 isolates the semiconductor substrate 130 from the metal stack 140.

One disadvantage of the above-described bond pad structure is that a substantial portion of the semiconductor substrate 130 is removed to accommodate the bond pad 125. Therefore, the number of semiconductor substrates 130 used for circuit configuration is reduced. As the percentage of IC area occupied by bond pads increases, a bond pad structure capable of supporting circuitry beneath the bond pads is needed.

Disclosure of Invention

One embodiment of the present invention relates to an image sensor, including: a semiconductor substrate including a photosensitive region surrounded by a peripheral circuit region; a cavity disposed within the peripheral circuitry area of the semiconductor substrate, the cavity extending at least from a first side of the semiconductor substrate up to a second side of the semiconductor substrate; an insulating layer disposed on the first side of the semiconductor substrate and coating sidewalls of the cavity; a conductive layer comprising a bond pad disposed on the insulating layer and on the first side of the semiconductor substrate, wherein the conductive layer extends into the cavity and is connected to a metal stack disposed below the second side of the semiconductor substrate; and a through silicon via ("TSV") pad disposed below the second side of the semiconductor substrate and connected to the metal stack, wherein the TSV pad is positioned to accept a TSV. .

Another embodiment of the present invention relates to a semiconductor device, including: a semiconductor substrate; a cavity disposed within the semiconductor substrate, the cavity extending through a second side of the semiconductor substrate from at least a first side of the semiconductor substrate; an insulating layer disposed on the first side of the semiconductor substrate and coating sidewalls of the cavity; a conductive layer disposed on the insulating layer and disposed within the cavity, wherein the conductive layer comprises a bond pad on the first side of the semiconductor substrate, and wherein the conductive layer is connected to a metal stack at a bottom of the cavity, wherein the bottom of the cavity is located opposite the first side of the semiconductor substrate; and a through silicon via ("TSV") pad disposed below the bottom of the semiconductor substrate and connected to the metal stack, wherein the TSV pad is positioned to accept a TSV.

Another embodiment of the present invention relates to a method for manufacturing a semiconductor device, the method including: providing a semiconductor substrate having circuitry disposed therein; forming a metal stack under a second side of the semiconductor substrate, wherein the metal stack includes a through-silicon via ("TSV") pad, and wherein the TSV pad is positioned to accept a TSV; forming a cavity through the semiconductor substrate; forming an insulating layer on a first side of the semiconductor substrate and on sidewalls of the cavity; removing a portion of the insulating layer from a bottom of the cavity, wherein the bottom of the cavity is located opposite the first side of the semiconductor substrate; and forming a conductive layer on the insulating layer and disposing the conductive layer within the cavity, wherein the conductive layer forms a bond pad over the semiconductor substrate, and wherein the conductive layer is connected to the metal stack at the bottom of the cavity. .

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

Fig. 1A is a bottom plan view of a conventional integrated circuit showing bond pads.

Fig. 1B is a cross-sectional view through line 1B to 1B' of the portion of the conventional integrated circuit in fig. 1A.

Fig. 2A is a plan view illustrating the planar bottom of an integrated circuit showing bond pads according to one embodiment of the invention.

Fig. 2B is a cross-sectional view through line 2B to 2B' of the integrated circuit of fig. 2A, in accordance with one embodiment of the present invention.

Fig. 2C is a cross-sectional view of a portion through lines 2B-2B' illustrating the integrated circuit of fig. 2A in more detail, according to one embodiment of the invention.

Fig. 3 is a flow chart illustrating a process of manufacturing a semiconductor according to one embodiment of the present invention.

FIG. 4 is a functional block diagram illustrating an imaging sensor according to one embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating a sample pixel circuit for two image sensor pixels within an image sensor, according to one embodiment of the invention.

Detailed Description

Embodiments of a semiconductor device and methods of manufacturing a semiconductor device are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Although directional terms such as top, bottom, lower and upper are used with reference to the orientation of the figures being described, this should not be construed as limiting the orientation of the embodiments in any way.

As used herein, the term "substrate" refers to any of a variety of substrates formed using semiconductor materials, for example, semiconductor materials based on silicon, silicon germanium, gallium arsenide, and/or the like. The substrate layer may comprise such a substrate and one or more structures resulting from operations that have been performed on the substrate, for example, such operations that form regions, junctions, and/or other structures in the substrate. By way of example and not limitation, such structures may include one or more doped and/or undoped semiconductor regions, epitaxial layers of silicon, and other semiconductor structures formed on the substrate.

Fig. 2A is a plan view illustrating a planar bottom portion of an integrated circuit and a plurality of bond pads, in accordance with one embodiment of the present invention. In fig. 2A, a backside illuminated ("BSI") image sensor 200 is illustrated as one example of an integrated circuit ("IC"). In BSI image sensor 200, a photosensitive region disposed within a substrate of an image sensor pixel array is exposed to incident light from the backside of the substrate. In other embodiments of the present invention, the IC may be a front side illumination ("FSI") image sensor or some other type of electronic circuit.

In the illustrated embodiment, BSI image sensor 200 includes a photosensitive region 210 surrounded by a peripheral circuit region 220. Bond pads (e.g., bond pad 225) and cavities (e.g., cavity 226) may be located within peripheral circuitry area 220 such that they do not block incident light from photosensitive area 210. Photosensitive region 210 may contain an array of image sensor pixels. In the illustrated embodiment, the cavity 226 is located on the outer periphery of the peripheral circuitry region 220 to increase the available semiconductor substrate area. In other embodiments, the cavity 226 is closer to the photosensitive region 210 than the bonding pad 225. Bond pads 225 make signals internal to BSI image sensor 200 available externally through wire bond connections.

Fig. 2B is a cross-sectional view of BSI image sensor 200 taken along line 2B-2B' in fig. 2A. The illustrated embodiment of BSI image sensor 200 includes bond pads 225, cavities 226, semiconductor substrate 230, photosensitive elements 231, peripheral circuitry 232, and handle substrate 260. The bond pad 225 and the cavity 226 may be formed on the backside of the semiconductor substrate 230. The semiconductor substrate 230 may be P-type and may be referred to as an epitaxial layer. The photosensitive element 231 formed on the front side of the semiconductor substrate 230 represents where an array of image sensor pixels can be disposed. The photosensor 231 can include a photodiode and a pass gate. Peripheral circuitry 232, also illustrated as being formed on the front side of the semiconductor substrate 230, may include control circuitry, functional logic circuitry, and readout circuitry associated with the photosensitive element 231. Peripheral circuitry 232 may reside solely within peripheral circuitry region 220 or within peripheral circuitry region 220 and photosensitive region 210. In one embodiment, the photosensor 231 is N-type. However, it will be appreciated by those skilled in the art that in other embodiments, the doping polarity may be different. For example, the photosensitive element 231 can be P-type, while the semiconductor substrate 230 can be N-type.

Fig. 2C is a cross-sectional view through a portion of line 2B-2B', illustrating BSI image sensor 200 in more detail than fig. 2B. Fig. 2C illustrates P + layer 233, antireflective ("AR") layer 234, insulator 270, conductive layer 275, liner insulator 290, cavity sidewall 295, and interlayer dielectric ("ILD") layer 240. A P + layer 233 is disposed on the back side of the semiconductor substrate 230, and an anti-reflective ("AR") layer 234 is disposed on the P + dopant layer 233. In the illustrated embodiment, an insulator 270 is disposed on the AR layer 234, and the insulator 270 also coats the cavity sidewalls 295. In one embodiment, the conductive layer 275 is disposed on the insulator 270 and the conductive layer 275 also extends into the cavity 226. Bond pad 225 is a portion of conductive layer 275 disposed on semiconductor substrate 230. The pad insulator 290 may be disposed on portions of the conductive layer 275, but will expose at least a portion of the bond pad 225. The insulator 270 coating the cavity sidewalls 295 may electrically isolate the portion of the conductive layer 275 disposed within the cavity from the semiconductor substrate 230.

In the illustrated embodiment, the cavity 226 is disposed within a semiconductor substrate 230 within the peripheral circuitry area 220. The cavity 226 may be etched in the substrate 230 or formed using a different process. The cavity 226 extends at least from the backside of the semiconductor substrate 230 to the front side of the semiconductor substrate 230. The cavity 226 may also extend through the ILD layer 240. In the illustrated embodiment, ILD layer 240 is disposed between semiconductor substrate 230 and metal stack 250. Portions of the conductive layer 275 (the portions disposed at the bottom of the cavity 226) are connected to the metal stack 250. This connection forms a conductive circuit between the bond pad 225 and the metal stack 250.

Fig. 2C illustrates that metal stack 250 disposed on the front side of substrate 230 includes metal interconnect layers M1, M2, M3, and M4. In some embodiments, the metal stack 250 may contain any number of metal interconnect layers. The metal interconnect layers may be formed between interlayer dielectrics and may be connected together by contacts. The photosensitive element 231 and the peripheral circuitry 232 can be electrically connected to the metal stack 250.

A metal interconnect layer M4 disposed on the front side of the substrate 230 is illustrated as being disposed above the handle substrate 260 and contacting the handle substrate 260. TSV pad 285 may be included in M4 or another metal interconnect layer. TSV pads 285 may be silicon and they are positioned to accept TSVs. TSV pads 285 may be positioned to distribute off-chip signals or receive off-chip signals. In one embodiment, TSV285 pad is positioned to maximize the availability of metal interconnect layers (e.g., M1, M2, and M3) directly below bond pad 225 in order to allow the metal interconnect layers to be directly connected to circuitry (e.g., peripheral circuitry 232) directly below bond pad 225. In the illustrated embodiment, TSV280 travels through handle substrate 260 and connects with TSV pad 285. In some embodiments, all or a portion of handle substrate 260 is removed from BSI image sensor 200. The TSV280 may travel through a substrate other than the handle substrate 260.

TSV pads 285 allow access to metal stack 250 and any circuitry connected to metal stack 250 (e.g., photosensitive elements 231 and peripheral circuitry 232) from the front side of BSI image sensor 200 through vias (e.g., TSVs 280), and bonding pads 225 allow access to metal stack 250 from the back side by wire bonding. Furthermore, having the cavities 226 disposed on the outer perimeter of the peripheral circuitry region 220 allows the semiconductor substrate to remain continuous over a larger area. Also, since the bond pad 225 is connected to the metal stack 250 by the portion of the conductive layer 275 disposed within the cavity, a circuit under pad ("cpu") is possible. In contrast, the bond pads 125 in the conventional IC100 require that a larger portion of the semiconductor substrate 130 be removed and the cpu is not possible. Thus, the illustrated embodiment allows for increased semiconductor substrate to retain circuitry while still allowing wire bond access (through bond pad 225) and TSV access (through the location of TSV pad 285). Although the illustrated embodiment is a BSI image sensor 200, the present invention may be applied to other ICs.

Fig. 3 is a flow chart illustrating a process of manufacturing a semiconductor according to one embodiment of the present invention. Process 300 is one example of how BSI image sensor 200 is manufactured. The order in which some or all of the process blocks appear in each process should not be construed as a limitation. Rather, those skilled in the art, having the benefit of the present disclosure, will appreciate that some of the process blocks may be performed in a variety of orders not illustrated, or even in parallel.

In process block 305, a semiconductor substrate (e.g., semiconductor substrate 230) is provided in which circuitry (e.g., peripheral circuitry 232) is disposed. In process block 310, a metal stack (e.g., metal stack 250) including a TSV pad (e.g., TSV pad 285) is formed on a second side of the semiconductor substrate. At process block 315, a cavity (e.g., cavity 226) is formed through the semiconductor substrate. The cavity may extend through the semiconductor substrate through the other layers until the cavity reaches the metal stack. The cavities may be formed using known etch processes, such as dry etching. At process block 320, an insulating layer (e.g., insulator 270) is formed on a first side of a semiconductor substrate. An insulating layer may also be formed on the sidewalls of the cavity and at the bottom of the cavity. The bottom of the cavity, where the cavity is connected to the metal stack, may be opposite the first side of the semiconductor substrate. At process block 325, the portion of the insulating layer at the bottom of the cavity is removed. The insulating layer at the bottom of the cavity is removed so that the conductive layer can be connected with the metal stack. At process block 330, a conductive layer (which includes a bond pad) is formed over the insulating layer and also disposed within the cavity. The conductive layer is disposed such that the conductive layer is connected to the metal stack.

Fig. 4 is a functional block diagram illustrating an imaging sensor 400 according to one embodiment of the invention. Imaging sensor 400 is one possible implementation of an IC implemented using the techniques described herein. The illustrated embodiment of image sensor 400 includes a pixel array 405, readout circuitry 410, functional logic 415, and control circuitry 420. The pixel array 405 is a two-dimensional ("2D") array of image sensors or pixels (e.g., pixels P1, P2 … …, Pn). The pixel array 405 can be disposed within the photosensitive element 231 within the photosensitive region 210. The readout circuitry 410, functional logic 415, and/or control circuitry 420 may be disposed within the peripheral circuitry 232. In one embodiment, each pixel is a complementary metal oxide semiconductor ("CMOS") imaging pixel. As illustrated, each pixel is arranged in rows (e.g., rows R1-Ry) and columns (e.g., columns C1-Cx) to acquire image data of a person, location, or object, which can then be used to render a 2D image of the person, location, or object. The structures and processes of the present invention may be used within an imaging sensor 400.

After each pixel has acquired its image data or image charge, the image data is read out by readout circuitry 410 and passed to functional logic 415. The readout circuitry 410 may include amplification circuitry, analog-to-digital ("ADC") conversion circuitry, or other circuitry. Function logic 415 may simply store the image data or even manipulate the image data by applying post image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise). In one embodiment, readout circuitry 410 may readout a row of image data at the same time as readout of multiple column lines (illustrated) or may readout the image data using a variety of other techniques (not illustrated), such as a serial readout or readout of all pixels in parallel all at once. Control circuitry 420 is coupled to the pixel array 405 to control operating characteristics of the pixel array 405. For example, the control circuit 420 may generate a shutter signal for controlling image acquisition.

FIG. 5 is a circuit diagram illustrating a sample pixel circuit 500 for two four-transistor ("4T") pixels within an imaging array, according to one embodiment of the invention. Pixel circuit 500 is one possible pixel circuit architecture for implementing each pixel within pixel array 405 of fig. 4. However, it should be understood that embodiments of the invention are not limited to 4T pixel architectures; rather, those skilled in the art, having the benefit of this disclosure, will appreciate that the teachings of this disclosure are applicable to 3T designs, 5T designs, and various other pixel architectures. In some embodiments, some of the circuitry illustrated in pixel circuitry 500 may be disposed within peripheral circuitry 232.

In fig. 5, pixels Pa and Pb are arranged in two rows and one column. The illustrated embodiment of each pixel circuit 500 includes a photodiode PD, a transfer transistor T1, a reset transistor T2, a source follower ("SF") transistor T3, a select transistor T4, and a storage capacitor C1. During operation, transfer transistor T1 receives a transfer signal TX, which transfers charge accumulated within photodiode PD to floating diffusion node FD. In one embodiment, floating diffusion node FD may be coupled to a storage capacitor (not shown) to temporarily store image charge.

A reset transistor T2 is coupled between power rail VDD and floating diffusion node FD to reset the pixel (e.g., discharge or charge FD and PD to a preset voltage) under control of a reset signal RST. Floating diffusion node FD is coupled to control the gate of SF transistor T3. SF transistor T3 is coupled between power rail VDD and select transistor T4. SF transistor T3 operates as a source follower providing a high impedance connection to floating diffusion FD. Finally, select transistor T4 selectively couples the output of pixel circuitry 500 to the readout column line under control of a select signal SEL. In one embodiment, the TX signal, the RST reset signal, and the SEL signal are generated by control circuitry 420.

The above description of illustrated embodiments of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (18)

1. An image sensor, comprising:

a semiconductor substrate including a photosensitive region surrounded by a peripheral circuit region;

a cavity disposed within the peripheral circuitry area of the semiconductor substrate, the cavity extending at least from a first side of the semiconductor substrate up to a second side of the semiconductor substrate;

an insulating layer disposed on the first side of the semiconductor substrate and coating sidewalls of the cavity;

a conductive layer comprising a bond pad disposed on the insulating layer and on the first side of the semiconductor substrate, wherein the conductive layer extends into the cavity and is connected to a metal stack disposed below the second side of the semiconductor substrate; and

a through silicon via "TSV" pad disposed below the second side of the semiconductor substrate and connected to the metal stack, wherein the TSV pad is positioned to accept a TSV.

2. The image sensor of claim 1, further comprising:

a photosensitive element disposed within the photosensitive region of the semiconductor substrate; and

readout circuitry disposed beneath the bond pads and within the peripheral circuitry area of the semiconductor substrate, wherein the readout circuitry is coupled to readout image data from the photosensitive elements.

3. The image sensor of claim 1, further comprising:

a handle substrate disposed below the TSV pad; and

a TSV that travels through the handle substrate and connects with the TSV liner.

4. The image sensor of claim 1, further comprising:

an interlayer dielectric disposed between the metal stack and the semiconductor substrate, wherein the cavity extends through the interlayer dielectric.

5. The image sensor of claim 1, further comprising:

an anti-reflective layer disposed over a photosensitive element disposed within the photosensitive region of the semiconductor substrate.

6. The image sensor of claim 1, wherein the cavity is located on an outer periphery of the peripheral circuit region of the semiconductor substrate.

7. The image sensor of claim 1, wherein the metal stack comprises a plurality of metal interconnect layers, and wherein at least a portion of the TSV pad is disposed directly below at least one metal interconnect layer within the metal stack disposed directly below circuitry and connected to the circuitry disposed directly below the bonding pad.

8. The image sensor of claim 1, wherein the entire bond pad is disposed over and on the peripheral circuitry area.

9. The image sensor of claim 1, wherein the metal stack comprises the TSV pad.

10. The image sensor of claim 1, wherein the TSV pads are positioned for distributing or receiving off-chip signals.

11. A semiconductor device, comprising:

a semiconductor substrate;

a cavity disposed within the semiconductor substrate, the cavity extending through a second side of the semiconductor substrate from at least a first side of the semiconductor substrate;

an insulating layer disposed on the first side of the semiconductor substrate and coating sidewalls of the cavity;

a conductive layer disposed on the insulating layer and disposed within the cavity, wherein the conductive layer comprises a bond pad on the first side of the semiconductor substrate, and wherein the conductive layer is connected to a metal stack at a bottom of the cavity, wherein the bottom of the cavity is located opposite the first side of the semiconductor substrate;

a through silicon via "TSV" pad disposed below the bottom of the semiconductor substrate and connected to the metal stack, wherein the TSV pad is positioned to accept a TSV;

a handle substrate disposed below the TSV pad; and

a TSV that travels through the handle substrate and connects with the TSV liner.

12. The semiconductor device of claim 11, wherein the semiconductor device comprises an image sensor, the image sensor further comprising:

circuitry disposed within the semiconductor substrate, wherein the circuitry is disposed below the bond pad.

13. The semiconductor device of claim 12, wherein the cavity is located on an outer periphery of the semiconductor substrate to maximize an area of a continuous semiconductor substrate.

14. The semiconductor device of claim 12, further comprising:

an interlayer dielectric disposed between the metal stack and the semiconductor substrate, wherein the cavity extends through the interlayer dielectric.

15. The semiconductor device of claim 12, wherein the metal stack comprises a plurality of metal interconnect layers, and wherein a portion of the TSV pad is disposed directly below at least one metal interconnect layer within the metal stack disposed directly below circuitry and connected to the circuitry disposed directly below the bonding pad.

16. The semiconductor device of claim 12, wherein the TSV connects the TSV pad to an off-chip signal.

17. A method for manufacturing a semiconductor device, the method comprising:

providing a semiconductor substrate having circuitry disposed therein;

forming a metal stack below a second side of the semiconductor substrate, wherein the metal stack comprises a through silicon via "TSV" pad, and wherein the TSV pad is positioned to accept a TSV;

forming a cavity through the semiconductor substrate;

forming an insulating layer on a first side of the semiconductor substrate and on sidewalls of the cavity;

removing a portion of the insulating layer from a bottom of the cavity, wherein the bottom of the cavity is located opposite the first side of the semiconductor substrate;

forming a conductive layer on the insulating layer and disposing the conductive layer within the cavity, wherein the conductive layer forms a bond pad over the semiconductor substrate, and wherein the conductive layer is connected to the metal stack at the bottom of the cavity;

forming a handle substrate below the TSV pad; and

forming a TSV that travels through the handle substrate and connects with the TSV pad.

18. The method of claim 17, further comprising:

forming an interlayer dielectric between the metal stack and the semiconductor substrate, wherein etching away the portion of the insulating layer at the bottom of the cavity comprises etching away a portion of the interlayer dielectric between the metal stack and the semiconductor substrate.