HK1172735B - Seal ring support for backside illuminated image sensor - Google Patents

Abstract

A backside illuminated imaging sensor with a real ring support includes an epitaxial layer having an imaging array formed in a front side of the epitaxial layer. A mental stack is coupled to the front side of the epitaxial layer, wherein the metal stack includes a seal ring formed in an edge region of the imaging sensor. An opening is included that extends from the back side of the epitaxial layer to a metal pad of the seal ring to expose the metal pad. The seal ring support is disposed on the metal pad and within the opening to structurally support the seal ring.

Description

Seal ring support for backside illuminated image sensor

Technical Field

The present disclosure relates generally to imaging sensors, and particularly, but not exclusively, to backside illumination ("BSI") imaging sensors.

Background

Semiconductor chips or dies (e.g., image sensor chips) are fabricated on a single semiconductor wafer along with hundreds and in some cases thousands of copies of the same die. The dicing to separate the semiconductor wafer into individual dies may be performed with a die saw (e.g., a diamond saw). The dicing is done along areas of non-functional semiconductor material separating each die, called dicing lines. The use of diamond saws introduces mechanical stress to the semiconductor wafer and can lead to cracking at the die edge and compromise the integrity and reliability of the integrated circuit. One structure used to make the die less susceptible to mechanical stress from the die saw is a seal ring. A seal ring in the die is formed in or on an outer region of one or more dielectric layers of a semiconductor substrate to protect the integrated circuit from contaminants (e.g., sodium) and to make the die less susceptible to mechanical stress caused by a die saw.

Today, many semiconductor imaging sensors are of the front side illuminated type. That is, it includes an imaging array fabricated on the front side of the semiconductor wafer, where light is received at the imaging array from the same front side. However, front-lit imaging sensors have a number of disadvantages, one of which is a limited fill factor.

Back-illuminated imaging sensors are an alternative to front-illuminated imaging sensors, which address the fill factor problem associated with front-illumination. Backside illuminated imaging sensors include an imaging array fabricated on the front surface of a semiconductor wafer, but receive light through the back surface of the wafer. Color filters and microlenses may be included on the back surface of the wafer to improve the sensitivity of the back side illumination sensor. However, to detect light from the backside, the wafer must be extremely thin. The thickness of the wafer may also be reduced in order to improve sensitivity. However, the thinner the wafer, the more susceptible it is to physical damage during various stages of fabrication. That is, as the semiconductor wafer gets thinner, the semiconductor wafer becomes weaker, making the backside illuminated imaging sensor wafer even more susceptible to mechanical stress from the die saw.

Disclosure of Invention

In one aspect, there is provided a back-illuminated imaging sensor, comprising: an epitaxial layer having an imaging array formed in a front side of the epitaxial layer, wherein the imaging array is adapted to receive light from a back side of the epitaxial layer; a metal stack coupled to the front side of the epitaxial layer, wherein the metal stack includes a seal ring formed in an edge region of the imaging sensor; an opening extending from the backside of the epitaxial layer to a metal pad of the seal ring to expose the metal pad; and a seal ring support disposed on the metal pad and within the opening to structurally support the seal ring.

In another aspect, there is provided a back-illuminated imaging sensor, comprising: an epitaxial layer having an imaging array formed in a front side of the epitaxial layer, wherein the imaging array is adapted to receive light from a back side of the epitaxial layer; a metal stack coupled to the front side of the epitaxial layer, wherein the metal stack includes a seal ring formed in an edge region of the imaging sensor; an opening extending from the backside of the epitaxial layer to a metal pad of the seal ring to expose the metal pad; and means for structurally supporting the seal ring disposed on the metal pad and disposed in the opening.

In another aspect, a method of manufacturing a backside illuminated imaging sensor is provided, the method comprising: providing a back-illuminated imaging sensor, the imaging sensor comprising: an epitaxial layer having an imaging array formed in a front side of the epitaxial layer, wherein the imaging array is adapted to receive light from a back side of the epitaxial layer; a metal stack coupled to the front side of the epitaxial layer, wherein the metal stack includes a seal ring formed in an edge region of the imaging sensor; etching an opening extending from the backside of the epitaxial layer to a metal pad of the seal ring to expose the metal pad; depositing a material on the back side of the epitaxial layer and within the opening; and etching the material to form a seal ring support over the metal pad and within the opening to structurally support the seal ring.

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

Fig. 1A is a diagram illustrating a semiconductor wafer with integrated circuit dies shown.

FIG. 1B is a diagram illustrating in more detail the integrated circuit die shown in FIG. 1A.

Fig. 2A is a plan or bottom plan view of a backside illuminated image sensor with a seal ring support according to an embodiment of the present invention.

Fig. 2B is a plan or bottom plan view of a backside illuminated image sensor with a seal ring support according to another embodiment of the present invention.

FIG. 3 is a cross-sectional view of a back-illuminated image sensor with a seal ring support taken along section line 3-3' of FIG. 2A, in accordance with an embodiment of the present invention.

FIG. 4 is a flow chart illustrating a method of fabricating a backside illuminated imaging sensor with a seal ring support according to an embodiment of the present invention.

Figure 5A is a cross-sectional view illustrating an embodiment of a partially fabricated back side illuminated image sensor wafer.

FIG. 5B is a cross-sectional view illustrating an embodiment of a partially fabricated backside illuminated image sensor wafer formed with seal ring support openings.

FIG. 5C is a cross-sectional view illustrating an embodiment of a partially fabricated backside illuminated image sensor wafer after deposition of a seal ring support material lining the seal ring support openings.

Figure 5D is a cross-sectional view illustrating an embodiment of a partially fabricated back side illuminated image sensor wafer after deposition of a passivation material.

Fig. 6 is a block diagram illustrating an embodiment of a BSI image sensor die.

Fig. 7 is a circuit diagram illustrating pixel circuitry for two four-transistor ("4T") pixels within an embodiment of a BSI imaging array.

Detailed Description

Embodiments of backside illuminated sensors with seal ring support structures are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrase "in one embodiment" appearing in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Directional terminology (e.g., "top," "bottom," "above," "below") is used with reference to the orientation of the figures being described.

Fig. 1A is a diagram illustrating a semiconductor wafer 100, the semiconductor wafer 100 including a number of dies 111-119. The semiconductor wafer 100 may comprise silicon or gallium arsenide or other semiconductor materials. Fig. 1B is a diagram illustrating semiconductor wafer 100 and dies 111-119 in more detail. Dicing lines 150 and 151 separate adjacent dies. The score line region 152 shows the area where the score lines 150 and 151 intersect. The die areas near the scribe line regions 152 are typically more susceptible to mechanical stress caused by the die saw because the die saw traverses the semiconductor wafer 100 twice in these regions, once along the scribe lines 150 and another time along the scribe lines 151. This is in contrast to regions 153 and 154, where the die saw typically passes only once.

FIG. 2A is a plan or bottom plan view of a backside illuminated image sensor 200A with a seal ring support 260A according to an embodiment of the invention. A seal ring support 260A is formed on the back side of the seal ring, which in turn is formed in or on the outer region 205 of the image sensor 200A and surrounds the integrated circuit region 220. In one embodiment, outer region 205 comprises only non-functional semiconductor material. That is, in one example, external region 205 may not include any integrated circuitry, while integrated circuitry region 220 may include one or more pixel arrays, readout circuitry, control circuitry, and other functional logic. Also, the outer region 205 may extend from the integrated circuit region 220 all the way to the outer edge 207 of the image sensor 200A.

The seal ring may protect the integrated circuit region 220 from contaminants, such as sodium, and may make the metal interconnects of the BSI image sensor 200A and the dielectric layers of the semiconductor substrate less susceptible to mechanical stress caused by a die saw or other processes used to separate multiple dies formed on a semiconductor wafer into individual dies. In fig. 2A, seal ring support 260A has a width w and is disposed within outer region 205 between integrated circuit region 220 and outer edge 207 of image sensor 200A. In one embodiment, seal ring support 260A has a width such that seal ring support 260A extends to outer edge 207. The seal ring support 260A may comprise an oxide, nitride, or metal such as aluminum or tungsten, or an alloy of other metals. The seal ring may have the same width as the width w of the seal ring support 260A, or the seal ring may have a width greater or less than w.

Fig. 2B is a plan or bottom plan view of a BSI image sensor 200B having a seal ring support 260B in accordance with another embodiment of the invention. The seal ring support 260B has two widthsw₁And w₂. In corner regions 225 of BSI image sensor 200B around the corners, seal ring support 260B has a width w₁Said width w₁Greater than a width w of the seal-ring support 260B along the side region 230 of the BSI image sensor 200B₂. In the illustrated embodiment of FIG. 2B, the greater width w of the seal ring support 260B in the corner region 225₂Greater support is provided to the seal ring at the scribe line intersection (see back fig. 1B where the corners of the die 112, 113, 115 and 116 in the region of the scribe line intersection, for example, are more susceptible to mechanical stress due to the die saw than at the scribe line regions 153 and 154). The seal ring may have the same width as the seal ring support 260B, or the seal ring may have a width greater or less than w₁And/or w₂Is measured.

Fig. 3 is a cross-sectional view of a BSI image sensor 300 having a seal ring support 360, taken along section line 3-3' of fig. 2A, in accordance with an embodiment of the invention. BSI image sensor 300 includes a device layer 310 and a carrier substrate 320. Device layer 310 includes an epitaxial (epi) layer 330 and a metal stack 340. Components such as the photosensitive regions, source and drain regions of transistors are included in imaging array 331. Imaging array 331 and peripheral circuitry 332 are disposed in epitaxial (epi) layer 330. A metal stack 340 is formed on the front side of epitaxial layer 330.

The dielectric layer 341 separates adjacent metal interconnect layers of the metal stack 340 and separates the metal interconnect layers from the epitaxial layer 330 and the carrier substrate 320. In the present embodiment, the metal stack 340 includes three metal interconnect layers. In other embodiments of the present invention, the metal stack 340 may have more or fewer metal layers. In some embodiments, the metal interconnect layers M1, M2, and M3 may comprise tungsten, aluminum, copper, aluminum copper alloys, or other alloys.

Imaging array 331 is formed in the front side of epitaxial layer 330 and is configured to receive light from the back side of epitaxial layer 330, which can also be the back side of device layer 310. Imaging array 331 can include an array of imaging pixels arranged in a plurality of rows and columns. Peripheral circuitry 332 may include readout circuitry, functional logic, and control circuitry. A color filter (not shown) is optionally included in BSI image sensor 300 to implement a color imaging sensor, and a microlens 333 is optionally included in BSI image sensor 300 to focus light onto an array of imaging pixels in imaging array 331. Both the optional color filter and the microlens 333 can be disposed on the back side of the device layer 310.

A carrier substrate 320 is coupled or bonded to the front side of the device layer 310 to provide structural support for the BSI image sensor 300. Note that the illustrated embodiment of BSI image sensor 300 is not drawn to scale. That is, the carrier substrate 320 may have a thickness that is much greater than the thickness of the device layer 310. For example, the carrier substrate 320 may be approximately 100 times thicker than the device layer 310. In some embodiments, the carrier substrate 320 is fabricated separately and then bonded to the front side of the device layer 310 by methods such as press bonding.

Seal ring 343 is formed in the outer edge region of dielectric layer 341 surrounding an integrated circuit region including peripheral circuitry 332 and imaging array 331. The metallization layer of seal ring 343 is connected from lower metal M1 to upper metal M3 through vias. Openings 350 are formed by etching the backside of epitaxial layer 330 through the entire depth of epitaxial layer 330 and through dielectric layer 341 to expose metal pads 342 of metal interconnects M1. Opening 350 may have a width 311 of 3 μm to 50 μm and a depth of 0.5 μm to 5 μm. Seal ring support 360 may comprise an oxide, nitride, or alloy of a metal such as aluminum or tungsten or other metal, and have a thickness of tens or hundreds of nanometers. In one embodiment, seal ring support 360 comprises metal, wherein seal ring support 360 and seal ring 343 act and function as a signal bus for imaging sensor 300. For example, seal ring support 360 and seal ring 343 may be used as a ground bus or as a power bus for imaging sensor 300. In the present embodiment, the seal ring 343 (like the metal interconnect layer) includes three metal layers, and in other embodiments, the seal ring 343 may include a smaller number of metal layers than the number of metal interconnect layers.

As shown in fig. 3, the seal ring support 360 includes a first horizontal portion 351, a vertical portion 353, and a second horizontal portion 355. The support width of the seal ring support 360 may be adjusted by adjusting the width 311 of the opening 311 and/or by more or less masking the second horizontal portion 355 on the backside of the epitaxial layer 330. For example, the seal ring support 360 may be formed by masking the support material such that the seal ring support 360 extends on the back side of the epitaxial layers 330 to the outer edge 307. Passivation layer 370 provides planarization on the back side of device layer 310. The microlens 333 is formed on the rear surface of the passivation layer 370.

Fig. 4 is a flow chart illustrating an embodiment of a process 400 for fabricating a BST image sensor wafer 500 with a seal ring support 560 (see fig. 5A-5D). The order in which some or all of the process blocks appear in each process should not be construed as limiting. Rather, as one of ordinary skill in the art having the benefit of the present disclosure will appreciate, some of the process blocks may be performed in a variety of orders not illustrated.

In process block 405, the carrier wafer 520 is wafer bonded to the front side of the device wafer 510 to provide structural support for the imaging sensor before thinning the back side of the device wafer 510, as seen in fig. 5A. In one embodiment, the carrier wafer 520 is bonded to the device wafer 510 by a method such as press bonding. The back side of device wafer 510 or epi layer 530 is then thinned in process block 407. Epitaxial layer 530 may be thinned to a thickness in the range of about 1 μm to about 10 μm.

In process block 410, any miscellaneous backside processing may be performed. For example, any backside implants or anneals may be performed in process block 410. In process block 415, seal ring support openings 550 are etched down through the backside of epitaxial layer 530 into dielectric layer 541 to expose metal pads 542 of metal interconnect layer M1, as seen in fig. 5B. The seal ring support opening 550 may have a width of 3 μm to 50 μm and a depth of 0.5 μm to 5 μm. In process step 420, a seal ring support material is deposited onto the backside of epitaxial layer 530 and etched away in areas where the seal ring support material is not needed. These regions include at least the region of the back side of the device wafer 510 directly over the imaging array 531 of each BSI image sensor die 501 and 502. In some embodiments, the seal ring support 560 in the region of the back side of the device wafer 510 directly above the peripheral circuitry 532 may be etched away. Seal ring support 560 may comprise an oxide, nitride, or metal such as aluminum or tungsten, or an alloy of other metals. The seal ring support 560 may have a thickness of tens to hundreds of nanometers.

In process block 425, a passivation material 580 is deposited on the back side of the device wafer 510 to provide planarization, as seen in fig. 5D. In process block 435, fabrication of BSI image sensor dies 501 and 502 is completed with steps such as forming microlenses 533 and sawing the dies to separate the dies from the semiconductor wafer along dicing lines 503.

FIG. 6 is a block diagram illustrating a back-illuminated imaging sensor 600 according to an embodiment of the invention. The illustrated embodiment of imaging sensor 600 includes an imaging array 605, readout circuitry 610, functional logic 615, and control circuitry 620.

Imaging array 605 is a two-dimensional ("2D") array of back-illuminated imaging sensors or pixels (e.g., pixels P1, P2,.., Pn). In one embodiment, each pixel is an active pixel sensor ("APS"), such as a complementary metal oxide semiconductor ("CMOS") imaging pixel. As illustrated, each pixel is arranged into rows (e.g., rows R1-Ry) and columns (e.g., columns C1-Cx) to acquire image data of a person, place, or object, which can then be used to render a 2D image of the person, place, or object.

After each pixel has acquired its image data or image charge, the image data is read out by readout circuitry 610 and transferred to function logic 615. The readout circuit 610 may include an amplification circuit, an analog-to-digital ("ADC") conversion circuit, or other circuits. Function logic 615 may simply store the image data or even manipulate the image data by applying post-image effects (e.g., crop, rotate, remove red-eye, adjust brightness, adjust contrast, or other operations). Control circuitry 620 is coupled to pixel array 605 to control the operating characteristics of pixel array 605.

Fig. 7 is a circuit diagram illustrating an embodiment of a pixel circuit 700 for two four-transistor ("4T") pixels within a BSI imaging array, in accordance with an embodiment of the invention. Pixel circuit 700 is one possible pixel circuit structure for implementing each pixel within pixel array 605 of fig. 6, but it should be understood that embodiments of the invention are not limited to 4T pixel structures; rather, those skilled in the art, with the benefit of the present disclosure, will appreciate that the teachings of the present disclosure also apply to 3T designs, 5T designs, and various other pixel structures. In fig. 7, BSI pixels Pa and Pb are arranged in two rows and one column. The illustrated embodiment of each pixel circuit 700 includes a photodiode PD, a transfer transistor T1, a reset transistor T2, a source follower ("SF") transistor T3, and a select transistor T4. During operation, transfer transistor T1 receives a transfer signal TX that transfers charge accumulated in photodiode PD to floating diffusion node FD. In one embodiment, the floating diffusion node FD may be coupled to a storage capacitor for temporarily storing image charge. A reset transistor T2 is coupled between a power rail VDD and the floating diffusion node FD to reset (e.g., discharge or charge the FD to a preset voltage) under control of a reset signal RST. Floating diffusion node FD is coupled to control the gate of SF transistor T3. SF transistor T3 is coupled between power rail VDD and select transistor T4. The SF transistor T3 operates as a source follower providing high impedance output from the pixel. Finally, select transistor T4 selectively couples the output of pixel circuit 800 to a readout column line under control of a select signal SEL. In one embodiment, the TX signal, the RST signal, and the SEL signal are generated by control circuitry 520.

The above description of illustrated embodiments of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (14)

1. A backside illuminated imaging sensor, comprising:

an epitaxial layer having an imaging array formed in a front side of the epitaxial layer, wherein the imaging array is adapted to receive light from a back side of the epitaxial layer;

a metal stack coupled to the front side of the epitaxial layer, wherein the metal stack includes a seal ring formed in an edge region of the imaging sensor;

an opening extending from the backside of the epitaxial layer to a metal pad of the seal ring to expose the metal pad; and

a seal ring support disposed on the metal pad and within the opening to structurally support the seal ring,

wherein the seal ring support has a first width in a corner region of the backside illuminated imaging sensor, and wherein the seal ring support has a second width in a side region of the backside illuminated imaging sensor that is different from the first width.

2. The backside illuminated imaging sensor of claim 1, wherein the imaging array is disposed in an integrated circuit region of the backside illuminated imaging sensor, and wherein the seal ring surrounds the integrated circuit region.

3. The backside illuminated imaging sensor of claim 1, wherein at least one of the first width and the second width is greater than a width of the opening.

4. The backside illuminated imaging sensor of claim 1, wherein the first width is greater than the second width.

5. The backside illuminated imaging sensor of claim 1, wherein the seal ring support comprises:

a first horizontal portion disposed on the metal pad;

a second horizontal portion disposed on the back side of the epitaxial layer; and

a vertical portion disposed between the first horizontal portion and the second horizontal portion.

6. The backside illuminated imaging sensor of claim 5, wherein the second horizontal portion extends to an outside edge of the backside illuminated imaging sensor.

7. The backside illuminated imaging sensor of claim 1, wherein the metal stack includes a metal interconnect layer and a dielectric layer disposed between the front side of the epitaxial layer and the metal interconnect layer, wherein the metal pads are included in the metal interconnect layer.

8. The backside illuminated imaging sensor of claim 1, wherein the seal ring support is a metal, nitride, or oxide.

9. The backside illuminated imaging sensor of claim 1, wherein the imaging array is a Complementary Metal Oxide Semiconductor (CMOS) imaging array.

10. A method of manufacturing a backside illuminated imaging sensor, the method comprising:

providing a back-illuminated imaging sensor, the imaging sensor comprising:

an epitaxial layer having an imaging array formed in a front side of the epitaxial layer, wherein the imaging array is adapted to receive light from a back side of the epitaxial layer;

a metal stack coupled to the front side of the epitaxial layer, wherein the metal stack includes a seal ring formed in an edge region of the imaging sensor;

etching an opening extending from the backside of the epitaxial layer to a metal pad of the seal ring to expose the metal pad;

depositing a material on the back side of the epitaxial layer and within the opening; and

etching the material to form a seal ring support over the metal pad and within the opening to structurally support the seal ring,

wherein the seal ring support has a first width in a corner region of the backside illuminated imaging sensor, and wherein the seal ring support has a second width in a side region of the backside illuminated imaging sensor that is different from the first width, and wherein depositing the material comprises: depositing a metal, nitride or oxide on the back side of the epitaxial layer.

11. The method of claim 10, wherein etching the material to form the seal ring support includes removing the material from a region of the backside of the epitaxial layer directly above the imaging array.

12. The method of claim 10, further comprising masking the material prior to etching the material.

13. The method of claim 10, further comprising depositing a planarization layer on the backside of the epitaxial layer and the seal ring support.

14. The method of claim 10, further comprising separating the backside illuminated imaging sensor from an adjacent backside illuminated imaging sensor along a dicing line after forming the seal ring support.