TWI415395B - Digital to analog converter with two outputs - Google Patents

Abstract

A digital to analog converter with two outputs controlled by an input signal with n-bits is disclosed. A reference voltage circuit generates (2n+1) reference voltages numbered from 1 to (2n+1). A switch array coupled to the reference voltage circuit, a first output terminal, and a second output terminal, includes a plurality of switches switching according to the input signal. The first output terminal outputs only one of odd reference voltages according to the input signal, and the second output terminal outputs one of even reference voltages according to the input signal, and the number of the switches is less than (nx2n+2n).

Description

Digital analog converter with two inputs

The present invention relates to digital analog converters, and more particularly to digital analog converters having fewer switches.

Digital to Analog Converters (DACs) are widely used in mixed-mode systems where digital analog converters serve as an interface between digital and analog signal processing.

Figure 1 is a circuit diagram of a conventional 8-bit (2 ³ -to-2) DAC. The conventional 8-bit DAC is controlled by an input signal of 3 bits, and the output voltages V0 and V1 are determined according to the input signal. The 8-bit DAC requires 3x2 ³ + 2 ³ switches. In other words, the conventional 2 ^N- bit DAC requires Nx2 ^N + 2 ^N switches. If N is equal to 10, the number of switches of the conventional 2 ^N- bit DAC will be very large and requires a large layout area.

Figure 2 is a diagram of the general architecture of a two-stage 2 ^N- bit DAC. The two-stage 2 ^N- bit DAC includes a first-stage DAC 21 and a second-stage DAC, wherein the first-stage DAC 21 is controlled by (n-2) bits, and the second-stage DAC having four switches is determined by the least significant bit Two bit control of the element (LSB). The first stage DAC 21 outputs two voltages at most according to (n-2) bits, and then two bits of the LSB control four switches to generate an output voltage Vout. Under the conventional architecture, the number of switches of the first stage DAC 21 is very large and requires a large layout area. The present invention therefore provides a DAC with fewer switches.

An embodiment of the present invention provides a digital analog conversion unit having two input terminals, which is controlled by an input signal of n bits, and includes: a reference voltage circuit for generating (2 ⁿ +1) reference voltages, respectively 1 to (2 ⁿ +1); a first output; a second output; and a switch array coupled to the reference voltage circuit, the first output, and the second output, the switch array comprising: a plurality of switches, according to The input signal is switched, wherein the first output terminal outputs one of the odd reference voltages according to the input signal, and the second output terminal outputs one of the even reference voltages according to the input signal, and the number of the switches is less than ( n ×2 ⁿ +2 ⁿ ).

The following is a preferred mode of carrying out the invention. The preferred mode is intended to illustrate the invention but is not intended to limit the invention. The scope of the invention is mainly based on the scope of the appended claims.

Figure 3 is a diagram of a DAC in accordance with an embodiment of the present invention. In order to simplify the description, the circuit connection manner will not be described again. The reference voltage circuit 31 is used to generate (2 ³ +1) reference voltages, numbered from 1 to (2 ³ +1), respectively. In this embodiment, the reference voltage circuit 31 includes a plurality of resistors coupled in series between the first voltage input terminal and the second voltage input terminal, wherein the first voltage input terminal and the second voltage input terminal are respectively used to generate reference voltages V0 and V8. Wherein the connection points of the resistors are respectively used to generate reference voltages V1-V7. In this embodiment, when the reference voltage V8 is higher than the reference voltage V0, the voltage levels of the reference voltages V0-V8 are sequentially increased individually; conversely, when the reference voltage V8 is lower than the reference voltage V0, the reference voltages V0-V8 The voltage levels are individually reduced in sequence.

The reference voltages V2, V4, V6, and V8, which are numbered third, fifth, seventh, and nin, respectively, are classified into odd-numbered reference voltages; and the numbers are second, fourth, sixth, and eighth, respectively. The reference voltages V1, V3, V5 and V7 are classified into reference voltages numbered even. The open relationship of Figure 3 is controlled by the input signal. In this embodiment, the input signal is a Gray coded signal, wherein only two bits of the two adjacent values of the Gray code signal are different. The input signal includes three bits g0, g1, and g2. In Fig. 3, only the reference voltages V0 and V8 numbered first and ninth are controlled by three bits of the input signal, and one of the reference voltages V0 and V8 is transmitted to the first output terminal N1. Furthermore, the numbered reference voltages V1-V7 are controlled by two bits of the input signal. For example, the outputs of the reference voltages V1, V3, V5, and V7 numbered second, fourth, sixth, and eighth, respectively, are controlled by bits g1 and g2 of the input signal; the numbers are third and third, respectively. The outputs of the seven reference voltages V2 and V6 are controlled by bits g0 and g2 of the input signal; and the outputs of the fifth reference voltage V4, respectively, are controlled by bits g0 and g1 of the input signal. Furthermore, in FIG. 3, all of the reference voltages numbered even, such as the reference voltages V1, V3, V5, and V7 numbered second, fourth, sixth, and eighth, respectively, are only by the bit g1 of the input signal. And g2 are controlled, and one of the reference voltages V1, V3, V5 and V7 is transmitted to the second output terminal N2.

When the bit g0 is equal to 0, the switches SW1, SW2, and SW3 are turned on. When the bit g0 is equal to 1, the switches SW4 and SW5 are turned on. When the bit g1 is equal to 0, the switches SW6, SW7, SW8, and SW9 are turned on. When the bit g1 is equal to 1, the switches SW10, SW11, and SW12 are turned on. When the bit g2 is equal to 0, the switches SW13, SW14, SW15, and SW16 are turned on. When the bit g2 is equal to 1, the switches SW17, SW18, SW19, and SW20 are turned on. As shown in Figure 3, the 2 ^N- bit DAC of the present invention requires only (( n × 2 ⁿ ) - 2 ⁿ + n +1) switches, and the number of switches is much smaller than that required for conventional 2 ^N- bit DACs. ( n × 2 ⁿ + 2 ⁿ ) switches.

Figure 4 is a diagram of a DAC in accordance with another embodiment of the present invention. The DAC includes a first DAC unit 41 and a second DAC unit. The first DAC unit 41 receives and outputs one of the odd-numbered reference voltages. The second DAC unit 42 is controlled by the input signal but is not controlled by the third bit of the input signal for receiving and outputting one of the even-numbered reference voltages. In FIG. 4, the output voltage of the first DAC unit 41 is V _X , and the output voltage of the second DAC unit 42 is V _Y .

Figure 5 is a diagram of a DAC in accordance with another embodiment of the present invention. Compared to the DAC of Figure 3, the circuit design of the DAC in Figure 5 can save more switches. The circuit design of Figure 5 uses a binary tree architecture to set up an 8-bit DAC. In Fig. 3, the on relationship is controlled by the input signal, and the input signal includes three bits g0, g1, and g2. In Fig. 5, only the reference voltages V0 and V8 numbered first and ninth are controlled by three bits of the input signal, and one of the reference voltages V0 and V8 is transmitted to the first output terminal N1. Furthermore, the numbered reference voltages V1-V7 are controlled by two bits of the input signal. For example, the output of the fifth reference voltage V4 is controlled by the bits g0 and g1 of the input signal; the outputs of the reference voltages V2 and V6, numbered 3 and 7 respectively, are the bits of the input signal. The outputs of the reference voltages V1, V3, V5, and V9, numbered second, fourth, sixth, and eighth, respectively, are controlled by bits g1 and g2, respectively, and are controlled by bits g1 and g2 of the input signal. Furthermore, in FIG. 5, all of the reference voltages numbered even, such as the reference voltages V1, V3, V5, and V7 numbered second, fourth, sixth, and eighth, respectively, are only by the bit g1 of the input signal. And g2 are controlled, and one of the reference voltages V1, V3, V5 and V7 is transmitted to the second output terminal N2.

In the embodiment of FIG. 5, the outputs of the first and third reference voltages V0 and V2 are determined by the switch SW13 directly connected to the first output terminal N1; and the second and fourth reference voltages V1 are numbered. The output of V3 and V3 is determined by switch SW14 that is directly connected to second output terminal N2. Further, the outputs of the reference voltages V5 and V7 numbered sixth and eighth are determined by the switch SW15 directly connected to the second output terminal N2; and the outputs of the reference voltages V6 and V8 numbered seventh and ninth are directly It is determined by the switch SW16 connected to the first output terminal N1.

In another embodiment of FIG. 5, the outputs of the first and third reference voltages V0 and V2 are controlled by a switch SW13 corresponding to the input signal and the bit g2 of the first output terminal N1; The outputs of the second and fourth reference voltages V1 and V3 are controlled by a switch SW14 corresponding to the input signal and the bit g2 of the second output terminal N2. Further, the outputs of the reference voltages V5 and V7 numbered sixth and eighth are controlled by the switch SW15 corresponding to the input signal and the bit g2 of the second output terminal N2; and the seventh and ninth reference voltages V6 and The output of V8 is controlled by a switch SW16 corresponding to the input signal and bit g2 of the first output terminal N1. As shown in FIG. 5, the 2 ^N- bit DAC using the binary number architecture of the present invention has a switch number much smaller than (( n × 2 ⁿ ) - 2 ⁿ + n +1), which can save switching costs.

When the bit g0 is equal to 0, the switches SW1, SW2, and SW3 are turned on. When the bit g0 is equal to 1, the switches SW4 and SW5 are turned on. When the bit g1 is equal to 0, the switches SW6, SW7, SW8, and SW9 are turned on. When the bit g1 is equal to 1, the switches SW10, SW11, and SW12 are turned on. When the bit g2 is equal to 0, the switches SW13, SW14 are turned on. When the bit g2 is equal to 1, the switches SW15 and SW16 are turned on. According to the design of Figure 5, only 16 switches are needed to set up the 8-bit DAC. Table 1 shows the number of switches required for a differently designed 2 ^N- bit DAC.

Although the present invention has been disclosed above by the preferred embodiments, it is not intended to limit the invention. Those skilled in the art will be able to extend the application of the concepts of the present invention to encompass several variations or similar arrangements of the present invention. The scope of the invention is therefore intended to be based on the scope of the appended claims.

V1"...output voltage

V2"...output voltage

twenty one. . . Digital analog converter (DAC)

Vref_h. . . High reference voltage

Vref_I. . . Low level reference voltage

Vout. . . The output voltage

31. . . Reference voltage circuit

V0-V8. . . Reference voltage

SW1-SW20. . . switch

N1. . . First output

N2. . . Second output

41. . . First DAC unit

42. . . Second DAC unit

V _X . . . The output voltage

V _Y . . . The output voltage

The present invention can be better understood by reading the above embodiments and in conjunction with the drawings, in which:

Figure 1 is a circuit diagram of a conventional 8-bit (2 ³ -to-2) DAC;

Figure 2 is a diagram of the general architecture of a two-stage 2 ^N- bit DAC;

Figure 3 is a diagram of a DAC in accordance with an embodiment of the present invention;

Figure 4 is a diagram of a DAC in accordance with another embodiment of the present invention;

Figure 5 is a diagram of a DAC in accordance with another embodiment of the present invention.

31. . . Reference voltage circuit

V0-V8. . . Reference voltage

SW1-SW20. . . switch

N1. . . First output

N2. . . Second output

Claims (9)

A digital analog conversion unit having two inputs, controlled by an input signal of n bits, comprising: a reference voltage circuit for generating (2 ⁿ +1) reference voltages, respectively numbered from 1 to 2 ⁿ +1); a first output terminal; a second output terminal; and a switch array coupled to the reference voltage circuit, the first output terminal, and the second output terminal, wherein the switch array comprises: a plurality of switches Switching according to the input signal, wherein the first output terminal outputs one of the odd reference voltages according to the input signal, and the second output terminal outputs one of the even reference voltages according to the input signal. And the number of the above switches is less than or equal to (( n × 2 ⁿ ) - 2 ⁿ + n +1). A digital analog conversion unit having two inputs, as described in claim 1, wherein the input signal is a Gray coded signal. The digital analog conversion unit having two inputs according to claim 1, wherein only one first reference voltage and one (2 ⁿ +1) reference voltage are output by n bits of the input signal. Controlled, and the output of other reference voltages is controlled only by (n-1) bits of the above input signal. The digital analog conversion unit having two inputs according to claim 1, wherein the reference voltage circuit comprises a plurality of resistors and strings. The coupling is coupled between a first voltage input terminal and a second voltage input terminal, wherein the first voltage input terminal generates a first reference voltage, and the second voltage input terminal generates a nin reference voltage, the connection point of the resistor Providing a second reference voltage, a third reference voltage, a fourth reference voltage, a fifth reference voltage, a sixth reference voltage, a seventh reference voltage, and an eighth reference voltage, respectively, when the ninth reference voltage is higher than the first The first reference voltage, the second reference voltage, the third reference voltage, the fourth reference voltage, the fifth reference voltage, the sixth reference voltage, the seventh reference voltage, the eighth reference voltage, and the ninth reference voltage when the voltage is referenced The voltage levels are individually increased in sequence. The digital analog conversion unit having two inputs according to claim 4, wherein the output of the first and ninth reference voltages is controlled by three bits of the input signal, and the second, fourth, and sixth And an output of the eight reference voltages is controlled by the second and third bits of the input signal, and the outputs of the third and seventh reference voltages are controlled by the first and third bits of the input signal, And the output of the fifth reference voltage is controlled by the first and second bits of the input signal. The digital analog conversion unit having two inputs according to claim 4, wherein the output of the first and third reference voltages is determined by a switch directly connected to the first output terminal, and the second and the second The output of the four reference voltages is determined by a switch that is directly connected to the second output. The digital analog conversion unit having two inputs according to claim 4, wherein the output of the sixth and eighth reference voltages is determined by a switch directly connected to the second output terminal, and the seventh And the output of the ninth reference voltage is determined by a switch directly connected to the first output terminal. The digital analog conversion unit having two inputs according to claim 4, wherein the outputs of the first and third reference voltages are caused by the switches corresponding to the input signal and one of the first output terminals Controlled, and the outputs of the second and fourth reference voltages are controlled by the switches corresponding to the input signals and the aforementioned locating elements of the second output. The digital analog conversion unit having two inputs according to claim 4, wherein the output of the sixth and eighth reference voltages is caused by the switch corresponding to the input signal and one of the second output terminals. Controlled, and the outputs of the seventh and ninth reference voltages are controlled by the switches corresponding to the input signals and the aforementioned locating elements of the first output.