201126916 六、發明說明： 【發明所屬之技術領域】 本發明係有關於數位類比轉換器，特別係有關於具有 較少開關的數位類比轉換器。 【先前技術】 數位類比轉換器（Digital to Analog Converters，DAC) 廣泛地用於展合信號系統中（mixed_m〇de system)，其中數 位類比轉換益作為數位和類比信號處理之間的介面。 第1圖為習知8位元(23-to-2)DAC的電路圖。習知8 位元DAC係藉由3個位元的輸入信號所控制，並且根據輸 入信號決定輸出電壓v〇和V1。8位元DAC需要3χ23+23 個開關。換言之，習知2n位元DAC需要Nx2'2n個開關。 若N等於1〇，則習知2n位元dAC的開關數目會非常多， 並且需要很大的佈局面積。 第2圖雙級2N位元DAC —般架構的圖示。雙級2n位 疋DAC包括第一級Dac 21和第二級DAC，其中第一級 DAC 21由（n_2)個位元控制’且具有四個開關的第二級DAC 由最低有效位元(LSB)的2個位元控制。第一級j)AC 21最 多根據(n-2)個位元輸出兩個電壓，然後Lsb的2個位元控 制四個開關產生輸出電壓Vout。在習知架構下，第一級 I>AC 21的開關數目會非常多，並且需要很大的佈局面積。 因此本發明提供具有較少開關的DAC。 【發明内容】 4 201126916 轉換η:實施例提供一種具有兩輪入端的數位類比 得換早7L，藉由η個位元的輸入信號所控制，包括.來 電壓電路，用以產生(2η+1)個參考電壓，分㈣丨編號 ； ； ^ 乂考電£電路、第一輸出端，以及第二輸 包括：複數開關，根據輪人信號而列 係根據輪入信號來輸出奇數的參键之二：第;= 端係根據輸入信號來輸出偶數的參考電壓之一者，j 關的數目少於〇7x2”+2")。 、’幵1 【實施方式】 俜二：：2實施本發明的較佳模式。所述的較佳模式 ^ 明本發明但並非心限制本發明。本發明的範圍 係以所附之申請專利範圍為主。 第3圖為根據本發明一實施例之dac的圖示 ^ 5兄明3’其電路連接方式不再贅述。參考電壓電路31用二 產生(2 +1)個參考電屢，分別由1編號至(2冲。在本實施 參考㈣電路31包括複數電阻串聯祕於第一電屢 二入端和第—電壓輸人端間，第—電屢輸人端和第二電愿 輸t端分別用以產生參考電屢V0和V8,其t電阻的連接 別用以產生參考電麼V1_V7。在本實施例中，當表考 V8㈣VQ時’參考 —Μ的電塵準位 ，個別依序提而，反之，當參考電屢w低於參考電屢 時’參考電壓V0_V8的電壓準位係個別依序降低。 編號分別為第三、第五、第七和第九的參考電屢V2、 201126916 V4、V6和V8被歸類至編號為奇數的參考電壓；且編號分 別為第二、第四、第六和第八的參考電壓VI、V3、V5和 V7被歸類至編號為偶數的參考電壓。第3圖的開關係由輸 入信號所控制。在本實施例中，輸入信號為格雷碼信號 (Gray coded signal)，其中格雷碼信號之兩個相鄰值僅有一 個位元不同。輸入信號包括三個位元g0、gl和g2。在第3 圖中，只有編號為第一和第九的參考電壓V0和V8係由輸 入信號的三個位元所控制，並且參考電壓V0和V8之一者 被傳送至第一輸出端N1。再者，編號居間的參考電壓V1-V7 係由輸入信號的兩個位元所控制。舉例而言，編號分別為 第二、第四、第六和第八的參考電壓VI、V3、V5和V7 的輸出係由輸入信號的位元gl和g2所控制；編號分別為 第三和第七的參考電壓V2和V6的輸出係由輸入信號的位 元g0和g2所控制；並且編號分別為第五的參考電壓V4 的輸出係由輸入信號的位元g〇和g 1所控制。再者，在第 3圖中》所有編號為偶數的參考電壓5例如編號分別為第 二、第四、第六和第八的參考電壓VI、V3、V5和V7僅 由輸入信號的位元gl和g2所控制，並且參考電壓VI、V3、 V5和V7之一者被傳送至第二輸出端N2。 當位元g0等於0時，開關SW1、SW2和SW3導通。 當位元g0等於1時，開關SW4和SW5導通。當位元gl 等於0時，開關SW6、SW7、SW8和SW9導通。當位元 gl等於1時，開關SW10、SW11和SW12導通。當位元 g2等於0時，開關SW13、SW14、SW15和SW16導通。 當位元g2等於1時，開關SW17、SW18、SW19和SW20 201126916 導通。如第3圖所示，本發明的2N位元dac僅需 (㈣2”)_2” 個開關’其開關數目遠小於習知2N位元DAC 所需的(wx2”+2”)個開關。 第4圖為根據本發明另一實施例之dac的圖示。DAc 包括第—DAC單元41和第二DAC單元。[DAC單元 41接收並輸出編號為奇數的參考電壓之一者。第二 單元42由輸入信號所控制但不由輸入信號第三的位元所 控制，用以接收並輸出編號為偶數的參考電壓之一者。在 第4圖中’第一 DAC單元41的輸出電壓為Vx，且第二 DAC單元42的輸出電壓為Vy。 第5圖為根據本發明另一實施例之DAc的圖示。相較 於第3圖的DAC，第5圖中DAC的電路設計能夠節省更 多的開關。第5圖的電路設計使用二元樹架構_町_ :⑽㈣來設置8位元說。在第3圖中，開關係由輸 入域所控制’且輪入信號包括三個位元g〇、gi和以。 /第圖中〃、有編號為第一和第九的參考電壓v〇*V8 糸由輸入彳5摘二個位元所控制，並且參考㈣v〇和 =者被傳送至第—輸出端N卜再者，編號居間的參考電 號八？由輸入信號的兩個位元所控制。舉例而言，編 二 的參考電壓V4的輸出係由輸入信號的位元 戶斤控制；編號分別為第三和第七的參考電廢V2和 分別為L出係由輸入信號的位元g〇 #g2所控制；並且編號 和ΛΑ 一、第四、第六和第八的參考電壓V1、V3、V5 的輪出係由輸入信號的位元gl和g2所控制。再者， θ中’所有編號為偶數的參考電，例如編號分別 201126916 為第二、第四、第六和第八的參考電壓vi、201126916 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to digital analog converters, and more particularly to digital analog converters having fewer switches. [Prior Art] Digital to Analog Converters (DACs) are widely used in the integrated signal system (mixed_m〇de system), where digital analog conversion is used as an interface between digital and analog signal processing. Figure 1 is a circuit diagram of a conventional 8-bit (23-to-2) DAC. The conventional 8-bit DAC is controlled by an input signal of 3 bits, and the output voltages v〇 and V1 are determined according to the input signal. The 8-bit DAC requires 3χ23+23 switches. In other words, the conventional 2n-bit DAC requires Nx2'2n switches. If N is equal to 1 〇, the number of switches of the conventional 2n-bit dAC will be very large, and a large layout area is required. Figure 2 is a diagram of the general architecture of a two-stage 2N-bit DAC. The two-stage 2n-bit 疋 DAC includes a first stage Dac 21 and a second stage DAC, wherein the first stage DAC 21 is controlled by (n_2) bits and the second stage DAC having four switches is determined by the least significant bit (LSB) 2 bit control. The first stage j) AC 21 outputs two voltages according to (n-2) bits at most, and then two bits of Lsb control four switches to generate an output voltage Vout. Under the conventional architecture, the number of switches of the first stage I>AC 21 will be very large and requires a large layout area. The present invention therefore provides a DAC with fewer switches. [Invention] 4 201126916 conversion η: embodiment provides a digital analog with two rounds of the end of the 7L, controlled by the input signal of n bits, including the voltage circuit, used to generate (2η+1 a reference voltage, sub- (four) 丨 number; ; ^ 电 test electric circuit, the first output, and the second input includes: a plurality of switches, according to the wheel signal, according to the wheel signal to output an odd number of keys Second: the first; = end according to the input signal to output one of the even reference voltage, the number of j off is less than 〇7x2" + 2 ")., '幵1 [Embodiment] 俜 2:: 2 implementation of the present invention The preferred mode of the invention is not intended to limit the invention, but the scope of the invention is mainly based on the scope of the appended patent application. Fig. 3 is a diagram of a dac according to an embodiment of the invention. The figure ^ 5 brother Ming 3 'the circuit connection is not described again. The reference voltage circuit 31 uses two to generate (2 +1) reference power, respectively, from 1 to (2 rush. In this implementation reference (4) circuit 31 includes Complex resistors are connected in series to the first electrical and secondary terminals and the first voltage Between the input terminals, the first-to-electrical input terminal and the second-powered input t-end are respectively used to generate reference voltages V0 and V8, and the connection of the t-resistance is used to generate the reference power V1_V7. In this embodiment When the V8 (four) VQ is tested, the reference-Μ's electric dust level is individually raised, and vice versa. When the reference power is repeatedly lower than the reference power, the voltage level of the reference voltage V0_V8 is sequentially lowered individually. The reference voltages V2, 201126916 V4, V6, and V8, which are the third, fifth, seventh, and ninth, respectively, are classified into odd-numbered reference voltages; and the numbers are second, fourth, sixth, and The reference voltages VI, V3, V5, and V7 of eight are classified into reference voltages numbered evenly. The open relationship of Fig. 3 is controlled by the input signal. In this embodiment, the input signal is a Gray coded signal. Wherein the two adjacent values of the Gray code signal differ by only one bit. The input signal includes three bits g0, gl, and g2. In Figure 3, only the first and ninth reference voltages V0 are numbered. And V8 are controlled by three bits of the input signal, and reference voltages V0 and V8 The first reference terminal V1 is transmitted to the first output terminal N1. Further, the numbered reference voltages V1-V7 are controlled by two bits of the input signal. For example, the numbers are second, fourth, sixth, and The output voltages of the eight reference voltages VI, V3, V5 and V7 are controlled by the bits gl and g2 of the input signal; the outputs of the reference voltages V2 and V6, numbered 3 and 7 respectively, are the bits g0 of the input signal. And the output of the reference voltage V4, which is numbered fifth, respectively, is controlled by the bits g 〇 and g 1 of the input signal. Furthermore, in Fig. 3, all of the reference voltages 5 of the even number are, for example, The reference voltages VI, V3, V5, and V7 numbered second, fourth, sixth, and eighth, respectively, are controlled by bits gl and g2 of the input signal, and one of the reference voltages VI, V3, V5, and V7 It is transmitted to the second output terminal N2. When the bit g0 is equal to 0, the switches SW1, SW2, and SW3 are turned on. When the bit g0 is equal to 1, the switches SW4 and SW5 are turned on. When the bit gl is equal to 0, the switches SW6, SW7, SW8, and SW9 are turned on. When the bit gl is equal to 1, the switches SW10, SW11, and SW12 are turned on. When the bit g2 is equal to 0, the switches SW13, SW14, SW15, and SW16 are turned on. When bit g2 is equal to 1, switches SW17, SW18, SW19, and SW20 201126916 are turned on. As shown in Fig. 3, the 2N-bit dac of the present invention requires only ((4) 2")_2" switches' whose number of switches is much smaller than that required by the conventional 2N-bit DAC (wx2" + 2") switches. Figure 4 is a diagram of a dac in accordance with another embodiment of the present invention. The DAc includes a first DAC unit 41 and a second DAC unit. [DAC unit 41 receives and outputs one of the odd-numbered reference voltages. The second unit 42 is controlled by the input signal but is not controlled by the third bit of the input signal for receiving and outputting one of the even-numbered reference voltages. In Fig. 4, the output voltage of the first DAC unit 41 is Vx, and the output voltage of the second DAC unit 42 is Vy. Figure 5 is a diagram of a DAc in accordance with another embodiment of the present invention. Compared to the DAC of Figure 3, the circuit design of the DAC in Figure 5 can save more switching. The circuit design of Figure 5 uses the binary tree architecture _ _ _ : (10) (four) to set the 8-bit theory. In Fig. 3, the open relationship is controlled by the input domain' and the rounding signal includes three bits g〇, gi and . / In the figure, the reference voltages v〇*V8, numbered first and ninth, are controlled by the input 彳5, and the reference (4)v〇 and = are transmitted to the first-output terminal N. Furthermore, the numbered reference number eight? Controlled by two bits of the input signal. For example, the output of the reference voltage V4 of the second is controlled by the bit of the input signal; the reference electric waste V2, which is numbered third and seventh, respectively, and the bit g, which is the output signal, respectively. #g2 is controlled; and the numbering and 轮 of the first, fourth, sixth and eighth reference voltages V1, V3, V5 are controlled by the bits gl and g2 of the input signal. Furthermore, in θ, all reference numbers that are evenly numbered, for example, number 201126916 are the reference voltages vi of the second, fourth, sixth and eighth, respectively.
Vj、V5 和 V7 僅由輸入信號的位元gl和g2所控制，並且參考電壓νι、 V3、V5和V7之一者被傳送至第二輸出端N2。 、 在第5圖的實施例中，編號第一和第三的參考電壓 和V2的輸出係由直接連接至第一輸出端m的開關 所決定；並且編號第二和第四的參考電壓Vl和的 係由直接連接至第二輸出端N2的開關SWl4所決定。]出 外，編號第六和第八的參考電M V5 * V7白勺輸出=直= 連接至第二輸出端N2的開關SW15所決定；並且編號第七 和第九的參考電壓¥6和V8的輸出係由直接連接至第一 出端N1的開關s W16所決定。 ' 在第5圖的另一實施例中，編號第一和第三的參考電 壓V0和V2的輸出係由相應於輸入信號和第一輸出端 之位元g2的開關SW13所控制；並且編號第二和第四的參 考電壓VI和V3的輸出係由相應於輸入信號和第二輸出端 N2之位元g2的開關SW14所控制。此外，編號第六和第 八的參考電壓V5和V7的輸出係由相應於輸入信號和第二 輸出端N2之位元g2的開關SW15所控制；並且編號第七 和第九的參考電壓¥6和V8的輸出係由相應於輸入信號和 第一輸出端N1之位元g2的開關SW16所控制。如第5圖 所示’本發明中使用二元數架構的2N位元DAC，其開關數 目遠小於((《以卜^+”…’能夠節省開關的費用。 當位元g0等於〇時，開關SW1、SW2和SW3導通。 當位元g〇等於1時，開關SW4和SW5導通。當位元gl 等於〇時’開關SW6、SW7、SW8和SW9導通。當位元 201126916 gl等於1時，開關SW10、SW11和SW12導通。當位元 g2等於0時，開關SW13、SW14導通。當位元g2等於1 時，開關SW15和SW16導通。根據第5圖的設計，僅需 16個開關來設置8位元DAC。表1顯示不同設計之2N位 元DAC所需的開關數目。 表1 位元（η) 開關數目 習知 第3圖 第5圖 3 32 20 16 4 80 53 45 6 448 327 263 8 2304 1801 1545 10 11264 9227 8715 12 53248 45069 43021Vj, V5 and V7 are only controlled by bits gl and g2 of the input signal, and one of the reference voltages νι, V3, V5 and V7 is transmitted to the second output terminal N2. In the embodiment of FIG. 5, the first and third reference voltages and the output of V2 are determined by switches directly connected to the first output terminal m; and the second and fourth reference voltages V1 and It is determined by the switch SW14 directly connected to the second output terminal N2. Out, the sixth and eighth reference electric power M V5 * V7 output = straight = connected to the second output terminal N2 switch SW15; and the seventh and ninth reference voltages ¥ 6 and V8 The output is determined by a switch s W16 that is directly connected to the first terminal N1. In another embodiment of FIG. 5, the outputs of the first and third reference voltages V0 and V2 are controlled by a switch SW13 corresponding to the input signal and the bit g2 of the first output; The outputs of the second and fourth reference voltages VI and V3 are controlled by a switch SW14 corresponding to the input signal and the bit g2 of the second output terminal N2. Further, the outputs of the reference voltages V5 and V7 numbered sixth and eighth are controlled by the switch SW15 corresponding to the input signal and the bit g2 of the second output terminal N2; and the reference voltages of the seventh and ninth numbers are ¥6 The output of V8 and V8 is controlled by a switch SW16 corresponding to the input signal and bit g2 of the first output terminal N1. As shown in Fig. 5, the 2N-bit DAC using the binary number architecture in the present invention has a switch number much smaller than (("I can save the cost of the switch." When the bit g0 is equal to 〇, The switches SW1, SW2 and SW3 are turned on. When the bit g〇 is equal to 1, the switches SW4 and SW5 are turned on. When the bit gl is equal to 〇, the switches SW6, SW7, SW8 and SW9 are turned on. When the bit 201126916 gl is equal to 1, The switches SW10, SW11 and SW12 are turned on. When the bit g2 is equal to 0, the switches SW13 and SW14 are turned on. When the bit g2 is equal to 1, the switches SW15 and SW16 are turned on. According to the design of Fig. 5, only 16 switches are required to be set. 8-bit DAC. Table 1 shows the number of switches required for differently designed 2N-bit DACs. Table 1 Bits (η) Number of Switches Conventional Figure 3 Figure 5 Figure 3 32 20 16 4 80 53 45 6 448 327 263 8 2304 1801 1545 10 11264 9227 8715 12 53248 45069 43021
雖然本發明已由較佳實施例揭露如上，但並非用以限 定本發明。習知技藝者應能延伸應用本發明的概念以涵括 Φ 本發明的數種變型或類似的設置。因此本發明的範圍係以 所附之申請專利範圍為主。 201126916 【圖式簡單說明】 本發明能藉由閱讀上述實施方式並搭配圖示而被較佳 地理解，其中： 第1圖為習知8位元(23-to-2)DAC的電路圖； 第2圖雙級2N位元DAC之一般架構的圖示； 第3圖為根據本發明一實施例之DAC的圖示； 第4圖為根據本發明另一實施例之DAC的圖示； 第5圖為根據本發明另一實施例之DAC的圖示。 【主要元件符號說明】 VI”〜輸出電壓； V2”〜輸出電壓； 21〜數位類比轉換器（DAC);Although the invention has been disclosed above by the preferred embodiments, it is not intended to limit the invention. Those skilled in the art will be able to extend the application of the concepts of the present invention to include Φ several variations of the invention or similar arrangements. The scope of the invention is therefore intended to be the scope of the appended claims. 201126916 [Simplified description of the drawings] The present invention can be better understood by reading the above embodiments and with the accompanying drawings, wherein: Figure 1 is a circuit diagram of a conventional 8-bit (23-to-2) DAC; 2 is a diagram showing a general architecture of a two-stage 2N-bit DAC; FIG. 3 is a diagram of a DAC according to an embodiment of the present invention; FIG. 4 is a diagram of a DAC according to another embodiment of the present invention; The figure is a diagram of a DAC in accordance with another embodiment of the present invention. [Main component symbol description] VI"~ output voltage; V2"~ output voltage; 21~digital analog converter (DAC);
Vref_h〜高準位的參考電壓；Vref_h~ high reference voltage;
Vref_I〜低準位的參考電壓；Vref_I~ low level reference voltage;
Vout〜輸出電壓； 31〜參考電壓電路； V0-V8〜參考電壓； SW1-SW20〜開關； N1〜第一輸出端； N2〜第二輸出端； 41〜第一 DAC單元； 42〜第二DAC單元；Vout~output voltage; 31~reference voltage circuit; V0-V8~reference voltage; SW1-SW20~switch; N1~first output terminal; N2~second output terminal; 41~first DAC unit; 42~second DAC unit;
Vx〜輸出電壓；Vx~output voltage;