TWI574385B - Non-volatile memory structure and manufacturing method thereof - Google Patents

Description

Non-volatile memory structure and manufacturing method thereof

The invention relates to a non-volatile memory structure and a manufacturing method thereof, in particular to a silicon-oxide-nitride-oxide-semiconductor (hereinafter referred to as SONOS) structure. Non-volatile memory structure and its making method.

A semiconductor memory system is a semiconductor component used to store data or data in a computer or an electronic product. The semiconductor memory system can be roughly classified into a volatile memory and a non-volatile memory, wherein the non-volatile memory has a power supply. It is widely used because it is interrupted and causes the loss of stored data.

As one of the non-volatile recording materials, the SONOS memory structure mainly has a nitride layer interposed between two oxide layers, and the nitride layer acts as an electron or electric charge trapping layer (charge trap). The two layers of oxide layers above and below the charge trapping layer are respectively disposed as a charge tunnel layer and a charge block layer. An oxide-nitride-oxide (ONO) structure, which is a main component of the information storage, is disposed on the semiconductor substrate, and a floating gate is further disposed thereon. It is called a SONOS memory.

However, as computer microprocessors become more powerful, the demand for high-capacity, low-cost memory is increasing. In order to meet this trend and the continuing challenges of semiconductor technology for high integration, the memory structure is becoming more and more compact, and the process of memory structure is becoming more and more complicated. In addition to the challenges in the process, the manufacturer is faced with the problem that the film elements are easily affected by the process during the manufacturing process, and the memory component yield and electrical performance are lowered. For example, the nitride layer as a charge trapping layer in SONOS memory is a critical structural component of SONOS memory. Therefore, how to continuously protect the nitride layer in the process is a goal that semiconductor companies have been striving for. .

Accordingly, it is an object of the present invention to provide a non-volatile memory structure that avoids the impact of a nitride layer in a semiconductor process and a method of fabricating the same.

According to the scope of the invention provided by the present invention, a method of fabricating a non-volatile memory structure is provided. The fabrication method first provides a substrate comprising a memory region and a logic region, and a dielectric layer and a conductive layer are sequentially formed on the substrate. Next, the logic region is covered and the conductive layer and the dielectric layer in the memory region are etched to form at least one first gate in the memory region. After the first gate is formed, an ONO structure is formed at the bottom of the first gate near the sidewall. After forming the ONO structure, an oxide structure is formed on the substrate, and the oxide structure covers the ONO structure. After forming the oxide structure, the memory region is covered and the conductive layer and the dielectric layer are etched in the logic region to form a second gate in the logic region. After the second gate is formed, a first sidewall is formed on a sidewall of the first gate and a second sidewall is formed on a sidewall of the second gate.

In accordance with the scope of the invention provided by the present invention, a non-volatile memory structure is also provided. The non-volatile memory structure includes a substrate having a memory region and a logic region, a first gate disposed in the memory region, and a second gate disposed in the logic region. An ONO structure at the bottom of the first gate, an oxide structure disposed on a sidewall of the first gate, and a first sidewall and a second sidewall disposed on the first gate a sidewall of the pole, and the second sidewall is disposed on a sidewall of the second gate.

The non-volatile memory structure and the method of fabricating the same according to the present invention can be integrated with existing logic processes, and more importantly, by the oxide structure formed on the sidewall of the first gate, the present invention provides The non-volatile memory structure is fabricated to effectively protect any film layer in the ONO structure, especially the nitride film layer. The nitride film layer is not damaged in the subsequent process, thereby ensuring its charge trapping function. Therefore, the non-volatile memory structure provided by the present invention can ensure a good electrical performance.

100‧‧‧Base

102‧‧‧ memory area

104‧‧‧Logical area

106‧‧‧Dielectric layer

108‧‧‧ Conductive layer

120‧‧‧first gate

122‧‧‧ Groove

124a, 124b‧‧‧ first oxide layer

126‧‧‧First nitride layer

128‧‧‧ONO structure

132‧‧‧Oxide structure

134‧‧‧First lightly doped bungee

140‧‧‧second gate

142‧‧‧Mat oxide layer

144‧‧‧Second lightly doped bungee

146‧‧‧ third oxide layer

148‧‧‧Second nitride layer

150‧‧‧First side wall

152‧‧‧Second side wall

154‧‧‧First source/bungee

156‧‧‧Second source/dip

160‧‧‧ memory components

162‧‧‧Logical components

1 to 9 are schematic views of a preferred embodiment of a method of fabricating a non-volatile memory structure provided by the present invention.

10 through 11 are schematic views of a variation of the preferred embodiment.

Please refer to FIG. 1 to FIG. 9 . FIG. 1 to FIG. 9 are schematic diagrams showing a preferred embodiment of a method for fabricating a non-volatile memory structure provided by the present invention. As shown in FIG. 1, the preferred embodiment first provides a substrate 100, such as A stack of substrates. The substrate includes a memory region 102 and a logic region 104, and a dielectric layer 106 and a conductive layer 108 are sequentially formed on the surface. In the preferred embodiment, the dielectric layer 106 is a ruthenium oxide layer formed by a thermal oxidation process or a deposition process, and the conductive layer is a polysilicon layer, but is not limited thereto. In addition, in the substrate 100, a p-type well region or an n-type well region or the like required for the semiconductor element can be formed first (not shown).

Please continue to see Figure 1. Subsequently, a mask layer 110 and a photoresist layer 112 are formed on the surface of the substrate 100. It should be noted that the mask layer 110 and the photoresist layer 112 completely cover the logic region 104; however, the photoresist layer 112 in the memory region 102 is patterned to define a gate structure to be formed. position. After the mask layer 110 and the patterned photoresist layer 112 are formed, an etching process is performed, and the mask layer 110 exposed by the patterned photoresist layer 112 is etched while the logic region 102 is covered and protected. The conductive layer 108 and the dielectric layer 106 form at least one first gate 120 in the memory region 102. As shown in FIG. 1, the first gate 120 includes at least a conductive layer 108 and a dielectric layer 106.

Please refer to Figure 2. After removing the photoresist layer 112 and the mask layer 110 in the memory region 102, the dielectric layer 106 at the bottom of the first gate 120 is etched to form a cavity 122 in the dielectric layer 106. After the recess 122 is formed, a first oxide layer 124a/124b is formed on the substrate 100. It should be noted that, since the conductive layer 108 and the substrate 100 both comprise a germanium material in the preferred embodiment, the first oxide layer 124a/124b is preferably formed by a thermal oxidation process, and thus the first oxide layer 124a. /124b is formed on the surface of any exposed tantalum material. As shown in FIG. 2, the top, sidewall and partial bottom of the conductive layer 108 of the first gate 120 form a first oxide layer 124a, and part of the surface of the substrate 100 is A first oxide layer 124b is formed.

Please refer to Figures 3 and 4. After forming the first oxide layer 124a/124b, a first nitride layer 126 is formed on the substrate 100. It is worth noting that the first nitride layer 126 fills the recess 122 as shown in FIG. After the first nitride layer 126 is formed, an etching process is performed to remove a portion of the first nitride layer 126 and the first oxide layer 124a/124b on the top of the gate and the surface of the substrate 100. The gate 120 forms an ONO structure 128 that fills the recess 122 near the bottom of the sidewall. As shown in FIG. 4, the ONO structure 128 includes a first oxide layer 124a formed at the bottom of the conductive layer 108 of the first gate 120 and a first oxide layer formed on the surface of the substrate 100 under the first gate 120. 124b, and a first nitride layer 126 interposed between the two first oxide layers 124a/124b. In addition, in this embodiment, the first nitride layer 126 has an L shape after the etch back process, and a portion of the first nitride layer 126 still covers the sidewall of the first gate 120 as shown in FIG. . Since the ONO structure 128 is disposed on the semiconductor substrate 100 and covered by a conductive layer 108 as a control gate, the fabrication of the SONOS memory structure is completed.

Please refer to Figure 5 and Figure 6. After forming the ONO structure 128, a second oxide layer 130 is formed on the substrate 100, such as, but not limited to, a tetra-ethyl-ortho-silicate (TEOS) layer. In the preferred embodiment, one of the second oxide layers 130 has a thickness of between 100 and 1000 angstroms, but is not limited thereto. Subsequently, another etching process is performed to remove a portion of the second oxide layer 130, and an oxide structure 132 covering the first nitride layer 126 and the ONO structure 128 is formed on the sidewall of the first gate 120, and is completely The second oxide layer 130 on the logic region 104 is removed. It is worth noting that this uses an etch back process. The oxide structure 132 is formed to have a thickness between 50 and 600 angstroms. Please refer to Figure 6. After forming the oxide structure 132, an ion implantation process may be performed to form a first lightly-doped drain (LDD) 134 in the substrate 100 on both sides of the first gate 120, respectively. As previously mentioned, the logic region 104 is still covered by the mask layer 110 during the formation of the first LDD 134 or the like.

Please refer to Figure 7. After forming the first LDD 134, a mask layer 136 is formed in the memory region 102, and the conductive layer 108 and the dielectric layer 106 in the logic region 104 are patterned to form at least a second in the logic region 104. Gate 140. After the second gate 140 is formed, the dielectric layer 106 may still be present on the substrate 100, and the remaining dielectric layer 106 may have a thickness of 0 to 100 angstroms. After the second gate 140 is formed, a pad oxide layer 142 is formed on the substrate 100. After the pad oxide layer 142 is formed, an ion implantation process is performed, and a second LDD 144 is formed in the substrate 100 on both sides of the second gate 140.

Please refer to Figure 8. After the second LDD 144 is formed, the mask layer 136 within the memory region 102 is removed. It should be noted that, in the foregoing steps, FIGS. 1 to 6 and related descriptions disclose the steps of fabricating the constituent elements in the memory region 102 in the preferred embodiment, and FIG. 7 and related descriptions thereof. The steps of fabricating the constituent elements in the logic region 104 in the preferred embodiment are disclosed. After the completion of the second LDD 144 and the removal of the mask layer 136, the steps of fabricating the constituent elements in the memory region 102 and the logic region 104 can be performed simultaneously. As shown in FIG. 8, next, a third oxide layer 146 and a second nitride layer 148 are sequentially formed on the substrate 100.

Please refer to Figure 9. Forming a third oxide layer 146 and a second nitridation After the layer 148, an etching process is performed to remove a portion of the second nitride layer 148 and a portion of the third oxide layer 146 to form sidewalls of the first gate 120 and the second gate 140, respectively. A first side wall 150 and a second side wall 152. As shown in FIG. 9, in the memory region 102, the first sidewall sub-150 may include a second nitride layer 148 and a third oxide layer 146; in the logic region 104, the second sidewall sub-152 may include Dinitride layer 148, third oxide layer 146 and pad oxide layer 142. Further, as shown in FIG. 9, the oxide structure 132 is interposed between the ONO structure 128 and the third oxide layer 146.

Please continue to see Figure 9. After the fabrication of the first sidewall 150 and the second sidewall 152, a first source/drain 154 and a second gate 140 are formed in the substrate 100 on both sides of the first gate 120, respectively. A second source/drain 156 is formed in each of the substrates 100 on both sides. So far, the creation of a logic component 160 in the memory region 102 and a logic component 162 in the logic region 104 is completed.

The non-volatile memory structure and the method of fabricating the same according to the preferred embodiment can be integrated with existing logic processes and, more importantly, by an oxide structure 132 formed on the sidewall of the first gate 120. Protecting the ONO structure 128, and in particular providing the first nitride layer 126 of the ONO structure 128, is sufficiently protected from damage to the first nitride layer 126 during subsequent processing to affect its charge trapping function.

In addition, please refer to FIG. 10 to FIG. 11 , and FIG. 10 to FIG. 11 are schematic diagrams showing a variation of the preferred embodiment. Those familiar with the art should know that after forming the first LDD 134, they will begin to face the first LDD in the subsequent process. 134 is a problem that affects its outline due to heat and spreads toward the center of the first gate 120. Therefore, in the present variation, the thickness of the first gate 120 and the thickness of the second oxide layer 130 or the oxide structure 132 can be adjusted to optimize the position of the first LDD 134 with respect to the ONO structure 128. Referring to FIG. 6 and FIG. 10 at the same time, according to the variation, the width of the first gate 120 can be reduced while maintaining the same channel length L and without changing the existing logic process. Increasing the thickness of the oxide structure 132 optimizes the position of the first LDD 134 relative to the ONO structure 128 for optimum charge capture efficiency. Therefore, it is avoided that the first LDD 134 profile that is excessively diffused in subsequent processes affects the electrical performance of the SONOS memory structure.

Please refer to Figure 11. After the fabrication of the second gate 140, the pad oxide layer 142, and the second LDD 144 in the logic region 104, and the third oxide layer 146 and the second nitride layer 148 are sequentially formed on the substrate 100. The etchback process as described above can be performed. It is to be noted that since the oxide structure 132 of the present variation has a large thickness, a relatively flat surface is provided, and the third oxide layer 146 and the second nitride layer 148 which are subsequently formed thereon are also obtained. A relatively flat outline. More importantly, the second nitride layer 148 having this flat profile is more easily etched during the etch back process, even as removed throughout Figure 11. Therefore, in this variation, the first sidewall sub-150 in the memory region 102 may only include the remaining third oxide layer 146; and the second sidewall sub-152 in the logic region 104 includes the second nitride layer 148, The third oxide layer 146 and the pad oxide layer 142. It is also worth noting that although the first sidewall sub-150 includes only the third oxide layer 146 in the present variation, the first sidewall sub-150 and the oxide structure 132 are subsequently formed during the subsequent fabrication of the first source/drain. The thickness can still define the location at which the first source/drain (not shown) is formed. In other words, even thickness The thicker oxide structure 132 causes the first sidewall sub-150 to no longer comprise the second nitride layer 148, and the variant can still successfully fabricate the first source/deuterium in a predetermined position without affecting the process results. pole.

According to the variation, the first LDD 134 can be avoided by reducing the width of the first gate 120 and increasing the thickness of the oxide structure 132 while maintaining the same channel length L and without changing the existing logic process. The diffusion profile in subsequent processes affects the electrical performance of the SONOS memory structure. In addition, the increase in the thickness of the oxide structure 132 may result in the first sidewall sub-150 within the memory region 102 containing only the third oxide layer 146. However, since the thickness of the oxide structure 132 is sufficient, it can still be effective in subsequent processes. The ONO structure 128 is protected from the first nitride layer 126. Furthermore, as previously described, even though the thicker oxide structure 132 of the present variation causes the first sidewall sub-150 to no longer comprise the second nitride layer 148, the variant can still make the first source in a predetermined position/ Bungee jumping.

In summary, the non-volatile memory structure and the method for fabricating the same according to the present invention can be successfully integrated with an existing logic process without affecting the logic region process at all. More importantly, the non-volatile memory structure provided by the present invention can effectively protect any film layer in the ONO structure, especially nitrogen, by the oxide structure formed on the sidewall of the first gate. Chemical film layer. The nitride film layer is not damaged in the subsequent process, thereby ensuring its charge trapping function. Therefore, the non-volatile memory structure provided by the present invention can ensure a good electrical performance. In addition, the present invention can also adjust the distance between the LDD and the ONO structure under the premise of the same channel length by adjusting the width of the gate structure and increasing the thickness of the oxide structure, thereby avoiding the influence of the diffusion profile of the LDD in the subsequent process. Electrical performance of SONOS memory structures.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Base

102‧‧‧ memory area

104‧‧‧Logical area

106‧‧‧Dielectric layer

108‧‧‧ Conductive layer

120‧‧‧first gate

122‧‧‧ Groove

124a, 124b‧‧‧ first oxide layer

126‧‧‧First nitride layer

128‧‧‧ONO structure

132‧‧‧Oxide structure

134‧‧‧First lightly doped bungee

140‧‧‧second gate

142‧‧‧Mat oxide layer

144‧‧‧Second lightly doped bungee

146‧‧‧ third oxide layer

148‧‧‧Second nitride layer

150‧‧‧First side wall

152‧‧‧Second side wall

154‧‧‧First source/bungee

156‧‧‧Second source/dip

160‧‧‧ memory components

162‧‧‧Logical components

Claims (18)

A method for fabricating a non-volatile memory structure includes: providing a substrate, the substrate comprising a memory region and a logic region, and sequentially forming a dielectric layer and a conductive layer on the substrate; covering the logic region And etching the conductive layer and the dielectric layer in the memory region to form at least one first gate in the memory region; forming an oxide-nitride in the bottom of the first gate near the sidewall An oxide-nitride-oxide (ONO) structure; forming an oxide structure on the substrate to cover the ONO structure; after forming the oxide structure, covering the memory region and etching the conductive layer in the logic region Forming at least one second gate in the logic region; and forming a first sidewall on a sidewall of the first gate and forming a second sidewall on a sidewall of the second gate child. The method of fabricating the non-volatile memory structure of claim 1, wherein the step of forming the ONO structure further comprises: forming a recess in the dielectric layer at the bottom of the first gate; Forming a first oxide layer on the substrate, covering the bottom of the first gate and a portion of the substrate; forming a first nitride layer on the substrate to fill the recess; and removing a portion of the first nitride layer To form the ONO structure. The method for fabricating a non-volatile memory structure according to claim 1, wherein the step of forming the oxide structure further comprises: Forming a second oxide layer on the substrate; and removing a portion of the second oxide layer to form the oxide structure, and the oxide structure covers the ONO structure. The method for fabricating a non-volatile memory structure according to claim 3, wherein one of the second oxide layers has a thickness of between 100 and 1000 angstroms. The method for fabricating a non-volatile memory structure according to claim 3, wherein one of the oxide structures has a thickness of 50-600 angstroms. The method for fabricating the non-volatile memory structure of claim 1, further comprising forming a first lightly doped drain in the substrate on both sides of the first gate. The step of LDD) is performed before the second gate is formed in the logic region. The method for fabricating a non-volatile memory structure according to claim 1, wherein the step of forming the first sidewall and the second sidewall further comprises: sequentially forming a third oxide on the substrate a layer and a second nitride layer; and removing a portion of the second nitride layer and a portion of the third oxide layer to form the first sidewall and the second sidewall. The method for fabricating a non-volatile memory structure according to claim 1, further comprising the step of forming a second LDD in the substrate on both sides of the second gate, forming the first sidewall Before the child and the second side wall. The method for fabricating a non-volatile memory structure according to claim 1, further comprising forming a first source/drain in the substrate on both sides of the first gate And a step of forming a second source/drain in the substrate on both sides of the second gate. A non-volatile memory structure includes: a substrate including a memory region and a logic region; a first gate and a second gate, the first gate being disposed in the memory region The second gate is disposed in the logic region; an ONO structure is disposed at the bottom of the first gate; an oxide structure is disposed on the sidewall of the first gate; a first LDD is disposed on the The first gate and the two sides of the substrate, and the oxide structure does not overlap with the first LDD; and a first sidewall and a second sidewall, the first sidewall is disposed on the first gate a sidewall, and the second sidewall is disposed on a sidewall of the second gate. The non-volatile memory structure of claim 10, wherein the first gate and the second gate comprise a conductive layer and a dielectric layer. The non-volatile memory structure of claim 11, wherein the ONO structure further comprises: a first oxide layer disposed on the bottom of the conductive layer and the surface of the substrate under the first gate; A first nitride layer is interposed between the first oxide layers, and a portion of the first nitride layer covers sidewalls of the first gate. The non-volatile memory structure of claim 10, wherein one of the oxide structures has a thickness of between 50 and 600 angstroms. The non-volatile memory structure of claim 10, wherein the first sidewall and the second sidewall respectively comprise at least one second oxide layer. The non-volatile memory structure of claim 14, wherein the oxide structure is interposed between the ONO structure and the second oxide layer. The non-volatile memory structure of claim 14, wherein the second sidewall further comprises a second nitride layer formed on the second oxide layer. The non-volatile memory structure of claim 10, further comprising a second LDD disposed in the substrate on both sides of the second gate. The non-volatile memory structure of claim 10, further comprising a first source/drain and a second source/drain, the first source/drain being disposed on the first The substrate is mounted on the substrate on both sides of the gate, and the second source/drain is disposed in the substrate on both sides of the second gate.