1307161 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種非揮發性記憶體（Non_volatileMemory)及其操作 方法，特別是關於一種可於低電壓低消耗電流進行寫入及抹除之低干擾性 之單閘極非揮發性記憶體及其操作方法。 【先前技術】 知：互補式金屬氧化半導體（Complementary Metal Oxide Semiconductor ’ CMOS)製程技術已成為特殊應用積體電路細邮如― specific integrated circuit ’ ASIC)之常用製造方法。在電腦資訊產品 發達的今天’電子式可清除程式化唯軌憶體(Eleetrieally⑹牆 Prograimnable Read Gnly Memory ’ ΕΕΡ_)祕具财躲編冑和抹除資 料之非揮發性記紐功能，且在電源關掉後資料不會敎，所以被廣泛使 用於電子產品上。 其中’非揮紐記倾係為可程式化的，其記憶的原理是_電荷的 儲存以改變記髓之電晶_閘極電壓，或是不麟電荷以留下原記憶體 之電晶體的·電壓。抹除操作収將儲存在非揮發性記憶體中之所有電 何移除’使硝有轉發性記憶體關原記紐之電晶體之閘極電壓。因 此在省知非揮發性記憶體之結構中，操作電壓往往都超過⑺伏特，不作 升’積k成成本的増加’更需要消耗大量電流才能達成升壓後操作的目 的，而且，以先_製簡術生產非揮發性記㈣，往㈣要增加很多首 製程’不但增加了製造_歸，也增加了生產成本，尤其是在嵌入= (embedded)產时，故，目前先進的製程技術，都是往低電壓發展。工 1307161 有鑑於此，本發明係揭示一種 〇〇 操作方法，《_地_咖軸=_輸繼及其 【發明内容】 其摔咐嫩—觀.之單_輸性記憶體及 在==性連接的兩導電閘極以形成單-浮接閘極結構， 偏壓、i τ對源私加—真正有用電屢或對電晶體基底施加-背向 效率’以缝寬之空乏崎各基雜面，進㈣善―浮制極之 效率’以大幅降低程式化單_之非揮發性記憶體的電流需求。 甘本發明之另—目的在於提供-種低干擾性之單_非揮發性記憶體及 /、操作紐，在_構財_底之_用—軒_埋層，使 外界對於電容結構之干擾可降到最低，並且，使導電閘極之起始臨界電壓 可獲得良好的控制。 本發明之再-目的在於提供—種低干擾性之單間極非揮發性記憶體及 其操作方法’藉由升高祕健，並賴極力吐—則售，明加F—N 隧穿電流來進行抹除，以達到高速抹除之功效。 本發明之X-目的在於提供—種低干擾性之單_非揮發性記憶體及 其操作方法’是使用正負壓來相超低操作賴、低操作電流、高可靠度 之功效，且使整體非揮發性記憶體之體積可小型化。 因此’為達上述㈣，本發明所揭露之低干擾性之單閘極非揮發性記 憶體及其操作方法’蘭於單閘極之轉發性記鍾，此單酿之非揮發 性記憶體是在半導縣底巾設有電晶體及電容結構，其巾電晶體包含第一 1307161 導電閘極堆疊在第一介電層表面，第一介電層位於半導體基底上或隔離井 中，且有二高度導電之第一離子摻雜區位於二側來形成源極及汲極丨電容 結構如同電晶體亦形成一像三明治之頂板-介電層_頂板結構，包括有第二 離子摻雜區、第二離子摻雜區埋層、第二介電層與第二導電閘極，且電容 結構之第二導電閉極及電晶體之第一導電閘極係隔離並以電性連接，以形 成非揮發性記《之單浮制極。其中，半導體基底或隔離縣p型，第 ~離子摻雜區與第二離子摻雜區與第二離子換雜區埋層為N型；或者，半 導體基底或_井可為N H軒摻舰與第二離子摻雜與第二離 子摻雜區埋層為P型。. 此單閘極之鱗發性記憶體的低壓操作方法，乃包括施加電壓於源極 或一背向碰(back-blas)於電晶縣紅料化料（或寫人時源極電壓 大於基底輕）’以及升高.箱或抹_賴大於祕電壓）以增 加Μ峨心嶋咐，咖_置，咖觸作賴、 低操作電流。凡_本㈣之方錢單難之非揮發餘髓元件以不同 之結構變化來進行嫌繼_，皆在她之範圍中。 底下藉由具體實施例配合所附_式詳加說明，當更料瞭解本發明 之目的、技術内容、伽及其所軸之功效。 【實施方式】 的剖=圖為本發明之第—實施例所提供的單·之轉發性記憶體結構 低干擾性之單閘極非揮發性 6己憶體結構100包括一 NMOS電晶體1307161 IX. Description of the Invention: [Technical Field] The present invention relates to a non-volatile memory (Non_volatile Memory) and a method of operating the same, and more particularly to a low write and erase low voltage and low current consumption Interfering single-gate non-volatile memory and its operation method. [Prior Art] It is known that Complementary Metal Oxide Semiconductor (CMOS) process technology has become a common manufacturing method for special application integrated circuits such as "specific integrated circuit" ASIC. In today's computer information products developed, 'electronically erasable stylized track-free memory (Eleetrieally (6) wall Prograimnable Read Gnly Memory ' ΕΕΡ _) secrets to hide and erase the non-volatile memory function of the data, and in the power off After the data is not lost, it is widely used in electronic products. The 'non-neutral typology is stylized, and the principle of memory is _ charge storage to change the electro-crystal _ gate voltage of the memory, or the crystal of the original memory. ·Voltage. The erase operation will charge all the power stored in the non-volatile memory, and remove the gate voltage of the transistor that has the reversible memory. Therefore, in the structure of the non-volatile memory, the operating voltage tends to exceed (7) volts, and it is not necessary to increase the cost of the product. It requires a large amount of current to achieve the purpose of post-boost operation, and Simplified production of non-volatile notes (four), to (four) to increase a lot of the first process 'not only increased manufacturing _ return, but also increased production costs, especially in the embedded = (embedded) production, so the current advanced process technology, It is developing towards low voltage. In view of the above, the present invention discloses a method for operating a crucible, "_地_咖 axis=_continuation and its [invention content] its wrestling - view. single_transfer memory and at == The two conductive gates are connected to form a single-floating gate structure, and the bias voltage, i τ is added to the source - the true useful power or the application of the back-plane efficiency to the transistor substrate The base surface, the (four) good - the efficiency of the floating pole 'to greatly reduce the current demand of the stylized single non-volatile memory. Another purpose of the invention is to provide a low-interference single-non-volatile memory and/or operation button, in the _ _ _ _ _ _ _ _ _ buried layer, so that the external interference to the capacitor structure It can be minimized and the starting threshold voltage of the conductive gate can be well controlled. A further object of the present invention is to provide a low-interference single-pole non-volatile memory and its operation method 'by raising the secret and relying heavily on the spit-selling, and adding the F-N tunneling current. Wipe off to achieve high-speed erase. The X-purpose of the present invention is to provide a low-interference single-non-volatile memory and its operation method', which is to use positive and negative pressure to achieve ultra-low operation, low operating current, high reliability, and The volume of the overall non-volatile memory can be miniaturized. Therefore, in order to achieve the above (4), the low-interference single-gate non-volatile memory disclosed in the present invention and the operation method thereof are 'for a single-gate transmissive clock, the single-bulk non-volatile memory is The semi-guided bed towel is provided with a transistor and a capacitor structure, and the towel transistor comprises a first 1307161 conductive gate stacked on the surface of the first dielectric layer, and the first dielectric layer is located on the semiconductor substrate or in the isolation well, and has two The highly conductive first ion doped region is located on both sides to form a source and a drain tantalum capacitor structure. The transistor also forms a sandwich-like top-dielectric layer-top plate structure including a second ion doped region, a second ion doped region buried layer, a second dielectric layer and a second conductive gate, and the second conductive closed electrode of the capacitor structure and the first conductive gate of the transistor are isolated and electrically connected to form a non-volatile Sexual note "The single floating pole. Wherein, the semiconductor substrate or the isolation county p-type, the first-ion doped region and the second ion-doped region and the second ion-exchange region buried layer are N-type; or, the semiconductor substrate or the well may be a NH-Xing ship and The second ion doping and the second ion doped region buried layer are P type. The low-voltage operation method of the single-gate scalar memory includes applying a voltage to the source or a back-blas to the red crystal material of the dianjing county (or the source voltage is greater when the person is written) The base is light) 'and rises. Box or wipe _ _ is greater than the secret voltage) to increase the Μ峨 heart 咖, _ _, coffee touch, low operating current. The non-volatile residual components of the _ _ (4) are difficult to follow with different structural changes, all in her scope. The details of the object, the technical content, the gamma and the axis of the present invention are better understood by the specific embodiments and the accompanying drawings. [Embodiment] FIG. 1 is a single-transfer memory structure provided by the first embodiment of the present invention. The low-interference single-gate non-volatile 6-recall structure 100 includes an NMOS transistor.
1307161 (画晒及-_容__㈣體基㈣中顧晶 體110包含―第—介電層⑴ p W縣請表社，一第一導 電閘極112 4夠—蝴11山，m軒摻隐於P型 半導體基底_，分_其馳113及汲極114，在雜113和祕 114間形成—通道115;N型電容結構120包含-第二離子編埋層124 與-第二離子_ 121分別於P型半導體基底_，_第二介電層⑵ 位於第二離子摻雜_ 124上方且與第二離子摻雜區⑵婦以及一 第二導電_ 123疊設於第二介電層122上方，形成頂板___側底板 之三明治型電容結構。_s電晶體11G之第—導電閘極叫n型電容結 構120之卿„卩第—導電閘極123係以電性連接且以隔轉料138隔離， 形成單浮接閘極⑴〇ating gate)14G之結構。其中，第—離子摻雜區、第 二離子摻祕m與第二離子摻雜埋層124係料N魏子換雜區。 此低干擾性之單閘極非揮發性記憶體結構1〇〇為設有四個端點之結 構’如第2A _示’該四個端點分別為源極、汲極、控制閘極以及基底連 接結構，並於基底130、源極113、及極114、第二離子摻雜區121上分別 施加基底電壓vsub、源極電壓vs、沒極電壓％與控制閉極電壓Vc;第2B圖 為其等效桃。此針擾性之單瞧非揮發性記憶縣構⑽之低電壓操 作過程的條件如下： 寫時： a· Vsub為接地(=〇)。 b· Vd>Vs>0，且 Vc>Vs>0。 ’'叫: 1307161 抹除時： a. Vsub為接地(=0^)。 b· Vd>Vc>Vsg〇〇 知例所提供的單_之非揮發性記憶體結構 第3圖為本發明之第二實 的剖視圖。1307161 (Drawing sun and -_容__(4) Body base (4) Zhong Gu crystal 110 contains "first-dielectric layer (1) p W county please, a first conductive gate 112 4 enough - butterfly 11 mountain, m Xuan The P-type semiconductor substrate _, the sub-113 and the drain 114, form a channel 115 between the impurity 113 and the secret 114; the N-type capacitor structure 120 includes a second ion buried layer 124 and a second ion _ 121 The P-type semiconductor substrate _, the second dielectric layer (2) is located above the second ion doping _ 124 and overlaps the second ion doping region (2) and the second conductive _ 123 on the second dielectric layer 122. Above, the sandwich type capacitor structure of the top plate ___ side plate is formed. The first-type conductive gate of the _s transistor 11G is called the n-type capacitor structure 120. The first-conductive gate 123 is electrically connected and separated. The material 138 is isolated to form a structure of a single floating gate (1) 〇 ating gate 14G, wherein the first ion doping region, the second ion doping m and the second ion doping buried layer 124 are N Weizi replacement regions. The low-interference single-gate non-volatile memory structure 1 is a structure having four end points 'such as 2A_show', the four end points are respectively source a drain electrode, a control gate, and a substrate connection structure, and applying a substrate voltage vsub, a source voltage vs, a gate voltage %, and a control closure on the substrate 130, the source 113, the electrode 114, and the second ion doping region 121, respectively The pole voltage Vc; Fig. 2B is its equivalent peach. The conditions of the low voltage operation process of the single-turn non-volatile memory county (10) of the pin-talking are as follows: When writing: a· Vsub is grounded (=〇). Vd>Vs>0, and Vc>Vs>0. ''Call: 1307161 When erasing: a. Vsub is grounded (=0^). b·Vd>Vc>Vsg〇〇Study provided by _ Non-volatile memory structure Fig. 3 is a second cross-sectional view of the present invention.
P 200 PM〇S 210 - N 雜「* 吟體基底230中，_電晶體2K)之第-離子捧 雜區為P型軒摻純，N^f ' 罨谷、，、。構220之弟二離子摻雜區埋層娜盥第 二離子換腿221咖斷她，且W晴更包括1N I井216 ’而PMOS電晶體21〇之第—導電開極212和N型電容結構挪之 側頂部第一導電閘極223亦以電性連接且以隔離材料挪隔離，形成單浮 接閘極240之結構。 對於低干擾性之單閘極非揮發性記憶體結構咖進行低電壓操作過程 時，是對於基底230、N型井216、源極213、及極214、第二離子推雜區 221上分別施加基底電壓Vsub、N型井電壓"、源極電壓％、祕電壓％ 與控制閘極電壓V。，其條件如下： 寫入時： a· Vsub為接地(=〇)。 b_ Vnwell^Vs>Vd〉0 ’ 且 Vc>Vd>0 0 另外，第4圖為第3圖之抹除架構示意圖，N型井電壓Vn«eli必需大於基 底電壓Vsub ’以防止PMOS電晶體的N型井至P型半導體基底間產生接面順 9 ν «ί:府减私⑽-。 !307161 浮接間極中被抹除。 抹除時： a. Vsub為接地(=〇)，Vc>〇 b. Vtwell^Vs>Vdg〇。 °偏壓，雜制閘極電壓Vc應足夠大以防止舰電晶體打開；該没極電壓 加到等於N型井糕Vnwell ’汲極賴μ於基底電壓l，進而使電荷在單 體結構 第5圖為本發明之第職供的單·之轉發性記憶 的剖視圖。 ,辦擾性之單咖_H±記憶體結構則包括臟電晶體训、N 型電谷結構320及P型井316於N型半導體基底聊中，瞧電晶細 與N型電容結構32G位於p型細表面，且_8電晶議之第—導電 閘極312和N型電容結構32()頂部的第二導電閉極微係以電性連接且以 隔離材料338隔離’而形成—單浮接閉極34()之結構。 對於低干擾性之單閘極非揮發性記憶體結構獅進行抹除及寫入過 程’係於N型半導體基底跏、p型井316、源極⑽、汲極籼與第二離 子摻雜區321上她罐電壓^、p型輸I、祕跑、沒 極電壓Vd與控侧極電麼v"且其低健操作過程的條件如下： 寫入時： a. V触為電源，Vfweu=()。 b. Vd>vs>〇，且 Vc>Vs>〇。 抹除時： 1307161P 200 PM〇S 210 - N Miscellaneous "* 吟 基底 230 230, _ 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 The second ion doped region buried layer Na Na second ion changing leg 221 to break her, and W Qing also includes 1N I well 216 'and PMOS transistor 21 〇 - conductive open pole 212 and N-type capacitor structure The top first conductive gate 223 is also electrically connected and isolated by an isolation material to form a single floating gate 240. For low-interference single-gate non-volatile memory structures during low-voltage operation For the substrate 230, the N-type well 216, the source 213, the pole 214, and the second ion doping region 221, a substrate voltage Vsub, an N-type well voltage, a source voltage %, a secret voltage %, and a control are respectively applied. The gate voltage V., the conditions are as follows: When writing: a· Vsub is grounded (=〇) b_Vnwell^Vs>Vd>0 ' and Vc>Vd>0 0 In addition, Fig. 4 is the third figure To erase the schematic diagram of the architecture, the N-well voltage Vn«eli must be greater than the substrate voltage Vsub' to prevent the junction between the N-well to the P-type semiconductor substrate of the PMOS transistor. ν «ί: 府减私 (10)-. !307161 The floating pole is erased. When erasing: a. Vsub is ground (=〇), Vc> 〇b. Vtwell^Vs>Vdg〇. The miscellaneous gate voltage Vc should be large enough to prevent the ship's transistor from opening; the immersion voltage is added equal to the N-type well cake Vnwell's 汲μμμ to the substrate voltage l, thereby making the charge in the cell structure Figure 5 A cross-sectional view of the forwarding memory of the first job of the present invention. The irritating single coffee _H± memory structure includes a dirty transistor train, an N-type electric valley structure 320, and a P-type well 316 in the N-type. In the semiconductor substrate, the 瞧-electrical fine-grained and N-type capacitor structure 32G is located on the p-type fine surface, and the second conductive closed-pole micro-system at the top of the first-conducting gate 312 and the N-type capacitor structure 32() The structure is electrically connected and isolated by the isolation material 338. The structure of the single floating junction 34 () is used for the erasing and writing process of the low-interference single-gate non-volatile memory structure lion. N-type semiconductor substrate 跏, p-type well 316, source (10), drain 籼 and second ion doped region 321 on her tank voltage ^, p-type input I, secret run, no-pole voltage Vd and the control side of the pole power v" and its low-health operation process conditions are as follows: When writing: a. V-touch is power, Vfweu=(). b. Vd>vs>〇, and Vc>Vs> When erasing: 1307161
a· Vsub 為接電源 ’ Vpwell=0 0 b. Vd>vc>Vs^0。 或者’利用基底背向偏壓(back-bias)程式化： 寫時： a· Vsub 為接電源 ’ Vpwell>〇。 b. Vd>Vs >Vpi»ell>〇，且 Vc>Vs〉Vp*eU>〇。 抹除時： a. VSub為接電源，VpweU為接地(=0)。 b. Vd>Vc>Vs^0〇 上述第1圖之低干擾性之單閘極非揮發性記憶體結構跡係在〜 石夕晶圓上製造而得’隔離結構138係由標準隔離模組製程來完成；2型 基本之隔離結構138之後，在腦s電晶體11G中以離子怖植的方式=形成 道’而在N型電容結賴中則是先於咖晶圓上以離子物成= 離子換雜區埋請後，再以相同的方式形成麵電晶體11G之通道抓 在成長第一導電閘極112、第二導電電_之介電層之後，接著沉積形成 多晶石夕，且以微細進侧化，將多晶判成單浮接閘請；接著， 進行離子佈植以形成_S電晶體11G的源極113、祕114和控制開極等 電極。在金板㈣之單___結構⑽ 之製作。 使用相同製程，第3圖之低千## 4 Μ 低干擾性之早_轉發性記顏結構2〇〇， 1307161 乃藉由在N型井216離子植入以及源極閘極植入區進行不_案化來製 、 帛5圖之低干擾性之單祕轉雜記憶體賴_，係在N型 =圓上以相同製程’且在p型井317及源極，極植人區進行不同圖案化 來凡成在本發明中，上述製程係指-般CMOS之製造流程。 在本發明中’進行程式化時，係施加電壓於低干擾性之單間極非揮發 性記憶體結構的源極，該祕電壓可對於源極及基賴之接面（細⑽） 產生-逆向偏壓’而源極政極間之電位降將允許通道載子從源極移動至 汲極。該職-基細之逆向偏壓更進—倾展至技的接面⑽咖⑽ junction region) ’因而在通道表面附近產生更高濃度的載子密度；在通 道表面附近的錢子密度便提高閘極電流效應，而使程式化所需之總電流 降低。’可靠度、程式化干擾及程式化速度將可制極大改善；相較 於習知未使用源極電壓之技術，閘極電流效率的改善可高達幾百倍。 此外’本發明更可藉由升高祕電壓，並在閘極加上—微小電壓以增 加F-N遂穿電流來進行抹除，以達到高速抹除之功效。 第7圖為本發明之第四實施麵提供的單閘極之轉發性記憶體結構 的剖視圖。低干擾性之單閘極非揮發性記憶體結構侧中乃包括一隔離井 438，其係用以隔離NM0S電晶體與N型電容結構42〇，其中，麵電 晶體410係包括有-第二離子摻雜區埋層似之結構，此第二離子推雜區 埋層424係位於介電層結構的下方，且與第二離子摻雜區42ι相鄰。 由於本發明是使用正貞壓來進—步降低工作絕對籠及錢，因此請 同時參考第7 ®與第8A _示，透過本發_低干舰之單閘極非揮發性 1307161 記憶體結構棚中的六個端點，如帛8A圖所*，該六個端點分別為源極、 汲極、控制閘極、P型井、N型井以及基底，並於p型半導體基底4加、源 極413、汲極414、P型井417、N型井416與第二離子摻雜區421上分別施 加基底電壓Vsub、源極電壓Vs、汲極電壓Vd、P型井電壓VP㈣、N型井電壓 V—與控制閘極電壓Vc ;帛8B圖為其等效電路。此低干擾性之單間極非揮 • 發性記憶體結構400之低電壓操作過程的條件如下： -- 寫時： ® a. vsub為接地(=〇)，以及Vpweu為負壓、Vn灿為正壓。 b. VS>Vpwell，，且 Vc>ys。 抹除時： a. Vsub為接地(=0)，以及Vpweu為負壓、^⑴為正壓。 b· ，且 vs<vd，且 vc>ys。 上述第7圖之結構係在p型石夕晶圓上製造而得，其隔離結構伽係由 •標準隔離模組製程來完成；在形成基本之隔離結構儒之後，N型井416、 P i井417、N型離子摻雜區埋層424以及臓電晶體之通道415係藉 由離子佈植來形成；在成長第一導電閘極412與第二導電閘極似之介電 層之後接著此積形成多晶石夕，且以微影姓刻進行圖案化將多晶石夕形成單 ^斤接閘極_，接著’進行離子佈植以形成舰電晶體410的源極413、 錄414和控制等電極。在金屬化之後，便完成低干擾性之單問極非 揮發性a己憶體結構4QQ之製作。 因此本翻之低干錄之單·轉發性記㈣義作方法，可大 13 1307161 幅降低私式化低干祕之單·轉發性記髓元件之電流需求。並且， 在抹除低干擾性之單間極非揮發性記憶體元件時，間極電壓可相對高於沒 _ 極電壓及電晶體基底電壓，以加速抹除速度。 糾’本發明亦提供一第五實施例，利用施加負電壓於p型井，使得 沒極或閘極絕對電壓於寫入及抹除時變小（低於5V)，來達成低電壓低消耗 -. 電流的操作效果。 翁 第9圖為本發明之第五實施綱提供的單·之轉發性記憶體結構 響的剖視圓。 此低干擾性之單_非揮發性記憶體結構漏包括臟電晶體51〇與 N型電容結構520於p型井517中，其中，在N型電容結構的介電層下 方係形成第二離子摻雜區埋層524,此第二離子捧雜區埋層524係與p型井 5Π相鄰，且上述的p型井517設於N型半導體基底娜上；而_電晶 體510之第-導電閘極51制型電容結構52〇之頂部之第二導電開極诩 _ 係以電14連接且以隔離材料538隔離，形成單浮接閘極54()之結構。 ' 騎第9圖之低干擾性之單閘極非揮發性記憶體結構500進行抹除與 寫入過程’疋在N型半導體基底53〇、源極⑽、没極514、p型井517與 -帛二離子摻雜隨上分別施加-基底電壓Vsub、源極電壓Vs、及極電壓= ‘ P財賴U與控_極電壓ve，並且，其低電壓操作過程的條件如下： 寫入時： a. Vsub為接電源，以及Vpwei|為負壓。 b. Vs>Vpwelln<Vd，Vc>Vs。 1307161 抹除時： 8·· Vsub為接電源’以及V，丨丨為負壓。 b· Vs—Vpwell ’ 且 Vs〈Vd，Vc〉Vs 0 壯所述係藉由實施例說明本發明之特點，其目的在使熟習該技術者 能暸解本發明之内容並據以實施，而非限定本發明之專利範圍，故，凡其 他未雌本發明所揭示之精神所完成之等效修料修改，鶴包含在以; - 所述之申請專利範圍中。 【圖式簡單說明】 第i圖為本發明之第-實_的單_之雜紐記紐麟之剖視圖； 帛2A®為本發明之第—實_之設有四個雜之結構示意圖； 第2B圖為第2A圖結構之等效電路； 第3圖為本發明之第二實施例的單閘極之非揮發性記憶體結構之剖視圖； 第4圖為本發明之第二實施例之抹除架構視示意圖； #帛5圖為本發明之第三實施例的單閘極之非揮發性記㈣結構之剖視圖； - 帛6 _本發明之第三實施例之抹除_視示意圖； .第7 _本發明之第四實施_單_之非揮發性記憶體結構之剖視圖； ‘帛8A®為本發明之細實關之設有六個端點之結構示意圖； 第8B圖為第8A圖結構之等效電路；及 圖為本發月之第五實施例的單閘極之非揮發性記憶體結構之剖視圖。 【主要元件符號說明】 100低干擾性之單閘極非揮發性記憶體結構 1307161a· Vsub is connected to the power supply ’ Vpwell=0 0 b. Vd>vc>Vs^0. Or 'Use the base back-bias to stylize: When writing: a· Vsub is the power supply ' Vpwell> 〇. b. Vd>Vs >Vpi»ell>〇, and Vc>Vs>Vp*eU>〇. When erasing: a. VSub is connected to the power supply, and VpweU is grounded (=0). b. Vd>Vc>Vs^0〇 The low-interference single-gate non-volatile memory structure trace of Figure 1 above is fabricated on ~ Shixi wafers. The isolation structure 138 is a standard isolation module. The process is completed; after the basic isolation structure 138 of the type 2, in the brain s transistor 11G, the method of ion implantation is used to form the track, and in the N-type capacitance connection, the ionic material is formed on the wafer before the wafer. After the ion exchange region is buried, the channel forming the surface transistor 11G in the same manner is grasped after growing the first conductive gate 112 and the second conductive dielectric layer, and then depositing to form polycrystalline stone, Further, the polycrystal is determined to be a single floating gate, and then ion implantation is performed to form the source 113, the secret 114, and the electrode for controlling the opening of the _S transistor 11G. Production of the single ___ structure (10) in the gold plate (4). Using the same process, Figure 3, Low Thousand ## 4 Μ Low Interference Early _ Forwarding Signature Structure 2〇〇, 1307161 is performed by ion implantation in the N-well 216 and source gate implantation Not _ case-based system, 帛5 map of the low-interference single secret transfer memory _, is the same process in the N-type = circle 'and in the p-type well 317 and source, the extremely implanted area Different Patterning In the present invention, the above process refers to a manufacturing process of a general CMOS. In the present invention, when stylizing, a voltage is applied to the source of the low-interference single-pole non-volatile memory structure, and the secret voltage can be generated for the source and the junction (fine (10)). The bias voltage and the potential drop between the source Poles will allow the channel carrier to move from the source to the drain. The reverse bias of the job-base is more advanced - the junction to the technology (10) junction region) - thus producing a higher concentration of carrier density near the surface of the channel; the density of money near the surface of the channel is increased The gate current effect reduces the total current required for stylization. Reliability, stylized interference, and stylized speed can be greatly improved; gate current efficiency can be improved by hundreds of times compared to conventional techniques that do not use source voltage. In addition, the present invention can be erased by increasing the secret voltage and adding a small voltage to the gate to increase the F-N bypass current to achieve high-speed erasing. Fig. 7 is a cross-sectional view showing the structure of a single gate transmissive memory provided in a fourth embodiment of the present invention. The low-interference single-gate non-volatile memory structure side includes an isolation well 438 for isolating the NM0S transistor and the N-type capacitor structure 42〇, wherein the surface transistor 410 includes a second The ion doped region has a buried layer structure, and the second ion doping region buried layer 424 is located below the dielectric layer structure and adjacent to the second ion doping region 42ι. Since the present invention uses positive pressure to further reduce the absolute cost of work, please refer to the 7th and 8th _, through the single-gate non-volatile 1307161 memory structure of the present invention. The six endpoints in the shed, such as the 帛8A diagram*, are the source, the drain, the control gate, the P-well, the N-well, and the substrate, respectively, and are added to the p-type semiconductor substrate 4 The base voltage Vsub, the source voltage Vs, the drain voltage Vd, and the P-well voltage VP (four), N are respectively applied to the source 413, the drain 414, the P-well 417, the N-well 416, and the second ion-doped region 421, respectively. The well voltage V- and the control gate voltage Vc; 帛8B are their equivalent circuits. The conditions of this low-interference single-pole non-volatile memory structure 400 are as follows: -- When writing: ® a. vsub is ground (=〇), and Vpweu is negative, Vn is Positive pressure. b. VS>Vpwell, and Vc>ys. When erasing: a. Vsub is grounded (=0), and Vpweu is negative pressure, and ^(1) is positive pressure. b· , and vs<vd, and vc>ys. The structure of the above Figure 7 is fabricated on a p-type Shi Xi wafer, and the isolation structure is performed by a standard isolation module process; after forming a basic isolation structure, the N-type well 416, P i Well 417, N-type ion doped region buried layer 424 and germanium transistor channel 415 are formed by ion implantation; after growing first conductive gate 412 and second conductive gate like dielectric layer The polycrystalline stone is formed, and the pattern is formed by the lithography, and the polycrystalline stone is formed into a single gate, and then ion implantation is performed to form the source 413 of the ship crystal 410, recording 414 and Control the electrodes. After metallization, the fabrication of a low-interference single-question non-volatile a-recall structure 4QQ is completed. Therefore, the single-transfer (4) method of the low-travel recording can be used to reduce the current demand of the private and low-drying single-transfer-remembering elements. Moreover, when erasing a low-interference single-pole non-volatile memory device, the inter-electrode voltage can be relatively higher than the NMOS voltage and the transistor substrate voltage to accelerate the erasing speed. The invention also provides a fifth embodiment, which uses a negative voltage to apply a negative voltage to the p-type well so that the absolute voltage of the gate or gate becomes smaller (less than 5V) during writing and erasing, thereby achieving low voltage and low consumption. -. The operating effect of the current. Fig. 9 is a cross-sectional view of the single-transfer memory structure of the fifth embodiment of the present invention. The low-interference single-non-volatile memory structure drain includes a dirty transistor 51〇 and an N-type capacitor structure 520 in the p-well 517, wherein a second ion is formed under the dielectric layer of the N-type capacitor structure. The doped region buried layer 524 is adjacent to the p-type well 5 ,, and the p-type well 517 is disposed on the N-type semiconductor substrate Na; and the _ transistor 510 is - The second conductive opening 诩 _ at the top of the conductive gate 51 is formed by electricity 14 and isolated by an isolation material 538 to form a single floating gate 54 (). 'Using the low-interference single-gate non-volatile memory structure 500 of Figure 9 to perform the erasing and writing process' 疋 on the N-type semiconductor substrate 53〇, the source (10), the pole 514, and the p-well 517 - Bismuth ion doping is applied separately - the substrate voltage Vsub, the source voltage Vs, and the pole voltage = 'P' and the voltage ve, and the conditions of the low voltage operation are as follows: : a. Vsub is connected to the power supply, and Vpwei| is the negative voltage. b. Vs > Vpwelln < Vd, Vc > Vs. 1307161 When erasing: 8·· Vsub is connected to power supply 'and V, 丨丨 is negative pressure. b·Vs—Vpwell′ and Vs<Vd, Vc>Vs 0 are described in the following by means of embodiments, the purpose of which is to enable those skilled in the art to understand the present invention and implement it instead of The scope of the invention is defined by the scope of the invention, and the equivalent modification of the invention is not included in the scope of the patent application. [Simple description of the drawing] The i-th picture is a cross-sectional view of the first _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 2B is an equivalent circuit of the structure of FIG. 2A; FIG. 3 is a cross-sectional view showing a non-volatile memory structure of a single gate of the second embodiment of the present invention; FIG. 4 is a second embodiment of the present invention FIG. 5 is a cross-sectional view showing a non-volatile (four) structure of a single gate of a third embodiment of the present invention; - 帛 6 _ a schematic view of a third embodiment of the present invention; Section 7 - a cross-sectional view of a non-volatile memory structure of a fourth embodiment of the present invention - '帛8A® is a schematic diagram of a six-terminal structure of the present invention; FIG. 8B is a 8A is an equivalent circuit of the structure; and a cross-sectional view of the non-volatile memory structure of the single gate of the fifth embodiment of the present month. [Main component symbol description] 100 low-interference single-gate non-volatile memory structure 1307161
110 NMOS電晶體 111 第一介電層 112 第一導電閘極 113 源極 114 汲極 115 通道 120 N型電容結構 121 第二離子摻雜區 122 第二介電層 123 第二導電閘極 124 第二離子摻雜區埋層 130 P型半導體基底 138 隔離材料 140 單浮接閘極 200 低干擾性之單閘極非揮發性記憶體結構 210 PM0S電晶體 212 第一導電閘極 213 源極 214 汲極 216 N型井 220 N型電容結構 16 1307161 221 第二離子摻雜區 223 第二導電閘極 224 第二離子摻雜區埋層 230 P型半導體基底 238 隔離材料 240 單浮接閘極 300 低干擾性之單閘極非揮發性記憶體結構 310 NMOS電晶體 312 第一導電閘極 313 源極 314 汲極 317 P型井 320 N型電容結構 321 第二離子摻雜區 323 第二導電閘極 324 第二離子摻雜區埋層 330 N型半導體基底 338 隔離材料 340 單浮接閘極 400 低干擾性之單閘極非揮發性記憶體結構 410 NMOS電晶體 17 1307161 412 第一導電閘極 413 源極 414 汲極 415 通道 416 N型井 417 P型井 420 N型電容結構 • 421 第二離子摻雜區 423 第二導電閘極 424 第二離子摻雜區埋層 430 P型半導體基底 438 隔離材料 440 單浮接閘極 500 低干擾性之單閘極非揮發性記憶體結構 •510 NMOS電晶體 512 第一導電閘極 . 513 源極 . 514 汲極 517 P型井 520 N型電容結構 521 第二離子摻雜區 ㈣|<路·ante 18 1307161 523 第二導電閘極 524 第二離子摻雜區埋層 530 N型半導體基底 538 隔離材料 540 單浮接閘極110 NMOS transistor 111 first dielectric layer 112 first conductive gate 113 source 114 drain 115 channel 120 N-type capacitor structure 121 second ion doping region 122 second dielectric layer 123 second conductive gate 124 Di-ion doped region buried layer 130 P-type semiconductor substrate 138 Isolation material 140 Single floating gate 200 Low-interference single-gate non-volatile memory structure 210 PM0S transistor 212 First conductive gate 213 Source 214 汲Pole 216 N-well 220 N-type capacitor structure 16 1307161 221 Second ion doped region 223 Second conductive gate 224 Second ion doped region buried layer 230 P-type semiconductor substrate 238 Isolation material 240 Single floating gate 300 Low Interfering single gate non-volatile memory structure 310 NMOS transistor 312 first conductive gate 313 source 314 drain 317 P-well 320 N-type capacitor structure 321 second ion doping region 323 second conductive gate 324 second ion doped region buried layer 330 N type semiconductor substrate 338 isolation material 340 single floating gate 400 low interference single gate non-volatile memory structure 410 NMOS transistor 17 1307161 412 first conductive Pole 413 source 414 drain 415 channel 416 N-well 417 P-well 420 N-type capacitor structure • 421 second ion doped region 423 second conductive gate 424 second ion doped region buried layer 430 P-type semiconductor substrate 438 isolation material 440 single floating gate 500 low-interference single-gate non-volatile memory structure • 510 NMOS transistor 512 first conductive gate. 513 source. 514 bungee 517 P-well 520 N-type capacitor Structure 521 Second Ion Doped Region (4)|<Lu·ante 18 1307161 523 Second Conductive Gate 524 Second Ion Doped Region Buried Layer 530 N-Type Semiconductor Substrate 538 Isolation Material 540 Single Floating Gate