TW200805631A - Single gate nonvolatile memory with low interference and operation method thereof - Google Patents

Abstract

This invention discloses a kind of single gate nonvolatile memory with low interference and an operation method thereof. A semiconductor substrate is embedded with the transistor and capacitor structure, an electro-conductive gate in the transistor and the semiconductor substrate are electrically connected to form a single floating gate of the memory cell, and an ion-doped buried layer structure is formed between a dielectric layer in the capacitor structure and the semiconductor substrate to reduce the interference to the capacitor structure from the external environment and to control the initial threshold voltage. This single gate memory cell can carry out operations like write-in, erasing and reading through the application of back-bias and can generate an inversion layer through the application of positive/negative voltage onto the drain, gate and silicon substrate or well region with the operation of the isolation well region to reduce the absolute voltage, reduce the surface of the boost circuit and achieve the purpose of reducing the electric current consumption.

Description

200805631 IX. Description of the Invention: [Technical Field] The present invention relates to a non-volatile memory (Non-Volatile Memory) and an operation method thereof, and more particularly to a method for writing and erasing at a low voltage and a low current consumption In addition to low interference single gate non-volatile memory and its method of operation. [Prior Art] ... According to Complementary Metal Oxide Semiconductor (CMOS) process technology, it has become a special application integrated circuit (appHcati〇n speC1flc integrated circuit, which is commonly used in manufacturing methods. Today's products are developed, electronically erasable stylized read-only memory (Electrically E dirty this

Programmable Read _ M gift y, Qing _) Because it has a non-volatile record (4) Wei that is electrically written and erased, and the data does not disappear after the electrical measurement, it is widely used in electronic products. · /, towel miscellaneous reading system is programmable, the principle of memory is to use the charge of the age of the _ dragon, or a little charge to set the original memory Body gate voltage. The erase operation is to store all the electricity stored in the non-volatile memory (4) the gate voltage of the transistor of the original memory. Because in the structure of a non-volatile memory, the operating voltage tends to exceed 1 volt, not only the increase in the cost of the product, but also the need to consume a large amount of current to achieve the post-boost operation... 卩 Advanced Process-based production of forwarding memory often requires a lot of entanglement and difficulty in manufacturing, as well as increased production costs, especially in embedded (edded) products; therefore, the current advanced process technology is low Voltage development. In view of this, Benfina reveals that _ while turning the memory and its (4) method to propose an effective solution to the above. SUMMARY OF THE INVENTION The main object of the present invention is to provide a low-interference single-closed non-volatile memory and/or method of operation, which is electrically connected to form a single-floating pole structure. When applying, apply a back bias to the source or the base of the dragon crystal to produce a wider source of the bottom surface of the source, thereby improving the efficiency of current flow to the floating junction. The current demand of the non-swipe. . Another aspect of the present invention is to provide a low-drying single-square memory and a method for its surface-forming a buried layer between the capacitor structure and the bottom of the semi-conducting county, so that the outside world The interference of the capacitor structure can be minimized, and the contact threshold voltage of the conductivity test can be well controlled.

and. A further object of the present invention is to provide a low-interference single-gate non-volatile memory and a ruthenium and a ruthenium method by adding a voltage to the pole and a small voltage to increase the F-N. • _ Wear wire to erase, to achieve the effect of erasing. The purpose of this batch is to provide - the interference of the single. Forwarding memory and • ', operation H is the effect of the system to achieve super-power voltage, low operating current, high reliability, and the overall The volume of non-volatile memory can be miniaturized. Therefore, in order to achieve the above object, the low-interference single-gate non-volatile memory body and the operation method thereof disclosed in the present invention are applied to a single-gate non-volatile memory, and the single-gate non-volatile 5 Remembrance is provided in the semiconductor substrate with a transistor and a capacitor structure, wherein the transistor comprises a first 200805631 interrogating electrode stacked on the surface of the first dielectric layer, the first filament is located on the semiconductor substrate or in the isolation well, and The second highly conductive first-ion doped region is located on both sides to form a source and a finite electrode; the capacitor structure is formed like a transistor - like a top plate of a sandwich - a dielectric layer, and the reverse structure includes a second ion doped region, a buried layer of the second ion doping region, a second dielectric layer and a second conductive gate, and the second conductive idle electrode of the capacitor structure and the first conductive idle electrode of the transistor are isolated and electrically connected to form Single floating gate for non-volatile memory. Wherein, the semiconductor beauty, the - soil & or IVij off-well is p-type, the first-ion doped region and the second ion-doped region and the second ion-doped region are buried in an N-type; or, the semiconductor substrate or isolation The well may be N-type, and the buried layer of the first ion doping region and the second ion doping region and the second ion doping region is p-type. The low-voltage operation method of the single-gate non-volatile memory is to reduce the voltage applied to the source or the back-test (baek-bias is a county red materialization method (or when the source voltage is greater than the substrate) (4) 'Reading _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The single gated non-volatile memory component is programmed and erased with different 'structural changes'. In the scope of the present invention, it is easier to use the specific embodiment with the attached details. The object, technical content, features, and effects achieved by the present invention are understood. Fig. 1 is a cross-sectional view showing the structure of a single-gate transmissive memory provided by the first embodiment of the present invention. The single-gate non-volatile memory structure includes a one-sided transistor 200805631 (NMOSFET) 11O and an N-type capacitor adhered to the 10 Λ 4 120 in the 半导体-type semiconductor substrate 130: the NMOS transistor 110 includes a first dielectric layer 111 P-type semiconductor substrate m surface A first conductive gate 112 is stacked on the first dielectric layer lu and the first ion-ion doped region is located in the p-type semiconductor substrate 130, respectively as & 1,, &, as its source 113 And the drain 114, forming a channel 115 between the source 113 and the gate 115; the N-type capacitor structure includes a second ion doped region buried layer 124 and a second ion doped region 121 respectively on the p-type semiconductor substrate (10) The second dielectric layer (2) is disposed above the second ion doping _ 124 to the second ion doping _ i2i _, and the second paste is disposed above the second dielectric layer 122 to form a top dielectric a sandwich capacitor structure of the layer side substrate. The first conductive gate ι 2 of the germanium transistor 11G and the second conductive idle electrode 123 of the n-type capacitor structure 12 以 are electrically connected and isolated by the isolation material 138 to form a single Floating _ (f loating gate difficult structure m ion doped region, second ion exchange (four) 121 and second ion doping _ 124 material ^ type ion exchange region. This low dry secret single gate forward note (four) structure (10) is a structure with four end points 'as shown in Figure 2A'. The four terminals are source, secret, and control gates respectively. The substrate connection structure 'and the substrate voltage vsub, the source voltage vs, the gate voltage % and the control gate voltage % are respectively known on the substrate 130, the source 113, the drain 114, and the second ion doping region (2); The figure is its equivalent circuit. The low-interference single-gate non-volatile memory structure has the following conditions for low-voltage operation: When writing: a· Vsub is grounded (:=〇) b· Vd>Vs>〇, and Vc>Vs> 0. 200805631 When erasing: a· Vsub is grounded (=r〇). ^b·Vd>Vc>vs-〇 〇 , Fig. 3 is a cross-sectional view showing the structure of a single-pole non-volatile memory provided by the second embodiment of the present invention. The low-interference single-gate non-volatile memory structure 2G0 includes a touch S transistor 210 and a 瘫-type capacitor structure 220-type semi-conductive bottom 230, and the first ion exchange region of the Congdian crystal is a Ρ type In the ion doping region, the second ion doping region of the Ν-type capacitor structure 22 埋 is buried with the second ion doping region 221, and the first ion doping further includes a ν 里 well 216 The first conductive gate 212 of the BIOS device 210 and the top conductive gate 223 of the ν-type capacitor structure 22 are also electrically connected and isolated by the isolation material 238 to form a single floating gate 240. The structure. For a low-interference single-gate non-volatile memory structure 2〇〇, a low-voltage operation process is performed for the substrate 230, the N-type well 216, the source 213, the dipole 214, and the second ion-doped region 221 The upper U-well voltage vnwell, the impurity voltage Vs, the drain voltage Vd and the control gate voltage Vc are respectively applied to the upper surface as follows: When writing: a· Vsub is grounded (=〇). .b· VnweU$Vs>V(J>0, and Vc>Vd>Q. In addition, Figure 4 is a schematic diagram of the erase structure of Figure 3, the N-well voltage ^_ must be greater than the substrate voltage vsub to prevent PMOS The junction between the N-well to the P-type semiconductor filament of the t crystal is biased toward 200805631, and the control gate voltage is applied to the floating gate of the Nn-well voltage Vnweu to be erased. When erasing: 仏 should be sufficient Large to prevent the PM0S transistor from being turned on; the drain voltage 'thortion voltage yd is equal to the substrate voltage Vsub, and thus the charge is grounded (=〇) in a single a·Vsub, 1>〇., b·Vnwell^vs>Vd— 〇 〇 图 & & & & & & & & & & & & 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The capacitor structure 320 and the P-type are thinner than the N-type semiconductor substrate 33, the germanium-electrical fine-grained and N-type capacitor structure 320 is located on the surface of the p-type well 317, and the surface of the transistor is the first conductive gate 312 and the N-type capacitor. The second conductive gate 323 at the top of the structure 32Q is electrically connected and isolated by the isolation material 338. The structure of the single floating gate 34G is formed. • #无低极 non-volatile memory structure 3〇〇 is erased and written, privately connected to N-type semiconductor base coffee, P-type well 316, source 313, drain 314 The substrate voltage Vsub, the P-well voltage Vpwell, the source voltage Vs, the drain voltage Vd, and the control gate voltage Vc are respectively applied to the second and sub-division regions 321, and the conditions of the low voltage operation process are as follows: When writing: a· Vsub is the power supply, v_l=〇. b· Vd>Vs>〇, and Vc>Vs>〇. When erasing: 10 200805631 a· Vsub is connected to the power supply, Vpweu=〇. b· Vd> Vc>Vs^〇0, or, using the base back-bias to stylize:, when writing: a· VSUb is connected to the power supply, vpweU>Q., b. Vd>Vs >Vpweil>〇 And Vc>Vs>VPweU>〇. - When erasing: • a. Vsub is connected to the power supply, Vpweii is grounded (=〇) b. Vd>Vc>Vs^〇〇The low interference of Figure 1 above The single-gate non-volatile memory structure is manufactured on the -p-type Shixi wafer, and the isolation structure 13δ is completed by the standard isolation module process; After the basic isolation structure 138 is formed in the _s transistor 12G by ion implantation, and the N-type capacitor structure 11Q (four) is preceded by the ion wafer with ion cloth _ into = 'ion doping After the buried layer 124 is formed, the channel 115 of the germanium transistor 120 is formed in the same manner; ♦ the long layer of the carbon-first conductive layer (10) and the second conductive electrode 123 are deposited to form a polycrystalline spine and The patterning is performed, and the polycrystals are formed into a single floating junction. Next, ion implantation is performed to form electrodes 113, a drain 114, and a control gate of the _S transistor m. After metallization, the fabrication of a low-interference single-gate non-volatile memory structure (10) is completed. Using the phase, the low-predictive single of the third picture _ turn the key (four) structure ·, 11

2008200805631 is a low-interference single-gate non-volatile memory structure that is made by the different patterns in the (4) well 216 ion implantation and the source-closed implant area. In the present invention, the above process is a manufacturing process in which the n-type _ Μ 以 以 以 以 以 以 以 且 且 且 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 。 。 In the present invention, when stylized, the source of the single-pole non-volatile memory structure of the low-interference is applied, and the hybrid voltage can be generated for the junction of the impurity and the base (the fine ratio (8) is generated-reversely biased Dust, and the potential drop between the source and the secret will allow the channel carrier to move from the source to the immersion. The secret-based fascination extends to the 妓 ( ( ( (4) Thus, a higher concentration of carrier density is produced near the surface of the channel; the density of the shout near the surface of the transport increases the current effect, and the total current required for the remainder is reduced. Therefore, 'reliability, stylized interference, and stylized speed It will be greatly improved; the gate current efficiency can be improved by several hundred times compared to the conventional technique of not using the source voltage.

In addition, the present invention can be erased by increasing the voltage of the immersion voltage and adding a small voltage to the gate to increase the I and F-N 遂 current to achieve high-speed erasing. S Fig. 7 is a cross-sectional view showing the structure of a single closed-pole non-volatile memory provided by the fourth supplement of the present invention. The low-interference single-gate non-volatile memory structure includes an isolation well 438 for isolating the NM〇s transistor and the N-type capacitor structure 42〇, wherein the hidden transistor 410 includes one The second ion doping region has a buried layer structure, and the second ion doping region buried layer 424 is located below the dielectric layer structure and adjacent to the second ion doping region 421. Since the present invention uses positive and negative voltages to further reduce the operating absolute voltage and current, please refer to FIGS. 7 and 8A simultaneously, through the low-interference single-gate non-volatile 200805631 memory of the present invention. The six end points in the structure shed, as shown in Figure 8A, are the source, the immersion, the control gate, the p-well, the N-well, and the substrate, respectively, and are on the p-type semiconductor substrate side. The base voltage Vsub, the secret voltage Vs, the secret voltage Vd, the p-type well voltage v_, and the N-type well voltage are respectively applied to the source 413, the dipole 414, the P-type well 417, the N-type well and the second ion-doped region 421, respectively. V'u and the control pole voltage Vc; 帛8B diagram is its equivalent circuit. The conditions of this low-interference single-polar non-volatile § 己 体 structure 400 low-voltage operation are as follows: When writing: a· Vsub is grounded (=0), and V (four) is negative pressure, vnwell is positive Pressure. b· VS>Vpweli, and Vs<Vd, and . When erasing: a· VSUb is grounded (two turns), and Vpweu is negative pressure, and v(10)(1) is positive pressure. b· Vs-VPwell, and vs<vd, and Vc>Vs. The structure of the above Figure 7 is fabricated on a p-type Shi Xi wafer, and the isolation structure 438 is completed by b-separating her process; after forming the basic isolation structure (10), the n-type well, P-type well 417, the N-type ion doped region buried layer 424 and the channel of the germanium transistor are formed by ion implantation; after growing the first conductive gate and the second conductive gate like the dielectric layer Into more (four), and the engraving of the polycrystalline town into a single ocean gate 440; then, ion implantation to form the surface of the transistor 41 〇 source, recorded 414 and control gate electrodes. After metallization, the fabrication of a low-interference single-closed non-volatile memory structure is completed. Therefore, the low-interference single-gate non-volatile memory operating method of the present invention can reduce the current demand of the single-non-volatile memory component which reduces the stylized low-interference. Moreover, when the low-interference single-gate non-volatile memory component is erased, the closed-pole voltage can be relatively higher than that of the low-voltage, and it depends on the speed of the 1200. The present invention also provides a fifth embodiment, which utilizes the application of a negative voltage to the Ρ-type well so that the immersion or gate is absolutely dependent on the writing and erasing (below 5V) to achieve low voltage and low voltage. Consumption • Current operation effect.帛9 _ The fifth embodiment of the present invention provides a cross-sectional view of a single non-volatile memory structure. The low-interference single-gate non-volatile memory structure 5 (10) includes a career transistor (10) disk N-type capacitor structure 52 〇 in the p-type well 517, wherein the N-type capacitor structure is formed by the dielectric set system a second ion doped region buried layer 524, the second ion doped region buried layer is adjacent to the p-type well 517' and the above-mentioned "well" (four) type semiconductor substrate is on the top and (iv) the first on the transistor 510 - The second conductive idler at the top of the conductive gate 51 is formed electrically connected and isolated by an isolation material 538 to form a structure of a single floating gate $仙. Low interference for Figure 9. The single gate non-volatile memory structure 5 〇〇 is erased and written to process 'on the N-type semiconductor substrate, source 513, gate 514, p-well 517 and * 帛 diion doped region 521 Apply a substrate voltage L, source voltage to the pole voltage ^ P type well voltage % and control electrode voltage [and, the conditions of its low voltage operation process are as follows: When writing: a · VSUb is connected to the power supply, and vPwell is Negative pressure. b_ Vs>Vp眯u ' and vs<yd,vc>vs. 14

200805631 When erasing: a· VSUb is connected to the power supply, and vpwell is negative pressure. b· Vs —Vpweil ' and Vs<Vd 'Vc>Vs 〇 The above description is by way of example (characteristics 'the purpose of which is to enable the skilled person to understand the present invention. (4) full-time, so, where

He has not deviated from the scope of this issue, and is included in the scope of the patent application described below. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a cross-sectional view showing a non-volatile memory structure of a single embodiment of the present invention; FIG. 2A is a schematic structural view showing four terminals of the present invention. 2B is an equivalent circuit of the structure of FIG. 2A; FIG. 3B is a cross-sectional view of the single-gate transmissive memory structure of the second embodiment of the present invention; FIG. 4 is a second embodiment of the present invention; FIG. 5 is a cross-sectional view showing the structure of the hybrid memory of the second embodiment of the present invention; FIG. 6 is a schematic view of the eraser architecture according to the third embodiment of the present invention; A view of the non-volatile memory structure of a single gate of the fourth embodiment of the invention according to the seventh embodiment of the invention. FIG. 8A is a schematic diagram showing the structure of six terminals of the present invention; 8B is an equivalent circuit of the structure of FIG. 8A; and FIG. 9 is a cross-sectional view showing the structure of the single gate non-volatile memory of the fifth embodiment of the present invention. [Main component symbol description] 100 Low-interference single-gate non-volatile memory structure 200805631 110 NM0S transistor 111 First dielectric layer 112 First conductive gate 113 Source 114 Datum 115 Channel 120 N-type capacitor structure

121 second ion doping region 122 second dielectric layer 123 second conductive gate 124 second ion doped region buried layer 130 P type semiconductor substrate 138 isolation material 140 single floating gate 200 low interference single gate Non-volatile memory structure 210 PM0S transistor 212 first conductive gate 213 source 214 drain 216 N-well 220 N-type capacitor structure 200805631 second ion doped region second conductive gate second ion doped region buried Single P-type semiconductor substrate isolation material single floating gate low interference single gate non-volatile memory structure

丽OS transistor first conductive gate source bungee P-well

221 223 224 230 238 240 300 310- 312 313 314 317 320 321 323 324 330 338 340 400 N-type capacitor structure second ion doped region second conductive gate second ion doped region buried layer N-type semiconductor substrate isolation material Single floating gate non-volatile memory structure with single floating gate very low interference 410 NMOS transistor 200805631 412 First conductive gate 413 Source 414 Datum 415 Channel 416 N-well 417 P-well • 420 N-type capacitor Structure 10 421 second ion doping region 423 second conductive gate 424 second ion doped region buried layer 430 P type semiconductor substrate 438 isolation material 440 single floating gate 500 low interference single gate non-volatile memory Body structure 510 NMOS transistor 512 first conductive gate 513 source - 514 drain 517 P-well 520 N-type capacitor structure 521 second ion doped region 18, y.-it - · ΓΛ γ ΐ ^ ^ ^ ^ ;ΐι'Τΐ·ΐ·. - - >-^JaA , Λ·. 200805631 523 second conductive gate 524 second ion doped region buried layer 530 N-type semiconductor substrate 538 isolation material 540 single floating gate

Claims (1)

200805631 X. Patent application scope: 1. A non-volatile memory of a single gate, comprising: a semiconductor substrate; a transistor formed in the semiconductor substrate, the electro-crystalline system comprising: a first medium An electric layer formed on a surface of the semiconductor substrate; a first conductive gate formed over the first dielectric layer; and a plurality of first ion doped regions formed on the first conductive gate The two sides of the semiconductor substrate are formed on the semiconductor substrate, and the capacitor structure comprises: a second dielectric layer formed on the surface of the semiconductor substrate; a second conductive gate formed over the first dielectric layer; a second ion doped region buried layer formed between the second dielectric layer and the semiconductor substrate; a second ion doping region is formed on the second dielectric layer side, and the first conductive closed electrode and the second conductive side electrode are electrically connected to each other as a single floating connection Interpolar. Shen Yue specializes in the single-gate scaly memory described in item 1, wherein the semiconductor substrate is a P-type material substrate or a semiconductor substrate. 3. If the application of the paste coffee 1 of her transmission surface, the first-sub-doping region and the second ion-doping region are mixed with the first type of ions, and the semiconductor substrate is mixed with the second And the first-syntax ion and the second-type ion system are different. 4. If the application special (4) is exported to her ship, wherein the semi-conductive substrate is a P-type semiconductor substrate, the first-ion doped region And the second ion doping region is ^ 200805631 Doped area. Shenyue Patent In, the 3rd lion's single-gate transmissive memory, the semiconductor. The bottom is an N-type semiconductor substrate, the _D-Wei miscellaneous region and the second ion doped region are P W-doped zone. 6. The non-volatile memory of the single gate as described in item i of the patent application, further comprising a third ·-Xin doping, located at the bottom (four) of the Cixian County, below the first-ion doping secret, Moreover, the _ hetero-triion-doped secret system and the second argon-doped region are doped with a simple ion. 7. If the single gate of the single gate is mentioned in the patent, the third ion doped region extends below the buried layer of the second ion doped region. 8. If the single-volume non-volatile journal described in item 7 of the full-time division is applied, an isolation well is disposed in the semiconductor substrate, and the isolation well system and the second ion exchange region are firstly mixed. The ion of the type, the doping of the triion and the ion of the semiconductor group, and the ion of the first type is different from the ion of the second type. φ 9. The non-speaker memory of the single gate according to item 6 of the patent application scope, wherein the semiconductor 'S bottom is the bottom of the N Xianxian County, the second ion doping secret and the third ion heterogeneous region are The p-type is mixed with the zone. 10. The single-gate non-volatile memory according to claim 6, wherein the semiconductor earth bottom is a P-type semiconductor substrate, and the first ion doping region and the third ion doping region are N-type doped area. 11. The single-gate non-volatile memory of claim 1, wherein the second ion doped region is an N+ buried layer. 21 200805631 A single-secret forwarding ship described in claim 1 is characterized in that a first channel structure is formed between the electric crystal and the semiconductor substrate. _ If applying for a single-gate transversal memory as described in the above-mentioned item, construct a trajectory of the semi-conductive bribe, the second channel, the turn, and the structure of the second channel; The second ion doped region is buried. H. The operation method of non-volatile memory, the volatile memory layer comprises a P-type rotating substrate, a transistor and a capacitor structure, and the transistor and the capacitor structure are disposed on the P-type semiconductor substrate The transistor includes a first conductive interpole and a plurality of first ion doped regions 'and the first ion doped regions are on both sides of the first conductive interpole The structure includes a second ion doped region buried layer, a second ion exchange region and a second conductive idle electrode, and the first conductive interlayer is electrically connected to the second conductive interlayer to form a floating connection a gate electrode, the operation method is characterized in that: a substrate electric 昼Vsub, a source electric house Vs, a drain electrode are respectively applied to the P-type semiconductor substrate, the source, the drain and the second ion doping region璧% and a control inter-electrode voltage W, and satisfy the following conditions: · When writing, satisfy vsub as ground; Vd>Vs>〇; and Vc>Vs>〇; and when erasing 'satisfy Vsub is grounded; Vd>Vc>Vs^〇〇15. A method of operating her non-volatile memory, the non- The hair memory system includes a 22 200805631 body substrate, a transistor, a N material and a _ capacitor structure, and the transistor and the electric valley 4 are disposed on the P-type semiconductor substrate, and the transistor includes a -first conductive The gate spot complex number ♦ ion doping 'and (4), the source and the drain are respectively formed on both sides of the thin-guide axis, and the n-type well is disposed under the first ion doping region, and the capacitor structure includes a second ion doped region buried layer, a second ion doped region and a second conductive electrode, and the first conductive gate is electrically connected to the second conductive gate to form a single floating closed end, The method of operation is characterized by: Applying a base voltage Vsub...N type well voltage L, a source voltage %, and a immersion on the P-type semiconductor substrate, the N-type well, the source, the drain, and the second ion exchange region, respectively The voltage Vd and a control gate voltage % satisfy the following conditions: 'When Vsub is grounded; Vnwell —Vs>Vd>0; and Vc>Vd>〇; and Vsub is grounded when erasing; Vc>;0; and VrweU-Vs>Vdg〇. 16. A method for operating a non-volatile memory of a single gate, the non-volatile memory system comprising an N-type semiconductor substrate, a transistor, a P-well, and a capacitor structure, wherein the p-type well is disposed in the N On the semiconductor substrate, the transistor and the capacitor structure are disposed on the surface of the P-type well, the transistor includes a first conductive gate and a plurality of first ion doped regions, and the first ion doped regions are A source and a drain are respectively formed on two sides of the first conductive gate, and the capacitor structure includes a 23 200805631 and the first method of operation is a second ion exchange and a second conductive polarity. The conductive gate is electrically connected to the second conductive gate to form a single floating gate, wherein the N-type semi-conductor bottom, the P-, the _, the pole and the second ion are mixed The substrate voltage Vsub, the -P type well voltage v_, a source voltage %= and the pole voltage Vd and a control gate voltage V are respectively applied to the region. And satisfy the following conditions: · When writing, Vsub is connected to the power supply; Vd>Vs>Vpwell, Vc>Vs>Vpwell, when erasing, Vsub is connected to the power supply; Vc>Vs$Vpweli; and Vd>Vs — Vpweli 0 17. The method of operating a single-gate non-volatile memory according to claim 16, wherein the writing condition satisfies V_g〇. 'The operation method of the single-gate non-volatile memory as described in Item 16 of the application, which is the vPwelg〇. '19. The method for forwarding the singularity as described in claim 16 of the patent application, wherein the erasing condition satisfies Vd > Vc > Vs. 20.- A method for operating a non-volatile memory of a single gate, the non-volatile memory p-type semiconductor substrate, - a transistor, an - N type well, a capacitor structure and a P type well, the i well sighs On the (10) type semiconductor substrate, the p-type well is disposed on the engraved type, and the electric current is disposed on the surface of the P-perimeter. The transistor includes a first-conducting brewing layer and a plurality of first-ion doping regions. And the [Ion doped regions are formed on the two sides of the first conductive gate respectively to form a source and a secret, the capacitor structure comprises a second ion doped region buried layer, a second ion doped region and a Hf gate And the first conductive gate is electrically connected to the second conductive gate to form a single floating gate, and the operation method is characterized by: Applying - substrate voltage Vsub, _ source voltage %, - drain voltage % to the P-type semiconductor substrate, the source, the gate, the p-well, the well and the second ion doping region, respectively P-well voltage vpwell, -N-well voltage and -control gate voltage Vc, and satisfy the following conditions: When writing, satisfy Vc>Vs>V_i;Vd>Vs>Vpwell; Vsub is grounded; and VnweU ^ 〇 And when erasing, satisfy Ve>Vs-VPWeu;Vd>Vs-Vpwell; Vsub is grounded, and Vnwell^O 0 25