1281163 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關一種亦揮發性記憶體（Non-volati le Memory) ’特別是關於一種可於低壓（低於1〇v)抹除之單 閘極之非揮發性記憶體的抹除方法。 …【先前技術】 按互補式金屬氧化半導體（Complementary Metal Oxide Semic〇nductor，CM〇s)製程技術已成為特殊應用積 體電路（application specific integrated circuit， • SIC)之常用製造方法。在電腦資訊產品發達的今天，電 子式可清除程式化唯讀記憶體^丨^化丨⑶丨丨^^”“卜1281163 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a non-volatile memory (Non-volati le Memory), in particular, to a low voltage (less than 1 〇v) erasing. A single gate non-volatile memory erasing method. ... [Prior Art] The Complementary Metal Oxide Semiconductor (CM〇s) process technology has become a common manufacturing method for application specific integrated circuits (SIC). In today's computer information products, electronically-erasable stylized read-only memory ^丨^化丨(3)丨丨^^”
Programmable Read 〇niy Memory，EEpR〇M)由於具備有電 性編寫和抹除資料之非揮發性記憶體功能，且在電源關掉 後貝料不會消失，所以被廣泛使用於電子產品上。 非 以改變 原記憶 揮發性 體回到 發性記 增加一 結構， 曝光顯 _降、工 揮發性記 記憶體之 體之電晶 記憶體中 原記憶體 憶體之結 導電層來 在製程上 影等步驟 時提高， 為可程 的閘極 極電壓 電荷移 體之閘 除了電 荷，而 般 CMOS 成本增 使用於 憶體係 電晶體 體的閘 之所有 之電晶 構中， 儲存電 則比一 ’使得 尤其在 式化的，其係用以儲存電荷 電壓，或不健存電荷以留下 。抹除操作則是將儲存在非 除，使得所有非揮發性記憶 極電壓。因此，在習知非揮 晶體之閘極層外，另需額外 形成雙閘極（d 〇 u b 1 e - 1 a y e f ) 製程多出薄膜沉積、蝕刻及 加、製程複雜、元件良率下 嵌入式（Embedded)EEPR0M 產Programmable Read 〇niy Memory, EEpR〇M) is widely used in electronic products because it has a non-volatile memory function that electrically writes and erases data, and the bead material does not disappear after the power is turned off. In addition to changing the original memory volatility, the structure of the memory is increased, and the structure is exposed, and the conductive layer of the original memory memory in the memory of the body of the memory is recorded in the process. In the step, the gate is increased, and the gate voltage of the gate is replaced by the electric charge, and the CMOS cost is increased in all the electric crystal structures of the gate of the transistor. The storage power is better than the one. It is used to store the charge voltage, or to store the charge to leave. The erase operation will be stored in non-distributed, making all non-volatile memory voltages. Therefore, in addition to the conventional non-volatile crystal gate layer, an additional double gate (d 〇ub 1 e - 1 ayef ) process is required to deposit thin film deposition, etching and addition, complicated process, and embedded under component yield. (Embedded) EEPR0M
第5頁 1281163 五、發明說明（2) 品時更為明顯。 ^習知對於EEPROM元件之抹除方法中，儲存之電荷係 淋=勒-諾得漢（Fowler-Nordheim)隧穿（簡稱F_N隧穿）技 c效應下從浮置閘極移動至電晶體來移除，電壓往 二二^於1〇V ’再由於單閘極ΕΕΜΡ_記憶體之 L fi—浮置閉極1容基底，導致儲存的電荷可依據電 被釋放至任一方向；致使單閉贿_元件 之過度抹除問題變得更嚴重。 【發明内容】 鑒於以上的問題，本發明的主要目的在於提供一 閘極之非揮發性記憶體的抹除方法，其係使用 結構，使得抹除電壓低於10V，並且 / 極及閘極施加電壓，以產生反層 棟除%疋對於沒 抹除完成時則因沒極電壓降“源； = 率’ 防止過度抹除，藉以解決先前技術之=升问而停止，可 因此為達上述目的，本發明所揭露之嚴門托此# 發性記憶體的抹除方法，應用於單閘極之、二鉍^ W結構，“揮ί 電晶體 -汲極；電容結構如同電曰體I:電層—側來形成源極及 苒如π電曰曰體亦形成一三明治結構，包括有 —1^ 第6頁 1281163 五、發明說明（3) 第二離子摻雜區、第-介 構之第二導電閘極層與第二導電閘極，且電容結 連接，並形成4揮發=〗之第—導電閘極係隔離並被電 為p型，第二離非子揮摻發/區^體之單浮接間極；半導體基底 '憶體的抹除方法，^ !井。此單閘極之非揮發性記 .遂穿延伸Ιίΐ;:包Ϊ施加電壓於沒極及閑極以使F-N 方式使非揮發除效能之。凡利用本發明之 作，皆在本發明ΪΠΐ結構變化來進行抹除之操, I沾社二-而°本發明所揭露之單閉極之非揮發性$愔辦 ==之Τ對於由ρ型半導想基底、電晶體：以 非揮發性記憶趙，進行抹除化過程，二 ί 基底、源極”及極與第-離子摻雜區上分別施加 :J電壓、源極電壓、汲極電壓與控制閘極電S 極 閉極電壓’控制間極電壓大於或等於源極電 “、二‘大於或等於基底電壓，基底電壓為接地。 —底下藉由具體實施例配合所附的圖式詳加說明，告更 :易瞭解本發明之目的、技術内容、特點及其所達成：功 b【實施方式】 第1圖為本發明之第一個實施例所提供的單閘極之非 揮發性記憶體結構的剖視圖，單閘極非揮發性記憶體結構 3〇 包括NMOS 電晶體（NMOSFET)32 及N 井（N-well)電容34 ip ，矽基底36中；NMOS電晶體32包含第一介電層32〇位於 >型 1281163 五、發明說明（4) 石夕基底36表面上，第一導電閘極322疊設於該第一介電層 320上方，以及二妒離子摻雜區位於13型矽基底36内，分別 作為其源極324及汲極324，，在源極324和汲極324，間形成 一通道326，·Ν井電容3 4包含第二離子摻雜區於p型矽基底 36内:為其~井34〇，第二介電層342位於|^井34〇表面上， .私及第二導電閘極344疊設於第二介電層342上方，進行形 成頂板-介電層-底板之電容結構。NM〇s電晶體32之第一導 電閘極322和N井電容34之頂部之第二導電閘極344係被電 連接且以一隔離材料38隔離，形成一單浮接閘極 floating gate)40 之結構。 此單閘極非揮發性記憶體結構3〇設有四個端點之結 構，如第2A圖所示，該四個端點分別為源極、汲極、押制 閘極以及基底，並於基底、源極、汲極、第一離子推雜區 上分別施加一基底電壓Vsub、源極電壓\、汲極電壓v 、 制閘極電壓Vc ;第2B圖為其等效電路。此單閘極非揮d發^ 記憶體結構3 0之低汲極電壓抹除化過程的條件如下· a·基底電壓Vsub為接地（=〇);以及 b· Vs - Vsub = 0，且vs < vd。 故，Vd >VC -Vs -Vsub = 〇。 上述第1，之結構係在p型矽晶圓上製邊而得，該隔離 結構38係由標準隔離模組製程來完成；在你 結構38之後’N侧及_電晶體以 子佈植來形成，在成長第一導電閘極322斑 3“之介電層之後’接著沉積形成多晶= 第8頁 1281163 五、發明說明（5) 進行圖案化將多晶梦形成單浮接閘極4 〇 ;接著進行離子 植以形成NMOS電晶體32的源極324、汲極324,和於制間極 廣化之後，便完成許多單閘極非:發性記憶 一綜上所述，本發明乃提出一種單閘極之非揮發性記憮 方法’係對單間極非揮發性記憶體結構施加電 ;ί;(低：10V)及閑極’該閉極電討對於通道下方產 道打開而下降或源極電壓；：m二極電壓會因通 .除化之電壓、，並且解決過；：問止抹除，藉以降低抹 使熟習該技：者：：：:說明本發明之特點，其目的在 定本發明之專解i發明之内容並據以實施，*非限 精神所完成之笪％ & 凡其他未脫離本發明所揭示之 請專利範修飾或修改，仍應包含細下所述之申Page 5 1281163 V. Description of invention (2) The time of the product is more obvious. ^In the EEPROM component erasing method, the stored charge system is transferred from the floating gate to the transistor under the effect of Fowler-Nordheim tunneling (referred to as F_N tunneling). Remove, the voltage goes to 2 2 ^1〇V ' and then because of the single gate ΕΕΜΡ _ memory L fi - floating closed pole 1 capacity substrate, resulting in stored charge can be released in either direction according to electricity; The issue of bribery _ component over-erasing has become more serious. SUMMARY OF THE INVENTION In view of the above problems, the main object of the present invention is to provide a gate non-volatile memory erasing method which uses a structure such that the erase voltage is lower than 10V, and the gate and gate are applied. The voltage is used to generate the reverse layer. In addition, when the completion is not erased, the voltage is reduced because the source has a voltage drop of "source; = rate" to prevent over-erasing, thereby solving the prior art = ascending the problem. The invention discloses a method for erasing the hair memory, which is applied to a single-gate, two-dimensional structure, and the structure of the capacitor is like an electric body I: The electric layer-side forms the source and the π-electrode body also forms a sandwich structure, including -1^ page 6 1281163 5. Description of the invention (3) Second ion doping region, first-media The second conductive gate layer is connected to the second conductive gate, and is connected by a capacitor junction, and forms a fourth volatilization = the first - the conductive gate is isolated and electrically p-type, and the second is separated from the non-spinning/region ^ The single floating junction of the body; the semiconductor substrate 'removal method of the body, ^! well. The non-volatile memory of the single gate is extended to 没ίΐ;: the voltage applied to the immersed and idle poles is such that the F-N mode enables non-volatile removal. Where the use of the present invention is carried out in the present invention, the structure is changed to perform the erasing operation, and the single closed-pole non-volatiles of the present invention are disclosed by ρ. Type semi-conducting substrate, transistor: using non-volatile memory Zhao, the erasing process, two substrates, source and polarity and the first ion doping region are applied: J voltage, source voltage, 汲The pole voltage and the control gate are electrically closed. The gate voltage is greater than or equal to the source voltage, and the second voltage is greater than or equal to the substrate voltage, and the substrate voltage is grounded. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 A cross-sectional view of a single gate non-volatile memory structure provided by one embodiment, a single gate non-volatile memory structure 3 〇 including an NMOS transistor (NMOSFET) 32 and an N-well capacitor 34 ip The first conductive layer 32 is disposed on the surface of the Shishi substrate 36, and the first conductive gate 322 is stacked on the first dielectric layer. Above the electrical layer 320, and the doped ion doping region is located in the 13-type germanium substrate 36, as its source 324 and drain 324, respectively, forming a channel 326 between the source 324 and the drain 324, The capacitor 3 4 includes a second ion doped region in the p-type germanium substrate 36: it is 34 well, the second dielectric layer 342 is located on the surface of the 34 hole, and the second and second conductive gates 344 are stacked. A capacitor structure for forming a top-dielectric layer-base is formed over the second dielectric layer 342. The first conductive gate 322 of the NM〇s transistor 32 and the second conductive gate 344 at the top of the N-well capacitor 34 are electrically connected and isolated by an isolation material 38 to form a floating gate 40. The structure. The single-gate non-volatile memory structure 3〇 has four end structures, as shown in FIG. 2A, the four terminals are a source, a drain, a gate, and a substrate, respectively. A substrate voltage Vsub, a source voltage \, a drain voltage v, and a gate voltage Vc are respectively applied to the substrate, the source, the drain, and the first ion doping region; and FIG. 2B is an equivalent circuit thereof. The conditions of the low gate voltage wiping process of the memory structure of the single gate are as follows: a. The substrate voltage Vsub is grounded (=〇); and b·Vs - Vsub = 0, and vs. < vd. Therefore, Vd >VC -Vs -Vsub = 〇. The first structure described above is obtained by trimming a p-type germanium wafer, and the isolation structure 38 is completed by a standard isolation module process; after the structure 38, the 'N side and the _ transistor are formed by sub-planting. After growing the first conductive gate 322 spot 3 "dielectric layer" followed by deposition to form polycrystalline = page 8 1281163 V. Description of the invention (5) Patterning to form polycrystalline dreams to form a single floating gate 4 〇 Then, ion implantation is performed to form the source 324 and the drain 324 of the NMOS transistor 32, and after the process is extremely broadened, a plurality of single gate non-initiative memories are completed, and the present invention is proposed. A single gate non-volatile recording method 'applies electricity to a single-pole non-volatile memory structure; ί; (low: 10V) and idle pole 'the closed-pole electricity is opened or lowered for the birth channel below the channel Extreme voltage;: m two-pole voltage will be due to pass-through voltage, and solved;: to stop erasing, in order to reduce the wipe to familiarize with the skill::::: Describe the characteristics of the invention, its purpose is Defining the content of the invention of the invention and implementing it according to the principle of *unlimited spirit & Others that do not deviate from the invention disclosed in the patent specification modification or modification, should still include the application described in detail
$ 9頁 1281163 圖式簡單說明 【圖式簡單說明】 第1圖為本發明之第一實施例的單閘極之非揮發性記憶體 結構之剖視圖； 第2 A圖為本發明之第一實施例之設有四個端點之結構示意 】；及 ，2B圖為第2A圖結構之等效電路。 【主要元件符號說明】 30 單閘極非揮發性記憶體結構 #2 NMOS電晶體 320 第一介電層 322 第一導電閘極 324 源極 324, 汲極 326 通道 34 N井電容 340 N井 342 第二介電層 ^44 第二導電閘極 * 6 P型矽基底 38 隔離材料 40 單浮接閘極BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a single-gate non-volatile memory structure according to a first embodiment of the present invention; FIG. 2A is a first embodiment of the present invention For example, the structure of four end points is shown; and, 2B is the equivalent circuit of the structure of FIG. 2A. [Main component symbol description] 30 single gate non-volatile memory structure #2 NMOS transistor 320 first dielectric layer 322 first conductive gate 324 source 324, drain 326 channel 34 N well capacitor 340 N well 342 Second dielectric layer ^ 44 second conductive gate * 6 P type germanium substrate 38 isolation material 40 single floating gate
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