1305123 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種高密度電路板結構之製法，尤指 一種高密度之電路板結構之製法。 【先前技術】 隨著半導體業的高度發展，以及高效能晶片之運算需 要，用以承載晶片之電路板亦需提昇訊號傳遞、改善頻寬 及控制阻抗等功能。然而，為符合半導體封裝件輕薄短小、 夕功此、咼速度及兩頻化的開發方向，該電路板已朝向細 線路及小孔徑發展。現有電路板製程從傳統100微米之線 •路尺寸，包括有導線寬度（Line width)、線路間距（Space) 及深寬比（Aspect ratio)等，已縮減至22微米，並且持續朝 向更小的線路精度發展。 為提高半導體晶片封裝用之電路板之佈線精密度，業 界遂發展出一種增層技術（Built_up)，亦即在一核心板（C(Je 修cuxuit board)表面利用線路增層技術交互堆疊多層介電層 及線路層，並形成有電鍍導通孔（PTH)貫穿該核心板以供 該核心板上下表面之線路之間的電性連接，而該電鍍導通 孔之製程係為影響電路板線路密度的關鍵。 請參閱第1A至10圖，係為習知核心電路板之製法。 如第1A圖所示，提供一例如樹脂壓合銅箔（Resin ⑶以⑶⑶卯〜^^^之具有金屬薄層⑺丨之核芯層丨⑼並 於其中設有複數個核芯層開孔1〇2。 如第1B圖所示，經過鍍銅及圖案化製程以於該核芯 19716 5 1305123 ' * * . 層100之表面上形成線路層1〇3及於該核芯層開孔i们之 孔壁上沈積有金屬層。 如第1C圖所示，復填充一導電或不導電之塞孔材料 11(如塞孔樹脂或含銅導電膏等）以填滿該核芯層開孔⑽ 之殘留空隙’俾形成—電锻導通孔lG2a以電性導通該核芯 層100上下表面之内層線路層1〇3。 如第1D圖所示，再以刷磨製程去除多餘塞孔材料 11，以維持核心電路板線路表面之平整度。 由於該電鍍導通孔102a内需填充塞孔材料u，使該 .電錢V通孔102a必須保持適當的大小方可將該塞孔材料 真入孔中因而使得該核芯層開孔1 〇2之尺寸難以縮 小’進而使該電鍍導通孔1〇2a之間的間距難以縮小，故無 ，於該電路板中製作高密度電料通孔以因應用細線路製 私' 之所需。且該電路板於制·ί呈d? 伋於I私中多了填孔及刷磨製程，如 此即提高電路板製造成本。 _ >第2圖所不者係為另—f知電路板結構之剖面示意 圖。該電路板2上下表面之線路層2q、2i係透過導電盲孔 22電性連接。該導電盲孔22中亦須填充塞孔材料μ，然 由於該盲孔之尺寸限制，塞孔困難，尤其是在電路板2之 厚度大於1〇〇心時，該塞孔材料無法有效填入導電盲孔 中而產生塞孔不良的情況，使該導電盲孔Μ中容易 =留氣泡:此種情形於後續熱循環製財容易產生爆板的 情況，使得電路板結構之可靠度降低。 因此，如何提供一種電路板之製法，以避免習知技術 19716 6 1305123 l 中核心電路板中益法丑彡士、A h 線路、電路拓之;t 電鑛導通孔、無法形成細 失管Π 受到影響、以及製程成本增加等缺 貫已U目前料轉克服之難題。 钱 【發明内容】 供ΐ::知技術之缺點，本發明之主要目的在於提 板結構之製法，得於核4巾形成-體 之導電柱以電性連拉玲k1 ^ ^ h心板上下表面之線路，俾可接弁 導電柱於該核心板中的德< 6 .^ 中的佈έ又岔度，且可應用於細線路製程。 之制太毛月之3目的在於提供一種高密度電路板結構 衣法，得提升電路板之可靠度及電性功能。 之_、车發j之再目的在於提供一種高密度電路板結構 、/、，得降低該電路板結構之製程成本。 处槿述及其他目的，本發明提供—種高密度電路板 :構^法’係包括：提供—具有第—及第二表面之核心 、’於該核心板中形成有至少—貫穿該第—及第二表面 =孔；於該核心板及其開孔處表面形成導電層；於該導 上形成阻層，且於該阻層中形成有複數開口以露出該 厂”及該開口處表面之導電層；以及於該核心 第A第一表面之阻層開口中分別電鍍形成第一及第 j路層’且於該核心板之開孔中形成—體成型之導電 ，並於該導電柱之表面形成接觸墊。 本發明之高密度電路板結構之製法的另一實施例，係 2·提供一具有第一及第二表面之核心板，並於該核心 板中形成有至少-貫穿該第—及第二表面之開孔；於該核 19716 7 13051231305123 IX. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a high-density circuit board structure, and more particularly to a method for manufacturing a high-density circuit board structure. [Prior Art] With the high development of the semiconductor industry and the computing needs of high-performance chips, the circuit board for carrying chips needs to improve signal transmission, improve bandwidth and control impedance. However, in order to meet the development direction of thin and light semiconductor packages, 功 此, 咼 speed and two-frequency, the board has been developed toward thin lines and small apertures. Existing board processes have been reduced to 22 microns from traditional 100 micron lines, including line width, space, and aspect ratio, and continue to face smaller Line accuracy development. In order to improve the wiring precision of the circuit board for semiconductor chip packaging, the industry has developed a layering technology (Built_up), that is, a layer of C (Je repair cuxuit board) surface stacking technology is used to alternately stack multiple layers. The electrical layer and the circuit layer are formed with a plated through hole (PTH) penetrating through the core plate for electrical connection between the lines of the lower surface of the core plate, and the process of the plated via hole is to affect the circuit board line density. Please refer to Figures 1A to 10 for the fabrication of the conventional core circuit board. As shown in Fig. 1A, a resin laminated copper foil (Resin (3) with (3) (3) 卯 ~ ^ ^ ^ has a thin layer of metal. (7) The core layer (9) of the crucible is provided with a plurality of core opening 1 2 in it. As shown in FIG. 1B, a copper plating and patterning process is performed to the core 19716 5 1305123 ' * * . A circuit layer 1〇3 is formed on the surface of the layer 100, and a metal layer is deposited on the hole wall of the core layer opening. As shown in FIG. 1C, a conductive or non-conductive plug material 11 is filled. Such as a plug hole resin or a copper-containing conductive paste, etc.) to fill the core layer opening (10) Residual voids 俾 forming—electrically forged vias 1G2a to electrically conduct the inner wiring layer 1〇3 of the upper and lower surfaces of the core layer 100. As shown in FIG. 1D, the excess plug material is removed by a brushing process 11 In order to maintain the flatness of the surface of the core circuit board. Since the plug hole material 102a needs to be filled with the plug material u, the electric money V through hole 102a must be kept in an appropriate size to allow the plug hole material to enter the hole. Therefore, the size of the core layer opening 1 〇 2 is difficult to be reduced, and thus the spacing between the plated via holes 1 〇 2a is difficult to be reduced, so no, a high-density electric material through hole is formed in the circuit board for application. The need for fine line manufacturing is unique. And the board is made in the system. The hole filling and brushing process is increased in the I private, which increases the manufacturing cost of the board. _ > Figure 2 The circuit layer 2q, 2i of the upper and lower surfaces of the circuit board 2 is electrically connected through the conductive blind hole 22. The conductive blind hole 22 also needs to be filled with the plug material μ. However, due to the size limitation of the blind hole, it is difficult to plug holes, especially in electricity. When the thickness of the plate 2 is greater than 1 〇〇, the plug material cannot be effectively filled into the conductive blind hole and the plug hole is poor, so that the conductive blind hole is easy to be trapped: the bubble is in the subsequent thermal cycle. The production of money is prone to bursting, which reduces the reliability of the circuit board structure. Therefore, how to provide a circuit board method to avoid the ugly ugly, A h in the core circuit board of the prior art 19716 6 1305123 l The line, the circuit extension; t electric mine conduction hole, the inability to form a fine loss of tube Π affected, and the increase in process cost, etc., have been overcome by the current problem. Qian [Invention] Supply:: The shortcomings of knowing technology The main purpose of the present invention is to prepare a plate structure, which is obtained by forming a conductive column of the core 4 towel to electrically connect the line of the lower surface of the core plate, and the conductive column is connected to the core. The cloth in the strip < 6 .^ in the board is twisted and can be applied to the fine line process. The purpose of the system is to provide a high-density circuit board structure, which can improve the reliability and electrical function of the board. The purpose of the vehicle is to provide a high-density circuit board structure, /, to reduce the process cost of the circuit board structure. For a summary and other purposes, the present invention provides a high density circuit board: a method comprising: providing - having a core of a first and a second surface, 'having at least - forming through the core in the core plate" And a second surface=hole; forming a conductive layer on the surface of the core plate and the opening thereof; forming a resist layer on the conductive layer, and forming a plurality of openings in the resist layer to expose the surface of the factory and the opening a conductive layer; and forming a first and a jth layer respectively in the opening of the resistive layer of the first surface of the core A; and forming a body-formed conductive in the opening of the core plate, and the conductive pillar is Forming a contact pad on the surface. Another embodiment of the method for fabricating the high-density circuit board structure of the present invention is to provide a core plate having first and second surfaces, and at least - through the first core plate - and the opening of the second surface; in the core 19716 7 1305123
' -' V 其開孔處：表面形成有第一導電層；於該核心板表 全屬：開孔：之第一導電層上電鍍形成-金屬層，且使該 屬^ ΐ滿5亥開孔；移除該核心板之第一及第二表面之金 覆蓋之第一導電層，留下填充於該開孔中之金 。以形成-填充於該開孔中之導電柱；於該核心板第一 第弟該導電柱外表面形成有-第二導電層；於該 層上分別形成-阻層，且該阻層中具有複數開口 .之二一及第二表面及該導電柱二相對表面 及於該核心板第一及第二表面之阻 曰幵3別電㈣成第-及第二線路層，且於該導電柱 之一相對表面分別形成有接觸墊。 如上述之製法，復包括移除該阻層及其所覆蓋之 而該核心板係為絕緣板，樹職合㈣或具有線路之 電路板；It導電柱係可取代習知之電鐘導通孔（PTH)或導 電目孔―ductive via)，以電性連接該核心板兩表面之線 >路，又於該導電柱之二相對表面分別具有—接觸塾 (ΜΑ，且該二接觸塾係分別電性連接該第-及第二線路 層。 再者該核。板之第、第二表面與第―、第二線路 ^上设可形成-線路增層結構，該線路增層結構係包 ::層、疊置於該介電層上之線路層，以及形成於該介Ϊ 層中之導電結構，且該線路增層結構中之導電結構電 =至該第-及第二線路層；又於該線路增層結構外表面里 有複數電性連接墊，及於該線路增層結構外表面形成有二 19716 8 1305123 * - * , 防焊層，且該防焊層中具有複數防焊層開孔以露出該線路 增層結構之電性連接塾。 因此，本發明之高密度電路板結構之製法，主要係 過電鍍製程於-核心板開孔中直接形成一導電柱，以作爲 該核心板表面之線路層電性連接之用，且無須如習知製程 中於電鍍¥通孔中填充塞孔材料，因而可縮小電錢導通孔 之尺寸’俾可提高該核心板中電鑛導通孔佈設的穷戶，且 ，可應用於細線路製程中’此外，本發明亦無須額外^于埴 孔及刷磨製程，因而可節省製程成本，且可提升電路板之 I靠度，以避免習知採用填孔製程所引起的塞孔材料益法 有效f滿開孔而於電鑛導通孔中殘留氣泡，嚴重影響電路 板可靠度之缺失。 【實施方式】 以下係藉由特定的具體實例說明本發明之實施方 1熟悉此技藝之人士可由本說明書所揭示之内容輕易地 >瞭解本發明之其他優點與功效。 [第一實施例] 請參閱第3A至3C圖、第从至忉圖、第从至讣 圖’係為本發明之高密度電路板結構之製法第一實 剖面示意圖。 之，請先=咖圖’係為核心板表面形成導電層 示’提供_係如雙面之樹脂壓合銅 泊之核心板30，該核心板3〇具有—第一 ^ ^ m 弟表面3如及與該 弟一表面相對之第二表面遍，於該第—表面30a及第二 19716 9 1305123 表面30b具有一金 少一貫穿嗲篦 ：’且於該核心板30中形成有至 一 / 第二表面之開孔3⑼；如第3Β圖所 該核心板3G之第一表面施及第二表面勘的金 屬泊301，並於該第一矣 . 表面3〇a、第一表面30b及開孔300 面30 面*如第3<：圖所示’於該核心板30之第-表 二A面地及開孔300中之表面形成有一導電'-' V at the opening: the surface is formed with a first conductive layer; the core plate is all: open: the first conductive layer is plated to form a metal layer, and the genus is fully opened a hole; removing the gold-covered first conductive layer of the first and second surfaces of the core plate, leaving gold filled in the opening. Forming a conductive pillar filled in the opening; forming a second conductive layer on the outer surface of the conductive pillar of the first core of the core plate; forming a resist layer on the layer, and having a resist layer in the resist layer a plurality of openings, the second surface and the second surface, and the opposite surfaces of the conductive pillars and the first and second surfaces of the core plate are electrically (four) into the first and second circuit layers, and the conductive pillars One of the opposite surfaces is formed with a contact pad. In the above method, the method includes removing the resist layer and covering the core board as an insulating board, a tree joint (4) or a circuit board having a line; and the It conductive pillar system can replace the conventional electric clock via hole ( PTH) or conductive via-ductive via, electrically connecting the two surfaces of the core plate, and the opposite surfaces of the conductive pillar respectively have a contact 塾 (ΜΑ, and the two contact 塾 are respectively Electrically connecting the first and second circuit layers. Further, the core. The first and second surfaces of the board and the first and second lines are provided with a line-forming structure, and the line layering structure is: a layer, a wiring layer stacked on the dielectric layer, and a conductive structure formed in the dielectric layer, and the conductive structure in the wiring build-up structure is electrically connected to the first and second circuit layers; a plurality of electrical connection pads are arranged on the outer surface of the line build-up structure, and two 19716 8 1305123 * - * , solder resist layers are formed on the outer surface of the line build-up structure, and the solder resist layer has a plurality of solder resist layers Opening a hole to expose an electrical connection of the line build-up structure. Therefore, the high density of the present invention The method of manufacturing the circuit board structure mainly comprises forming a conductive pillar directly in the opening of the core plate through the electroplating process, so as to be used as the electrical connection of the circuit layer on the surface of the core plate, and does not need to be electroplated as in the conventional process. The hole is filled with the plug hole material, so that the size of the money guiding hole can be reduced 俾 俾 can improve the poor distribution of the electric ore conducting hole in the core plate, and can be applied in the fine line process 'In addition, the present invention does not need additional ^In the boring and brushing process, the process cost can be saved, and the I-dependence of the circuit board can be improved, so as to avoid the conventional use of the hole-filling process to cause the hole material to be effective. The residual air bubbles in the via hole seriously affect the reliability of the circuit board. [Embodiment] The following is a specific example to explain the implementation of the present invention. Those skilled in the art can easily disclose the contents disclosed in the present specification. Other advantages and effects of the present invention will be understood. [First Embodiment] Referring to Figures 3A to 3C, the drawings from the top to the bottom, and from the drawings to the drawings, the method for manufacturing the high-density circuit board structure of the present invention is described. A real cross-sectional schematic diagram. First, please = 咖图' is to form a conductive layer on the surface of the core board to provide 'provide _ such as double-sided resin laminated copper core core board 30, the core board 3 〇 has - first ^ ^ m The surface 3 of the second surface is opposite to the surface of the younger one, and the surface 30b of the first surface 30a and the second 19716 9 1305123 has a thread of one through: 'and in the core plate 30 Forming an opening 3 (9) to the first/second surface; as shown in FIG. 3, the first surface of the core plate 3G is applied to the second surface of the metal toe 301, and the first surface is 3〇a, A surface 30b and an opening 300 surface 30 are formed as a conductive material on the surface of the first to the second surface of the core plate 30 and the opening 300 as shown in the third <
層33。該導電層33 Φr * A s A 要係了為金屬、合金或沉積數層金 屬層所構成，如選自鋼、雜 钔錫鎳、鉻、鈦、銅-鉻合金或錫 金核構成之群組之其中—者所組成，或可使用例如 ::聚苯胺或有機聚合物等導電高分子材料。 = >閱第4A至4D圖，係為核心板表面形成導電層之 =實&如第4A圖所示，提供一係如表面具有線路之 :路板之核心板31，該核心板31具有一第一表面3u及 -表面相對之第二表面31b，於該第一表面…及 、一表面31b分別壓合一單面樹脂壓合銅箔31丨，該樹脂 壓合銅箱Mi係於-介電層311a之一表面形成有一金屬箱 如第4B圖所示，於該具有樹脂壓合銅箔3 11之該 核匕板31中形成有至少一貫穿之開孔如第π圖所 :私除忒樹脂壓合銅箔311表面的金屬箔3iib，並於該 第表面31a與第二表面31b的介電層31U表面，以及開 =310中形成粗化面；如第4D圖所示，於該核心板31之 第表面3la及第二表面31b的介電層311a，以及開孔310 中之表面形成有一導電層33。 凊參閱第5A至5F圖，如第5A圖所示，提供一係如 10 19716 1305123 • , 絶緣板之核心板32，該核心板32具有一第一表面3仏及 與該第表面相對之第二表面32b之核心板32,且於該核 心板32中形成有至少一貫穿之第一及第二表面之開孔 320 ° 如第5B圖所示，接著，於該核心板32之第一表面 32a、第二表面32b及開孔32〇中之表面形成有一導電層 33以下之貫施即以絕緣板之核心板32為例作說明。 如第5C圖所示，於該核心板32之第一及第二表面 2b之‘電層33上形成有一阻層34。該阻層34可為 Ή如乾膜或液癌光阻之光阻層（ph〇t〇resist)，並可藉由印 刷、紋塗或貼合等方式形成於該導電層33表面，再藉由曝 光、顯影等方式進行圖案化製程，並且形成有複數開口 以外露出該核心板32之第一及第二表面32a、 硭刀之‘電層33以及對應該核心板32之開孔32〇位置的 導電層33。 # 如第5D圖所示’對該核心板32進行電鍍 (Electroplatmg)製程，藉由該導電層33作為電流傳導路 裣以於該核心板32之開孔32〇中一體電鍍形成有一導電 柱35 4於該第一M 32a及第二表面32b上分別電鍍形 成有第線路層35a及第二線路層35b，又於該導電柱％ 之兩表面分別形成有接觸墊351，該接觸墊351係電性連 接5玄第一及第二線路層35a、35b，使該第一及第二線路層 35a、35b藉由該導電柱35而電性連接。 如第5E圖所不，移除該阻層34及其所覆蓋之導電層 19716 11 1305123 33’私除4阻層34及導電層％之技藝係為業界所習知， 故在此不在為文贅述之。 士第5F圖所示，後續復可於依據實際電性設計需要， 於該核心板32、第一娩枚β， Α Α 弟線路層35a及接觸墊351上形成有一 線路增層結構3 6，以芬» « 〇 以及在该核心板32、第二線路層35b 及接觸墊351上开5 + 2 仏 ^ 上小成另一線路增層結構36,，而該線路增 增、、'吉構36、36’在—上卞_ι_ . 係匕括有介電層36卜361，，疊置於該介電 層上之線路層362、1 ^Layer 33. The conductive layer 33 Φr * A s A is composed of a metal, an alloy or a plurality of deposited metal layers, such as a group selected from the group consisting of steel, strontium tin, nickel, chromium, titanium, copper-chromium alloy or tin-gold core. Among them, a conductive polymer material such as polyaniline or an organic polymer may be used. = > Read Figures 4A to 4D, which are formed by forming a conductive layer on the surface of the core board. As shown in Fig. 4A, a core board 31 having a circuit such as a road surface is provided, and the core board 31 is provided. A first surface 3u and a second surface 31b opposite to each other are formed on the first surface and a surface 31b, respectively, and a single-sided resin laminated copper foil 31 is pressed, and the resin-bonded copper box Mi is attached to A metal case is formed on one surface of the dielectric layer 311a. As shown in FIG. 4B, at least one through hole is formed in the core plate 31 having the resin laminated copper foil 3 11 as shown in FIG. The metal foil 3iib on the surface of the copper foil 311 is pressed away by the resin, and the roughened surface is formed on the surface of the dielectric layer 31U of the first surface 31a and the second surface 31b, and in the opening = 310; as shown in FIG. 4D, A conductive layer 33 is formed on the surface of the first surface 31a and the second surface 31b of the core board 31 and the surface of the opening 310. Referring to Figures 5A through 5F, as shown in Figure 5A, a core plate 32 of an insulating plate is provided, such as a first surface 3仏 and a first surface opposite the first surface, such as 10 19716 1305123. a core plate 32 of the second surface 32b, and at least one opening 320° penetrating through the first and second surfaces is formed in the core plate 32, as shown in FIG. 5B, and then on the first surface of the core plate 32. The surface of the 32a, the second surface 32b, and the opening 32 is formed with a conductive layer 33 below, that is, the core plate 32 of the insulating plate is taken as an example. As shown in Fig. 5C, a resist layer 34 is formed on the "electric layer 33" of the first and second surfaces 2b of the core plate 32. The resist layer 34 may be a photoresist layer such as a dry film or a liquid cancer photoresist, and may be formed on the surface of the conductive layer 33 by printing, patterning or laminating, and then borrowed. The patterning process is performed by exposure, development, etc., and the first and second surfaces 32a of the core plate 32, the electric layer 33 of the file, and the opening 32 of the core plate 32 are formed in addition to the plurality of openings. Conductive layer 33. # Electroplating the core plate 32 as shown in FIG. 5D. The conductive layer 33 is used as a current conducting path to integrally form a conductive pillar 35 in the opening 32 of the core plate 32. 4, a first circuit layer 35a and a second circuit layer 35b are respectively formed on the first M 32a and the second surface 32b, and a contact pad 351 is formed on each of the two surfaces of the conductive pillar, and the contact pad 351 is electrically connected. The first and second circuit layers 35a and 35b are connected to each other, and the first and second circuit layers 35a and 35b are electrically connected by the conductive pillars 35. As shown in FIG. 5E, it is known in the industry to remove the resist layer 34 and the conductive layer 19716 11 1305123 33' which is covered by the conductive layer 1916 11 1305123 33'. Describe it. As shown in FIG. 5F, the subsequent re-establishment may be based on the actual electrical design requirements, and a line build-up structure 3 6 is formed on the core board 32, the first delivery layer β, the Α 弟 线路 circuit layer 35a and the contact pad 351. Effort» « 〇 and on the core board 32, the second circuit layer 35b and the contact pad 351 open 5 + 2 仏 ^ on the other line build-up structure 36, and the line increase, 'jiji 36, 36' in the upper layer _ι_ . The system includes a dielectric layer 36 361, the circuit layer 362, 1 ^ stacked on the dielectric layer
362，以及形成於該介電層中之導 結構 363、36V，η # & I 電結構363、363,分別電性連接該 弟線路層35a及笸-怂的a，μ '36 > 365 及弟一線路層35b;又於該線路增層結構 夕表面具有複數電性連接墊364、3 路增層結構36、％，认主 &錢 ,6外表面形成有一防焊層37、37，，且該 .θ 、37’中具有複數防焊層開孔370、370,以露出# 線路增層結構36、36,之電性連接墊364、364，。 “ [弟一實施例] •之^ ^A ^ 61圖所示係為本發明之高密度電路板結構 ,."^ 一實施例之剖面示意圖；得提供一係如前述實施 右^糸如雙面之樹脂壓合銅荡之核心板3〇，或係如表面且 32 =之電=板之核心板3卜或者係如絕緣板之核心板 ，下之貫施係以絕緣板之核心板32為例作說明。 第6A圖，首先，提供一具有第一表面32a及 :了第-表面相對之第二表面32b之核心板32,且於該核 =板32中形成有至少一貫穿第一及第 開孔320。 19716 12 1305123 ,.、 :青參閲第盹圖，接著，於該核心板”之第一表面 3 a第—表面32b及該開孔32Q表面形成有―第—導電層 33“該第一導電層…主要係爲金屬、合金或沉積數層二 屬層：構成二亦可為導電高分子材料所構成。 π參閲第’進行電鍍製程，藉由該第—導電 =作為電流傳導路徑，俾於該第一表面仏及第二表面 成有-金屬層352，並於該開孔3 有一導電柱35。 κ •請參閱第奶圖，移除該核心板32之第一及第1心 的金屬層352及其所覆蓋之第一；電二面 留下填充於該開孔320中之導電柱35。 曰 請參閲第6E圖，於該核心板32 32a、32b及該導電柱35之 及弟一表面 33b，哕篦m 相對表面形成有第二導電層 ^弟一導電層33b主要係爲金屬、合 屬層所構成，亦可為導電高分子材料所構成^儿…金 • 請參閲第6F圖，於該第二導雷展 層34,且該阻層34中形成有複==上形成有-阻 第二表面—及該導電二^ 導電層33b。 一相對表面之部分第二 請參閲第6G圖，進行電鍛製程，藉由 3补作為電流傳導路徑，而在該核 - V電層 面32a、32b之阻層34的開。3 之弟-及第二表 及第二線路層35a、35b，且於該導電刀別電鍍形成有第〜 形成有接觸塾351，並可藉由該導才主35之二表面電鑛 35之接觸墊351以 19716 13 1305123 電性連接該第一及第二線路層35a、35b。 覆蓋之第二導 請參閲第6H圖，移除該阻層34及其所 電層33b。 請參閱第61圖，後續復可於依據實際電性設計需要， 於該核心板32、第一線路層3化及接觸墊351上形:一 路增層結構36,以及在該核心板32、第二線路層说2 觸塾351上形成另一線路增層結構％，，而該線路增層社 構36、36,係包括有介電層361、361，，疊置於該介電曰層。 之線路層362、362’ ’以及形成於該介電層中之導 363、363’，且該導電結構363、3幻，分別電性連接該^一 線路層35a及第二線路層35b;又於該線路增層結構％、 =卜表面具有複數電性連接墊364、364,，於該線路增層 、、、°構36、36,外表面形成有-防焊層37、37，，且該防焊； 37、37,中具有複數防悍層開孔，、37()，以露出該線路^ 層結構36、36,之電性連接墊364、364,。 曰 综上所述，本發明之高密度電路板結構之製法，主 係透過電”程於核心板中形成具有接觸塾之導電桂 5連接該核心板兩表面之第-及第二線路，而無須於電鍍 ^通孔中填充塞孔材料，目而得以縮小電路板層間導電^ 之尺寸，俾可提高該核心板中導電枉佈設的密度，且可 用於細線路製程中；此外，如上所述，本發明無進行填= =刷磨製程’因而可節省製程成本，且可提升電路板之可 ，度以避免習知採用填孔製程所引起的塞孔材料無法 效填滿電料通孔而於電料通孔㈣冑氣泡，嚴重影響 19716 14 1305123 * 丨· , 電路板可靠度之缺失。 之原理及其功效，而 蟄之人士均可在不違 施例進行修飾與改 應如後述之申請專利 上述實施例僅例示性說明本發明 非用於限制本發明。任何熟習此項技 背本發明之精神及範疇下，對上述實 變。因此，本發明之權利保護範圍， 範圍所列。 【圖式簡單說明】362, and the conductive structures 363, 36V, η # & I electrical structures 363, 363 formed in the dielectric layer, respectively electrically connected to the circuit layer 35a and 笸-怂 a, μ '36 > 365 And a circuit layer 35b; and on the surface of the line build-up structure, there are a plurality of electrical connection pads 364, a 3-way build-up structure 36, a %, a main & money, 6 outer surface formed with a solder resist layer 37, 37 And having a plurality of solder mask openings 370, 370 in the .θ, 37' to expose the # line buildup structures 36, 36, the electrical connection pads 364, 364. "[Another embodiment]] ^ ^ A ^ 61 is shown in the high-density circuit board structure of the present invention, a schematic cross-sectional view of an embodiment; The double-sided resin is pressed against the core plate of the copper plate, or is like a surface and 32 = the electric plate of the plate is the core plate of the plate or the core plate of the insulating plate, and the core plate of the insulating plate is applied. 32 is an example. In FIG. 6A, first, a core plate 32 having a first surface 32a and a second surface 32b opposite to the first surface is provided, and at least one through the core plate 32 is formed. The first opening and the opening 320. 19716 12 1305123 , . , : see the second drawing, and then the first surface 3 a of the core plate ” the first surface 32b and the opening 32Q surface is formed with a “first” conductive Layer 33 "the first conductive layer ... is mainly a metal, an alloy or a deposition of two layers of two layers: composition 2 may also be composed of a conductive polymer material. π see the 'electroplating process, by the first conductive = as a current conduction path, the first surface and the second surface are formed with a metal layer 352, and the opening 3 has Conductive column 35. κ • Please refer to the milk map, remove the first and first core metal layer 352 of the core plate 32 and the first cover thereof; the electric two sides remain filled in the opening 320 The conductive column 35. Referring to FIG. 6E, on the core plate 32 32a, 32b and the surface 33b of the conductive column 35, the second conductive layer is formed on the opposite surface of the 哕篦m, and the conductive layer 33b is mainly formed. It is composed of a metal or a conjugate layer, and may also be composed of a conductive polymer material. [Gold] Please refer to FIG. 6F for the second conductive layer 34, and the resist layer 34 is formed with a complex == formed on the second surface - and the conductive second conductive layer 33b. A portion of the opposite surface, please refer to Figure 6G, for the electric forging process, by 3 as the current conduction path, The core-V electrical layer 32a, 32b is formed of a resist layer 34, and the second and second circuit layers 35a and 35b are formed by electroplating, and a contact 塾351 is formed. The first and second circuit layers 35a, 35b can be electrically connected to the contact pads 351 of the surface electrode 35 of the main body 35 bis to 19716 13 1305123. For the second guide, please refer to Figure 6H to remove the resist layer 34 and its electrical layer 33b. Please refer to Figure 61, and the subsequent reconstruction can be based on the actual electrical design requirements, on the core board 32, the first The circuit layer 3 and the contact pad 351 are shaped: a build-up structure 36, and another line build-up structure % is formed on the core plate 32 and the second circuit layer 2, and the line is increased. The structures 36, 36 include dielectric layers 361, 361, stacked on the dielectric layer, circuit layers 362, 362", and leads 363, 363' formed in the dielectric layer, and The conductive structures 363, 3 are electrically connected to the circuit layer 35a and the second circuit layer 35b, respectively; and the surface of the circuit is provided with a plurality of electrical connection pads 364, 364 on the surface. Adding layers, and, 36, 36, the outer surface is formed with - solder resist layers 37, 37, and the solder resist; 37, 37, with a plurality of anti-mite layer openings, 37 () to expose the The circuit layers 36, 36 are electrically connected to the pads 364, 364. In summary, the high-density circuit board structure of the present invention is mainly formed by forming a first-and second-line line connecting the two surfaces of the core board with the conductive ridges 5 in the core board. It is not necessary to fill the plug hole material in the plating hole, thereby reducing the size of the conductive layer between the circuit board layers, and increasing the density of the conductive germanium in the core board, and can be used in the fine line process; The invention does not perform the filling == brushing process, thereby saving the process cost, and improving the availability of the circuit board, so as to avoid the conventional use of the hole-filling process to prevent the plug material from filling the electric material through hole. In the electric material through hole (four) 胄 bubble, seriously affecting 19716 14 1305123 * 丨 ·, the lack of reliability of the circuit board. The principle and its efficacy, and the person who can be modified and modified in accordance with the application example will be described later. The above-mentioned embodiments are merely illustrative of the present invention and are not intended to limit the present invention. Any of the above-described embodiments of the present invention will be described in the spirit and scope of the present invention. Listed around. [Simple description]
第1A至1D圖為習知一 核心電路板之製法之剖面 示意 第2圖係為習知另一電路板結構之剖面示意圖； 第3A至3C圖係為本發明之高密度電路板結構之核心 板表面形成導電層之實施例剖面示意圖； 第4 A至4D圖係為本發明之高密度電路板結構之核心 板表面形成導電層之另一實施例剖面示意圖； 第5A至5F圖係為本發明之高密度電路板結構之製涑 籲第一實施例之剖面示意圖；以及 第6A至61圖係為本發明之高密度電路板結構之製法 第二實施例之剖面示意圖。 【主要元件符號說明】 100 101 l〇2a 102 103 核芯層 金屬薄層 電鍍導通孔 核芯層開孔 線路層 15 19716 1305123 11 基孔材料 2 電路板 20、21、362、362’ 線路層 22 導電盲孔 23 基孔材料 30、31、32 核心板 300、310、320 開孔 301 、 311b 金屬箔 30a、31a、32a 第一表面 30b、31b、32b 第二表面 311a、361、361， 介電層 311 樹脂壓合銅箔 33a 第一導電層 33b 第二導電層 33 導電層 34 阻層 340 開口 351 接觸墊 352 金屬層 35 導電柱 35a 第一線路層 35b 第二線路層 36、36， 線路增層結構 363 、 363， 導電結構 16 19716 1305123 364、364’ 電性連接墊 37、37’ 防焊層 370、370’ 防焊層開孔1A to 1D are cross-sectional views showing a conventional core circuit board. FIG. 2 is a schematic cross-sectional view showing another conventional circuit board structure; FIGS. 3A to 3C are the core of the high-density circuit board structure of the present invention. FIG. 4A to FIG. 4D are cross-sectional views showing another embodiment of forming a conductive layer on the surface of the core plate of the high-density circuit board structure of the present invention; FIGS. 5A to 5F are diagrams of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 6A to FIG. 61 are cross-sectional views showing a second embodiment of a high-density circuit board structure according to the present invention. [Main component symbol description] 100 101 l〇2a 102 103 Core layer metal thin layer plated via core layer Open hole circuit layer 15 19716 1305123 11 Base hole material 2 Circuit board 20, 21, 362, 362' Circuit layer 22 Conductive blind hole 23 base hole material 30, 31, 32 core plate 300, 310, 320 opening 301, 311b metal foil 30a, 31a, 32a first surface 30b, 31b, 32b second surface 311a, 361, 361, dielectric Layer 311 resin laminated copper foil 33a first conductive layer 33b second conductive layer 33 conductive layer 34 resist layer 340 opening 351 contact pad 352 metal layer 35 conductive pillar 35a first wiring layer 35b second wiring layer 36, 36, line increase Layer structure 363, 363, conductive structure 16 19716 1305123 364, 364' electrical connection pad 37, 37' solder resist layer 370, 370' solder mask opening
17 1971617 19716