TW200816890A - Method for fabricating high-density circuit board structure - Google Patents
Method for fabricating high-density circuit board structure Download PDFInfo
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- TW200816890A TW200816890A TW95135926A TW95135926A TW200816890A TW 200816890 A TW200816890 A TW 200816890A TW 95135926 A TW95135926 A TW 95135926A TW 95135926 A TW95135926 A TW 95135926A TW 200816890 A TW200816890 A TW 200816890A
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- layer
- circuit board
- core
- conductive
- core plate
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 19
- 229910000679 solder Inorganic materials 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 239000011347 resin Substances 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 10
- 239000011888 foil Substances 0.000 claims description 8
- 239000011889 copper foil Substances 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 3
- 210000003298 dental enamel Anatomy 0.000 claims 1
- 238000005476 soldering Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 122
- 239000012792 core layer Substances 0.000 abstract description 9
- 238000007747 plating Methods 0.000 abstract description 6
- 239000011799 hole material Substances 0.000 description 36
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 239000010931 gold Substances 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 5
- 230000001680 brushing effect Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229920001940 conductive polymer Polymers 0.000 description 2
- 238000005429 filling process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 241000251468 Actinopterygii Species 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910000599 Cr alloy Inorganic materials 0.000 description 1
- 241000287828 Gallus gallus Species 0.000 description 1
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- GXDVEXJTVGRLNW-UHFFFAOYSA-N [Cr].[Cu] Chemical compound [Cr].[Cu] GXDVEXJTVGRLNW-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000788 chromium alloy Substances 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- XNGIFLGASWRNHJ-UHFFFAOYSA-L phthalate(2-) Chemical compound [O-]C(=O)C1=CC=CC=C1C([O-])=O XNGIFLGASWRNHJ-UHFFFAOYSA-L 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
200816890 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種高密度電路板結構之製法, 一種咼密度之電路板結構之製法。 己‘ 【先前技術】 隨著半導體業的高度發展,以及高效能晶片之運曾$ 要’用以承載晶片之電路板亦需提昇訊號傳遞、改善= 及控制阻抗等功能。然而,為符合半導體封裝件輕薄°短小見 多功能、高速度及高頻化的開發方向,該電路板已朝:細、 線路及小絲發展。現有電路板製程從傳統⑽微米之線 路尺寸,包括有導線寬度(Line Width)、線路間距(Space) 及深寬比(Aspect ratio)等,已縮減至22微米,並且持續朝 向更小的線路精度發展。 、 為提高半導體晶片封裝用之電路板之佈線精密度,業 界遂發展出一種增層技術(Built_up),亦即在一核心板(c〇^ circuit board)表面利用線路增層技術交互堆疊多層介電層 及線路層,並形成有電鍍導通孔(PTH)貫穿該核心板以^ 該核心板上下表面之線路之間的電性連接,而該電鍍導通 孔之製程係為影響電路板線路密度的關鍵。 請麥閱第1A至1D圖,係為習知核心電路板之製法。 如第1A圖所示,提供一例如樹脂壓合銅箔(Resin coated copper,RCC)之具有金屬薄層1〇1之核芯層1〇〇,並 於其中設有複數個核芯層開孔102。 如第1B圖所示,經過鍍銅及圖案化製程以於該核芯 5 19716 200816890 4 、 , 層100之表面上形成線路層1〇3及於該核芯層開孔⑺2之 孔壁上沈積有金屬層。 如第1C圖所示,復填充一導電或不導電之塞孔材料 ιι(如塞孔樹脂或含銅導電膏等)以填滿該核芯層開孔 之殘留空隙,俾形成—電鍍導通孔職以電性導通該核芯 層100上下表面之内層線路層103。 如第1D圖所示,再以刷磨製程去除多餘塞孔材料 11,以維持核心電路板線路表面之平整度。 由於該電鍍導通孔102a内需填充塞孔材料n,使該 電鐘導通孔102a必須保持適當的大小方可將該塞孔材料 11填入孔中’因而使得該核芯層開孔1〇2之尺寸難以 小’進而使該電鍍導通孔102 、 、 Yiuza之間的間距難以縮小,故無 法於口玄電路板中製作局密度電錢導通孔以因應用細線路製 程之所需。且該電路板於製程中多了填孔及刷磨製程,如 此即提高電路板製造成本。 圖。ns rm為另—f知電路板結構之剖面示意 22ΦΛ 下 線路層2〇、21係透過導電盲孔 =電性連接。該導電盲孔22中亦須填充塞孔材料23,狹 ρ 雞尤其疋在電路板2之 异度大於斷m時,該塞孔材料無法有效填入導電盲孔 “中’而產生基孔不良的情況’使該導電盲孔。中容易 $二:此種情形於後續熱循環製程中容易產生爆板的 月况使件電路板結構之可靠度降低。 因此,如何提供-種電路板之製法,以避免習知技術 19716 6 200816890 Z核。電路板中無法形成高密度電鍍 線路、電路板之可靠度受到影響、以及製程成細 失’實已成爲曰5營w θ加專缺 成舄目則業界亟待克服之難題。 【發明内容】 鑒於上述習知技術之缺點, 供-種高密度電路板結構之f法本二:主f:的在於提 之¥電柱以電性連接該核 = 導雷叔协姑分、A丄 I衣® t綠路,俾可提升 : + ;口乂 X心板中的佈設密度,且可應用於細線路f程。 本發明之另—目的在於提供— 之製法,得提升電路板之可靠度及電性功能電路板、、、。構 之2發Γ = 一目的在於提供一種高密度電路板結構 衣去,侍卜低該電路板結構之製程成本。 '结構=述Τ二其:目:’本發明提供一種高密度電路板 板:衣f係包括:提供-具有第-及第二表面之核心 板’並於該核心板中形成右200816890 IX. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a high-density circuit board structure, and a method for manufacturing a circuit board structure of germanium density. 『[Prior Art] With the high development of the semiconductor industry and the high-performance wafers, the boards used to carry the chips also need to improve signal transmission, improvement = and control impedance. However, in order to meet the development trend of thinness, thinness, versatility, high speed and high frequency of semiconductor packages, the board has been developed toward fine, thin wires and small wires. Existing board processes have been reduced to 22 micron from traditional (10) micron line sizes, including Line Width, Space, and Aspect ratio, and continue to be oriented toward smaller line accuracy development of. In order to improve the wiring precision of the circuit board for semiconductor chip packaging, the industry has developed a layering technology (Built_up), that is, using a layer-adding layer to alternately stack multiple layers on the surface of a core board (c〇^ circuit board). The electrical layer and the circuit layer are formed with an electrical connection between the circuit of the core plate and the lower surface of the core plate through a plating via (PTH), and the process of the plating via is to affect the circuit board density. The essential. Please read the 1A to 1D drawings, which is the method of the conventional core circuit board. As shown in FIG. 1A, a core layer 1〇〇 having a thin metal layer 1〇1, such as a resin-coated copper foil (RCC), is provided, and a plurality of core layer openings are provided therein. 102. As shown in FIG. 1B, a copper plating and patterning process is performed to deposit a wiring layer 1〇3 on the surface of the core 5 and a hole wall of the core layer opening (7) 2 on the surface of the core 5 19716 200816890 4 . There is a metal layer. As shown in FIG. 1C, a conductive or non-conductive plug material ιι (such as a plug resin or a copper-containing conductive paste) is filled to fill the residual void of the core layer opening, and the galvanic via is formed. The inner layer circuit layer 103 of the upper and lower surfaces of the core layer 100 is electrically connected. As shown in Fig. 1D, the excess plug material 11 is removed by a brushing process to maintain the flatness of the core circuit board surface. Since the plug hole material 102a needs to be filled with the plug hole material n, the electric clock via hole 102a must be kept in an appropriate size to fill the plug hole material 11 into the hole. Thus, the core layer opening hole 1〇2 The size is difficult to be small, and the spacing between the plated vias 102 and Yiuza is difficult to be reduced. Therefore, it is not possible to fabricate the local density money via holes in the interface board for the application of the fine line process. Moreover, the circuit board has more filling and brushing processes in the process, thereby increasing the manufacturing cost of the circuit board. Figure. Ns rm is another cross-section of the circuit board structure. 22ΦΛ The circuit layer 2〇, 21 is through the conductive blind hole = electrical connection. The conductive blind hole 22 also needs to be filled with the plug hole material 23, and the narrow hole chicken, especially when the circuit board 2 has a different degree of difference than the broken m, the plug hole material cannot be effectively filled into the conductive blind hole "medium" and the base hole is bad. The situation of 'making the conductive blind hole. It is easy to $2: This situation is easy to produce a flashover in the subsequent thermal cycle process. The reliability of the circuit board structure is reduced. Therefore, how to provide a circuit board method In order to avoid the conventional technology 19716 6 200816890 Z core. The high-density electroplating circuit can not be formed in the circuit board, the reliability of the circuit board is affected, and the process becomes fine. It has become a 营5 bat w θ plus special lack of attention In view of the above-mentioned shortcomings of the prior art, in view of the shortcomings of the above-mentioned prior art, a method for providing a high-density circuit board structure is as follows: the main f: is to electrically connect the core to the core. Lei Shu Xiegu, A丄I clothing® t green road, can be improved: +; the density of the layout in the X-ray plate, and can be applied to the fine line f. Another object of the present invention is to provide - System method, to improve the reliability and electrical function of the circuit board The road board, and the structure of the two hairpins = one purpose is to provide a high-density circuit board structure clothing, the low cost of the circuit board structure process. 'Structure = description 2: A high-density circuit board: the clothing f includes: providing a core board having a first and second surface and forming a right in the core board
V 之心,·> W成有至少一貫穿該第一及第二表面 電居:/ S ^"板及其開孔處表面形成導電層;於該導 核心妃加^ 4 |層中形成有稷數開口以露出該 板4为表面及該開口處表導 板之# ο 处衣曲之冷電層,以及於該核心 二線::表面之阻層開口中分別電鍍形成第-及第 桎,二\ ^於5亥核心板之開孔中形成—體成型之導電 亚於該導電柱之表面形成接觸墊。 本,明之高密度電路板結構之製法的另一實施例,係 板中飛出古石,1、 弟—表面之核心板,並於該核心 夕貝牙戎第一及第二表面之開孔;於該核 19716 7 200816890 : = 表面形成有第-導電層;於該核心板表 八麗:中之第一導電層上電鍍形成-金制,且㈣ j層填滿該開孔;移除該核心板之第一及第二表面之全 =及其所覆蓋之第—導電層,留下填充㈣㈣中^ 制以形成-填充於該開孔中之導電柱;於該核心板第一 :導電柱外表面形成有—第二導電層;於該The heart of V, ·> has at least one through the first and second surfaces: /S ^" the surface of the plate and the opening thereof forms a conductive layer; in the layer of the conductive core Forming a plurality of openings to expose the cold-electric layer of the surface of the plate 4 and the surface guide of the opening, and electroplating forming the first and the second in the opening of the core:: Dijon, two ^ ^ formed in the opening of the core plate of the 5th core, the body formed by the conductive sub-surface formed on the surface of the conductive column to form a contact pad. Another embodiment of the method for manufacturing a high-density circuit board structure of the present invention, wherein the core plate is flying out of the ancient stone, the core plate of the surface of the body, and the opening of the first and second surfaces of the core of the core; In the core 19716 7 200816890 : = a conductive layer is formed on the surface; the first conductive layer of the core plate is electroplated to form a gold layer, and (4) the j layer fills the opening; The first and second surfaces of the core plate = and the first conductive layer covered thereby, leaving a filling (4) (4) to form a conductive pillar filled in the opening; the core plate is first: conductive a second conductive layer is formed on the outer surface of the column;
十山’θ 73㈣成—阻層’且該阻層中具有複數開口 心出該心板之第_及第二表面及該導電柱二相對表面 之部分第二導電層;以及於該核心板第一及第二表面之阻 層開口中分職鑛形成第―及第二線路層,且於該導電柱 之二相對表面分別形成有接觸墊。 .如^述之製法,復包括移除該阻層及其所覆蓋之導電 層;而該核心板係為絕緣板,樹脂Μ合銅践具有線路之 電=板;豸導電柱係可取代習知之電鍍導通孔(ρτΗ)或導 電盲孔(conductive via),以電性連接該核心板兩表面之線 路;又於該導電柱之二相對表面分別具有一接觸墊 (land) ’且該二接觸墊係分別電性連接該第一及第二線路 層0 再者,該核心板之第一、第二表面與第一、第二線路 層上復可形成一線路增層結構,該線路增層結構係包括有 介電層、疊置於該介電層上之線路層,以及形成於該介電 層中之導電結構,且該線路增層結構中之導電結構電性連 接至该第一及第二線路層;又於該線路增層結構外表面具 有複數電性連接墊,及於該線路增層結構外表面形成有二 19716 8 200816890 - 、 » 防焊層,且該防焊層中具有複數防焊層開孔以 增層結構之電性連接墊。 '"深路 因此,本發明之高密度電路板結構之製法,主要 過電鍍製程於一核心板開孔中直接形成-導電柱,以作爲 该核心板表面之線路層電性連接之用,且無須如習知 中於電鑛導通孔中填充塞孔材料,因而可縮小電鑛導= 之尺寸,俾可提高該核心板中電鍍導通孔佈設的密度,且 ,可應用於細線路製程中;Λ外,本發明亦無須額外進行填 '孔f刷磨製程,因而可節省製程成本,且可提升電路板之 可靠度,以避免習知採用填孔製程所引起的塞孔材料無法 有效填滿開孔而於電鍍導通孔中殘留氣泡,嚴重 ; 板可靠度之缺失。 〜胃 【實施方式】 以下係藉由特定的具體實例說明本發明之實施方 式,熟悉此技藝之人士可由本說明書所揭示之内容輕易地 t瞭解本發明之其他優點與功效。 [第一實施例]十山'θ 73(四)成—resist layer ′ and the resist layer has a plurality of open cores out of the first and second surfaces of the core plate and a portion of the second conductive layer on the opposite surface of the conductive pillar; and the core plate The first and second surface resistive layer openings are divided into the first and second circuit layers, and the contact pads are respectively formed on the opposite surfaces of the conductive pillars. The method of manufacturing includes removing the resist layer and the conductive layer covered thereby; and the core plate is an insulating plate, and the resin-bonded copper has a circuit of electric=plate; The conductive via (ρτΗ) or the conductive via is electrically connected to the two surfaces of the core board; and the opposite surfaces of the conductive pillar respectively have a contact land and the two contacts The pads are respectively electrically connected to the first and second circuit layers. Further, the first and second surfaces of the core plate and the first and second circuit layers are formed to form a line build-up structure. The structure includes a dielectric layer, a circuit layer stacked on the dielectric layer, and a conductive structure formed in the dielectric layer, and the conductive structure in the circuit build-up structure is electrically connected to the first a second circuit layer; further comprising a plurality of electrical connection pads on the outer surface of the line build-up structure, and a second 19716 8 200816890 - , » solder resist layer formed on the outer surface of the line build-up structure, and having the solder resist layer Multiple solder mask opening to electrically connect the layered structure . Therefore, the method for manufacturing the high-density circuit board structure of the present invention mainly forms a conductive pillar directly in the opening of a core plate through the electroplating process, and serves as an electrical connection for the circuit layer on the surface of the core plate. Moreover, it is not necessary to fill the plug hole material in the electric conduction via hole as in the prior art, thereby reducing the size of the electric ore conductor, and increasing the density of the plating via hole in the core plate, and can be applied to the fine line process. In addition, the present invention does not require additional filling of the 'hole f brushing process, thereby saving process cost and improving the reliability of the circuit board, so as to prevent the plug hole material caused by the hole filling process from being effectively filled. The hole is left in the plated through hole and the bubble is serious; the reliability of the plate is lacking. </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; [First Embodiment]
請參閱第3A至3C圖、第4A至4D圖、第5A至5F 圖,係為本發明之高密度電路板結構之製法第一實施例之 剖面示意圖。 請先參閱第3A至3C圖,係為核心板表面形成導電層 =貝施,如第3A圖所示,提供一係如雙面之樹脂壓合銅 j之核心板30,該核心板30具有一第一表面3〇a及與該 弟一表面相對之第二表面30b,於該第一表面3〇a及第二 19716 9 200816890 * ι« , ^ /、有金屬鑌301,且於該核心板30令形成有至 少一貫穿該篦一芬榮 r〆风有主 -较队 表面之開孔3〇〇;如第3B圖所 不,移除該核心板3〇之筮—本 屬荡3〇1,並於該第—之/面^面地及第二表面鳩的金 中m各、 表面30a、弟二表面30b及開孔300 中开/成粗化面;如第3C圖所示,於該 芦33。及開孔300中之表面形成有一導電 I爲 主要係可為金屬、合金或沉積數層金 〔_鉛人全箄所椹/ ,.°、錫、,臬、鉻、鈦、銅-鉻合金或錫 聚乙口伊二 群組之其中一者所組成,或可使用例如 & ▲來本胺或有機聚合物等導電高分子材料。 二閱第4Α至4D圖’係為核心板表面形成導電層之 另一貫施’如第4Α圖所卡,蔣板一多 電路板之核心fey :獒仏一係如表面具有線路之 鱼兮笔一本板31,§亥核心板31具有一第一表面31a及 第I身而、面相對之第二表面31b,於該第一表面31&及 壓人^ 3lb刀別壓合—單面樹脂壓合銅箱311,該樹脂 3二:於一介電層311&之-表面形成有-金屬箱 •3 i 1 b ’ 如弟4P4同&匕一 圖所不’於該具有樹脂壓合銅箔3 i丨 二中形成有至少一貫穿之開孔31〇;如第4c圖; :'于'㈣脂壓合銅箱311表面的金屬们爪,並於該 ^ Ή = 31a與第二表面311?的介電層311a表面,以及開 …一形成粗化面;如第4D圖所示,於該核心板31之 :表Φ 3la及第二表面Mb的介電層31^,以及開孔⑽ 中之表面形成有一導電層33。 明參閱第5A至5F圖’如第5A圖所示,提供一係如 19716 10 200816890 絕緣板之核心板32,該核心板32具有一第一表面32a及 與該第一表面相對之第二表面32b之核心板&,且於該核 心板32中形成有至少一貫穿之第一及第二表面之開孔 如第5B圖所示,接著,於該核心板32之第一表面 32a、第二表面32b及開孔32〇中之表面形成有一導電層 33。以下之實施即以絕緣板之核心板32為例作說明。曰 f 如第5C圖所示,於該核心板32之第一及 ,H ^ f 33上形Μ 一阻層34 °該阻層^可為 歹,如乾膜或液g光阻之光阻層(phQtQresist),並可夢由 塗或貼合等方式形成於該導電層33表面,㈣由曝 3先4〇顯影等方式進行圖案化製程,並且形成有複數‘ 邱八^出該核心板32之第一及第二表面32a、32b :t :導電層33以及對應該核心板32之開孔320位置的 導電層33。 ^ 如第5〇圖所示,對該核心板32進行電鍍 (Electroplating)製程, 又 徑,以於⑽、“猎由^電層33作為電流傳導路 乂〜板32之開孔32〇中一體電 柱35,並於噠筮一主 奴〜取’ ¥冤 、 表面32a及第二表面32b上分別電鍵形 成有第-線路層35U楚a 上刀心㈣ 及弟一線路層35b,又於該導電柱35 接:第2 Γ形成有接觸墊351,該接觸塾351係電性連 :二:線路層 ^ ^错由該導電柱35而電性連接。 狄圖所不,移除該阻層34及其所覆蓋之導電層 19716 11 200816890 ' 1 1 33,移除遠阻層34及u 久守电層33之技蟄係為業界所 故在此不在為文贅述之。 ’ 如弟5F圖所示,後續復可於依據實際電性設計 於該核心板32、第-線路層35a及接觸墊351上形 線路增層結構36,以及在該核心板32、第二線路層说 :接觸塾351i形成另一線路增層結構 :結構36'36'係包括有介電層3—,要置於該V電 層上之線路層362、369,,、、,ιζ π/ ^ 以及幵>成於該介電層中之導雷 、=構363、363,,且該導電結構如、363,分別電性連接該 弟線路層35a及第二線路層说;又於該線路增層結構 36 /6’外表面具有複數電性連接墊,,及於該線 路增層結構36、36,外表面形成有一防焊層37、”,,且該 防焊層37、37,中具有複數防焊層開孔37()、37(),以露出該 線路增層結構36、36,之電性連接墊364、364,。 [弟一貫施例] 制汝第6A至61圖所示係為本發明之高密度電路板結構 之製法第二實施例之剖面示意圖;得提供一係如前述實施 例之係如雙面之樹脂壓合銅箔之核心板30,或係如表面具 有線路之電路板之核心板31,或者係如絕緣板之核心板 32 ’以下之實施係以絕緣板之核心板32為例作說明。 一明翏閲第6A圖,首先,提供一具有第一表面32a及 ”該第表面相對之第二表面32b之核心板32,且於該核 ^板32中形成有至少一貫穿第一及第二表面32a、32b之 開孔320。 19716 12 200816890 * β · , 請參閲第6B R ^ - 32a、第二表面32/ 者’於S亥核心板32之第一表面 33a。該第-導電芦3;:孔320表面形成有-第-導電層 屬層所構成,亦可'、、,屬、s孟或沉積數層金 嗜夫㈣I "1分子材料所構成。 明多閲弟6C圖,進杆雪你剎 33a作為雷法杨、、, 、又衣程’藉由該第一導電; ha作為電流傳導路徑,俾於該 眾彳电層 32b電鍍形成有— 、面32a及第二表面 ,有-導妹35。層52,並於該開孔咖中電鍍形成 、請參閲第6D圖,移除該核心板3 ❿、32b的金屬層352及其所 :―表面 留下填充於該開孔中 / ¥電層僅 請參閲㈣圖,於該::板柱3325… 32a、32b及該導電柱35之 弟一表面 aau ^ αλ. 和對表面形成有第二暮泰® 33b’該第二導電層33b主要係有弟V电層 屬層所構成,玄 _ 、― σ金或沉積數層金 鸯層所構成’亦可為導電高分子材料所構成。 ()請參閲第好圖,於該第二導電層33bimK == 且層34中形成有複數開。34。以露出該第:、 導電層33br321^5亥導電柱35二相對表面之部分第二 ,、參閲第6G圖’進行電錢製程,藉由該第二導電層 卞為電流傳導路徑’而在該核心板32之 面32a、32b之阻層34的開口 及弟一表 n隻Αώ 叫中刀別電鍍形成有第一 升^層W、3%,且於該導電柱35之二表面電錄 $成有接觸塾川,並可藉由該導電柱35之接觸墊351以 19716 13 200816890 • ». , 電性連接該第一及第二線路層35a、35b。 請參閱第6H圖,移除該阻層34及其所覆蓋之第二導 電層33b。 請參閱第61圖,後續復可於依據實際電性設計需要, 於”亥核〜板32、第一線路層35a及接觸塾351上形成一線 路增層結構36,以及在該核心板32、第二線路層3外及接 觸墊351上形成另一線路增層結構%,,而 構I%’係包括有介電層361、361’,4置於該/電層層。上 、本路層362、362,以及形成於該介電層中之導電結構 363且该導電結構363、363’分別電性連接該第一 線路層35a及第二線路層35b;又於該線路增層結構%、 36,外表面具有複數電性連接塾364、364,,於該線路增声 結構3 6、3 6 ’外矣而其彡士 0 曰 3 ,外表面形成有一防焊層37、37,,且該防焊層 、37’中具有複數防焊層開孔37〇、37〇,以露出該線路增 曰結構36、36,之電性連接墊364、364,。3A to 3C, 4A to 4D, and 5A to 5F are schematic cross-sectional views showing a first embodiment of the method for fabricating a high-density circuit board according to the present invention. Please refer to the figures 3A to 3C for forming a conductive layer=Bei Shi on the surface of the core board. As shown in FIG. 3A, a core board 30 of a double-sided resin-bonded copper j is provided. The core board 30 has a first surface 3〇a and a second surface 30b opposite to the surface of the brother, on the first surface 3〇a and the second 19716 9 200816890 * ι« , ^ /, having a metal 镔 301, and at the core The plate 30 is formed with at least one opening 3〇〇 extending through the surface of the main-comparison team of the 篦一芬荣r 〇〇; as shown in Fig. 3B, removing the core plate 3 筮 本 本 本 本〇1, and the roughened surface is opened/formed in the gold surface m, the surface 30a, the second surface 30b, and the opening 300 of the second surface ; surface and the second surface ;; as shown in FIG. 3C , in the reed 33. And the surface of the opening 300 is formed with a conductive I as a main metal or alloy or a plurality of layers of gold. _ lead, 锡, tin, tin, chrome, titanium, copper-chromium alloy Or one of the group of tin polyethyl phthalate, or a conductive polymer material such as & ▲ to the amine or organic polymer. The second reading of the 4th to 4D drawings is another way to form a conductive layer on the surface of the core board. As shown in Figure 4, the core of the Jiang Banyi circuit board is a fey: a string of fish with a line on the surface. A plate 31, the core plate 31 has a first surface 31a and a first body, and a second surface 31b opposite to the surface, on the first surface 31 & and pressing 3 3 knives - single-sided resin Pressing the copper box 311, the resin 3: on the surface of a dielectric layer 311 & - formed on the surface - metal box • 3 i 1 b ' such as the 4P4 with & a map does not have the resin compression The copper foil 3 i 丨 2 is formed with at least one through hole 31 〇; as shown in Fig. 4c; : '(4) the metal claws on the surface of the (4) grease-bonded copper box 311, and the ^ Ή = 31a and the second The surface of the dielectric layer 311a of the surface 311?, and the surface of the dielectric layer 311a; as shown in Fig. 4D, the dielectric layer 31 of the core plate 31: the surface Φ 3la and the second surface Mb, and the opening A conductive layer 33 is formed on the surface of the hole (10). Referring to Figures 5A through 5F, as shown in Figure 5A, a core panel 32 such as 19716 10 200816890 insulating sheet is provided, the core panel 32 having a first surface 32a and a second surface opposite the first surface a core plate of 32b & and an opening formed in the core plate 32 with at least one of the first and second surfaces extending as shown in FIG. 5B, and then on the first surface 32a of the core plate 32, A conductive layer 33 is formed on the surface of the two surfaces 32b and the openings 32A. The following embodiment is described by taking the core plate 32 of the insulating plate as an example.曰f, as shown in FIG. 5C, on the first and bottom of the core plate 32, a resist layer 34 is formed on the H ^ f 33. The resist layer can be a germanium, such as a dry film or a liquid photoresist. Layer (phQtQresist), and can be formed by coating or laminating on the surface of the conductive layer 33, (4) patterning process by exposure 3, 4 〇 development, etc., and forming a plurality of 'Qiu Ba ^ out the core board The first and second surfaces 32a, 32b of 32: t: a conductive layer 33 and a conductive layer 33 corresponding to the location of the opening 320 of the core plate 32. ^ As shown in Fig. 5, the core plate 32 is subjected to an electroplating process, and the diameter is used to (10), "hunting the electric layer 33 as the current conducting path 板 ~ the opening 32 of the plate 32" The electric column 35 is formed on the first and second main surfaces 32b of the first and second main slaves, and the first circuit layer 35U is formed with a first circuit layer (35) and a second circuit layer 35b. The pillars 35 are connected to each other: the second layer is formed with a contact pad 351, and the contact layer 351 is electrically connected: two: the circuit layer is electrically connected by the conductive pillars 35. The figure is removed, the barrier layer 34 is removed. And the conductive layer 19716 11 200816890 '1 1 33, the technical system for removing the remote resist layer 34 and the u long-term power-storing layer 33 is for the sake of the industry. In the following, the circuit is provided on the core board 32, the first line layer 35a and the contact pad 351 according to the actual electrical design, and the line layer structure 36 is formed on the core board 32 and the second circuit layer: the contact 塾351i Forming another line build-up structure: the structure 36'36' includes a dielectric layer 3 - a circuit layer 362, 369, 、, ζ π / ^ and 幵 > into the dielectric layer of the lightning, = 363, 363, and the conductive structure, such as, 363, respectively, electrically connected to the circuit layer 35a and the second circuit layer; Further, the outer surface of the line build-up structure 36 / 6 ′ has a plurality of electrical connection pads, and the line build-up structures 36 , 36 have a solder resist layer 37 , “ , and the solder resist layer 37 is formed on the outer surface. 37, having a plurality of solder mask openings 37 (), 37 (), to expose the line build-up structures 36, 36, the electrical connection pads 364, 364. [Brief Example] The following is a schematic cross-sectional view showing a second embodiment of the method for manufacturing a high-density circuit board structure according to the present invention; a double-sided resin such as the foregoing embodiment is provided. The core plate 30 of the laminated copper foil, or the core plate 31 of the circuit board having the circuit on the surface, or the core plate 32' such as the insulating plate, is exemplified by the core plate 32 of the insulating plate. Referring to FIG. 6A, firstly, a core plate 32 having a first surface 32a and a second surface 32b opposite to the first surface is provided, and at least one through the first and the second is formed in the core plate 32. The opening 32 of the two surfaces 32a, 32b. 19716 12 200816890 * β · , see the 6B R ^ - 32a, the second surface 32 / the first surface 33a of the S-core core plate 32. The first conductive Lu 3;: The surface of the hole 320 is formed by a layer of a first-conducting layer, and may be composed of ',,, genus, sm or a layer of gold (4) I "1 molecular material. Ming Duo 6C Figure, into the snow, your brakes 33a as Lei Fayang,,, and the clothing process 'by the first conduction; ha as a current conduction path, 俾 该 该 该 该 该 该 该 该 b b b b 该 该 该 该 32 32 32 The two surfaces, there is a guide 35, a layer 52, and is formed by electroplating in the aperture coffee, see Figure 6D, removing the metal layer 352 of the core plate 3, 32b and its: Filled in the opening / ¥ electric layer only please refer to (4) picture, here:: plate column 3325... 32a, 32b and the surface of the conductive column 35 aau ^ αλ. and the formation of the surface The second conductive layer 33b of the second 暮泰® 33b' is mainly composed of a layer of the voltaic layer of the VV, and the 玄 _, ― σ gold or the deposited layer of gold 鸯 layer can also be composed of a conductive polymer material. () Please refer to the first figure, in the second conductive layer 33bimK == and a plurality of openings 34 are formed in the layer 34. To expose the portion of the opposite surface of the conductive layer 33br321^5 Secondly, referring to FIG. 6G, 'the electric money process, the opening of the resist layer 34 on the faces 32a, 32b of the core plate 32 by the second conductive layer 电流 being the current conduction path' Only the middle knives are electroplated to form a first liter layer W, 3%, and the surface of the conductive pillars 35 is electrically recorded with a contact 塾chuan, and can be contacted by the contact pads 351 of the conductive pillars 35. 19716 13 200816890 • ». Electrically connecting the first and second circuit layers 35a, 35b. Referring to Figure 6H, the resist layer 34 and the second conductive layer 33b covered therein are removed. The subsequent complex can be formed on the "Hui core ~ board 32, the first circuit layer 35a and the contact 塾 351 according to the actual electrical design needs. Structure 36, and another line build-up structure % is formed on the core board 32, the second circuit layer 3 and the contact pad 351, and the structure I%' includes a dielectric layer 361, 361', 4 placed The / electrical layer. The upper circuit layer 362, 362, and the conductive structure 363 formed in the dielectric layer, and the conductive structures 363, 363' are electrically connected to the first circuit layer 35a and the second circuit layer 35b, respectively. The build-up structure %, 36, the outer surface has a plurality of electrical connections 塾 364, 364, the outer sound-increasing structure 3 6 , 3 6 ' outside the line and its gentleman 0 曰 3, the outer surface is formed with a solder resist layer 37 37, and the solder resist layer, 37' has a plurality of solder mask openings 37A, 37A to expose the circuit reinforcing structures 36, 36, the electrical connection pads 364, 364.
V 綜上所述,本發明之高密度電路板結構之製法, =透過電鑛製程於核心板中形成具有接觸墊之導電柱以電 性連接該核心板兩表面之第一 導通孔中埴#及弟-線路,而無須於電鍍 之中填充基孔材料,因而得以縮小電路板層間導電柱 二寸’俾可提高該核心板中導電柱佈設的密度,且可應 用於細線路製程中·屮从 , w ^ 肀,此外,如上所述,本發明無進行填孔V In summary, the high-density circuit board structure of the present invention is formed by forming a conductive pillar having a contact pad in the core plate to electrically connect the first via holes of the two surfaces of the core plate through the electro-mine process. And the younger-line, without the need to fill the base material in the plating, thereby reducing the size of the conductive column between the layers of the board, which can increase the density of the conductive pillars in the core board, and can be applied to the fine line process. From, w ^ 肀, in addition, as described above, the present invention is not filled
及刷磨製程,因而可銪么 、L ^ . 了即渴衣耘成本,且可提升電路板之可 :以避免自知採用填孔製程所引起的塞 政填滿電鑛導通孔而於電科通孔中㈣氣泡,嚴重= 19716 14 200816890 電路板可靠度之缺失。 上述實施例僅例示性說明本發明之原理及其工 非用於限制本發明。任何熟習此項技藝之人士均=效,^ 背本發明之精神及料下,對上述實施例進行修:=違 =。因此’本發明之權利保護範圍,應如後述:申^主 範圍所列。 月 【圖式簡單說明】 圖; 第1A至1D圖為習知一核心電路板之製法之剖面示意 第2圖係為習知另一電路板結構之剖面示意圖; 第3A至3C圖係為本發明之高密度電路板結構之核心 板表面形成導電層之實施例剖面示意圖; 第4 A至4D圖係為本發明之高密度電路板結構之核心 板表面形成導電層之另一實施例剖面示意圖; 第5A至5F圖係為本發明之高密度電路板結構之製法 (第一實施例之剖面示意圖;以及 弟6A至61圖係為本發明之高密度電路板結構之製法 第二實施例之剖面示意圖。 【主要元件符號說明】 100 核芯層 101 金屬薄層 102a 電鍍導通孔 102 核芯層開孔 103 線路層 15 19716 200816890And the brushing process, so it can be awkward, L ^. That is the cost of thirsty clothes, and can improve the board: to avoid the self-information caused by the hole filling process to fill the electric mine conduction hole and electricity Coton hole (four) bubble, serious = 19716 14 200816890 The lack of reliability of the board. The above-described embodiments are merely illustrative of the principles of the invention and are not intended to limit the invention. Anyone who is familiar with the art is effective, and the above embodiment is repaired under the spirit of the present invention: = violated =. Therefore, the scope of protection of the present invention should be as described later: the scope of the application. Figure 1A to 1D is a schematic cross-sectional view of a conventional core circuit board. Figure 2 is a schematic cross-sectional view of another conventional circuit board structure; Figures 3A to 3C are FIG. 4A to FIG. 4D are schematic cross-sectional views showing another embodiment of forming a conductive layer on the surface of the core plate of the high-density circuit board structure of the present invention; FIG. 5A to 5F are the manufacturing method of the high-density circuit board structure of the present invention (a schematic sectional view of the first embodiment; and the sixth embodiment of the high-density circuit board structure according to the second embodiment of the present invention) Schematic diagram of the cross section. [Main component symbol description] 100 core layer 101 metal thin layer 102a electroplated via hole 102 core layer opening 103 circuit layer 15 19716 200816890
11 2 20 > 21 ^ 362 > 22 23 30、31、32 300、 310、320 301、 311b 30a、31a、32a 30b、31b、32b 311a、36卜 361 311 33a 33b 33 34 340 351 352 35 35a 35b 36、36, 363 、 363, 塞孔材料 電路板 :’線路層 導電盲孔 基孔材料 核心板 開孔 金屬箔 第一表面 第二表面 介電層 樹脂壓合銅箔 第一導電層 第二導電層 導電層 阻層 開口 接觸墊 金屬層 導電柱 第一線路層 第二線路層 線路增層結構 導電結構 16 19716 200816890 I 1 / 364、364, 37、37, 370 、 370, 電性連接墊 防焊層 防焊層開孔11 2 20 > 21 ^ 362 > 22 23 30, 31, 32 300, 310, 320 301, 311b 30a, 31a, 32a 30b, 31b, 32b 311a, 36 361 311 33a 33b 33 34 340 351 352 35 35a 35b 36, 36, 363, 363, plug hole material circuit board: 'circuit layer conductive blind hole base hole material core plate open hole metal foil first surface second surface dielectric layer resin laminated copper foil first conductive layer second Conductive layer conductive layer resistive layer opening contact pad metal layer conductive column first circuit layer second circuit layer line build-up structure conductive structure 16 19716 200816890 I 1 / 364, 364, 37, 37, 370, 370, electrical connection pad Solder layer solder mask opening
17 1971617 19716
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW95135926A TWI305123B (en) | 2006-09-28 | 2006-09-28 | Method for fabricating high-density circuit board structure |
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| Application Number | Priority Date | Filing Date | Title |
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| TW95135926A TWI305123B (en) | 2006-09-28 | 2006-09-28 | Method for fabricating high-density circuit board structure |
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| TW200816890A true TW200816890A (en) | 2008-04-01 |
| TWI305123B TWI305123B (en) | 2009-01-01 |
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