TWI396265B - Chip package structure and method thereof - Google Patents

Description

Chip package structure and method thereof

The present invention relates to packaging techniques, and more particularly to a wafer package structure and method therefor.

Due to the high speed, multi-function, high capacity, and light, thin, short, and small requirements of the user, the mounting density of the semiconductor element is becoming higher and higher. In general, the basic chip package structure includes at least: a substrate; at least one wafer is disposed thereon and electrically connected to the substrate; and a packaging material covers the wafer, the electrical connection structure and a portion of the substrate. In the field of packaging, how to reduce process steps, reduce costs and improve package integration is an endless goal and an important issue.

In order to solve the above problems, an object of the present invention is to provide a chip package structure and method thereof, which package an entire package by using a film instead of the original substrate and the package material.

One of the objects of the present invention is to provide a chip package structure and a method thereof for sealing a wafer to two films by a film, which is simple in packaging method and can effectively prevent foreign matter from affecting the wafer.

In order to achieve the above object, a chip package structure according to an embodiment of the present invention includes: a first adhesive film having a plurality of inner contacts on an upper surface and a plurality of external contacts on a lower surface, wherein the inner contacts are The external contacts are electrically connected; at least one wafer is disposed on the upper surface of the first adhesive film and electrically connected to the inner contact; a second adhesive film covers the wafer and forms a closed film with the first adhesive film The space accommodates the wafer; and the plurality of conductive solder balls are disposed on the external contacts.

A chip packaging method according to another embodiment of the present invention includes the following steps: providing a first film, wherein the first film has a plurality of inner contacts on an upper surface and a plurality of external contacts on the lower surface, and The inner contact is electrically connected to the external contact; at least one wafer is disposed on the upper surface of the first adhesive film and the wafer is electrically connected to the inner contact; a plurality of conductive solder balls are disposed on the external contact; and a second adhesive is disposed The film is on the wafer; and the excess first film and the second film are removed by a stamping step and the first film is joined to the second film to form a closed space to accommodate the wafer.

Referring to FIG. 1E, in the embodiment, the chip package structure includes: a first film 10; at least one wafer 20; a second film 40; and a plurality of conductive solder balls 30. The first adhesive film 10 has a plurality of inner contacts 12 on an upper surface and a plurality of external contacts 14 on the lower surface, wherein the inner contacts 12 and the external contacts 14 are electrically connected. The wafer 20 is disposed on the upper surface of the first adhesive film 10 and electrically connected to the inner contact 12 . The second adhesive film 40 covers the wafer 20 and forms a closed space accommodating wafer 20 with the first adhesive film 10. The conductive solder balls 30 are disposed on the external contacts 14.

In one embodiment, the inner contact 12 and the outer contact 14 are electrically connected to each other by a metal line (not shown) of the first adhesive film 10. In one embodiment, the wafer 20 has a plurality of copper bumps (not shown) electrically connected to the inner contacts 12. In one embodiment, the wafer package structure can be provided with a plurality of wafers 20. In one embodiment, the wafers 20 can be stacked one on another as shown in FIG. In one embodiment, the wafers 20 can also be arranged side by side (not shown).

Referring to FIG. 1A, FIG. 1B, FIG. 1C, FIG. 1D and FIG. 1E, the wafer packaging method in the embodiment includes the following steps. As shown in FIG. 1A, a first film 10 is provided, wherein the first film 10 has a plurality of inner contacts 12 on an upper surface and a plurality of external contacts 14 on the lower surface, and the inner contacts 12 and the external contacts 14 series electrical connection. At least one wafer 20 is disposed on the upper surface of the first adhesive film 10 and electrically connects the wafer 20 to the internal contacts 12, as shown in FIG. 1B. The wafer 20 can be electrically connected to the inner contact 12 by a plurality of copper bumps (not shown). Referring to FIG. 1C, a plurality of conductive solder balls 30 are disposed on the external contacts 14. A second film 40 is disposed on the wafer 20 and the excess first film 10 and the second film 40 are removed by a stamping step. The first film 10 is joined to the second film 40 to form a closed space for accommodating the wafer 20, as shown in FIGS. 1D and 1E.

In an embodiment, a heating step may be simultaneously provided to assist the first film 10 to be connected to the second film 40. In various embodiments, a plurality of wafers 20 are stacked one on another (as shown in Figure 2) or side by side. In one embodiment, the stacked wafers 20 can be electrically connected using a through-silicon via (TSV) technique.

The invention adopts a film as the core of the whole packaging technology, and combines and segments by means of a punch. The use of the film of the present invention utilizes existing tape winding techniques. Whether the film covering the wafer is sticky is not a major requirement, and it is only necessary to isolate the foreign matter. If it is necessary to avoid excessive change of the film in the thermal expansion and contraction environment, it is possible to increase the fine pores in the film to reduce the expansion phenomenon to avoid the film breakage.

In summary, the present invention encapsulates the entire package by replacing the original substrate and the packaging material with a film; sealing the wafer into the two films by the film, the packaging method is simple and can effectively prevent foreign matter from affecting the wafer.

The embodiments described above are merely illustrative of the technical spirit and the features of the present invention, and the objects of the present invention can be understood by those skilled in the art, and the scope of the present invention cannot be limited thereto. That is, the equivalent variations or modifications made by the spirit of the present invention should still be included in the scope of the present invention.

10. . . First film

12. . . Internal point

14. . . External point

20. . . Wafer

30. . . Conductive solder ball

40. . . Second film

1A, 1B, 1C, 1D and 1E are schematic views showing an embodiment of the present invention.

2 is a schematic view of an embodiment of the invention.

10. . . First film

12. . . Internal point

14. . . External point

20. . . Wafer

30. . . Conductive solder ball

40. . . Second film

Claims (8)

A chip package structure comprising: a first adhesive film having a plurality of inner contacts on an upper surface and a plurality of external contacts on a lower surface, wherein the inner contacts are electrically connected to the external contacts; At least one wafer is disposed on the upper surface of the first adhesive film and electrically connected to the inner contacts; a second adhesive film covers the wafer and forms a closed space with the first adhesive film The wafer is received; and a plurality of conductive solder balls are disposed on the external contacts. The chip package structure of claim 1, wherein the wafer has a plurality of copper bumps electrically connected to the inner contact. The chip package structure of claim 1, further comprising a plurality of the wafers stacked on each other. A chip packaging method includes the steps of: providing a first film, wherein the first film has a plurality of inner contacts on an upper surface and a plurality of external contacts on a lower surface, and the inner contacts are The external contacts are electrically connected; at least one wafer is disposed on the upper surface of the first adhesive film and the wafer is electrically connected to the inner contacts; and a plurality of conductive solder balls are disposed on the external contacts; Forming a second film on the wafer; and removing a first film and the second film by using a stamping step, and connecting the first film to the second film to form a closed space to accommodate The wafer is placed. The wafer packaging method according to claim 4, wherein a heating step is further provided at the same time. The wafer packaging method of claim 4, wherein a plurality of the wafers are stacked on each other. The chip packaging method of claim 6, wherein the stacked chips are electrically connected using a through-silicon via (TSV) technique. The chip packaging method of claim 4, wherein the wafer is electrically connected to the inner contacts by using a plurality of copper bumps on the active surface.