TWI459481B - Semiconductor package structure and its manufacturing method - Google Patents

Description

Semiconductor package structure and its manufacturing method

The invention relates to a semiconductor package structure and a manufacturing method thereof, in particular to a semiconductor package structure with high reliability and a manufacturing method thereof.

With the booming electronics industry, the packaging step has become one of the important processes in electronic products. According to the estimation of foreign research institutions, wafer level package and embedded package from EM 2011 The average annual growth rate to 2015 is about 30%, which is much larger than the average annual growth rate of other packaged types of structures. This is because wafer-level packages and embedded packages have the advantages of good electrical properties, lightness and shortness.

As shown in FIG. 1 , a cross-sectional view of a conventional wafer level package structure is a semiconductor wafer package method, which is performed directly on the wafer after the integrated circuit on the entire wafer is completed. The encapsulation (for example, hot molding of the encapsulation material 12, etc.) is performed, and finally, the package structure having the semiconductor wafer 11 is cut, and the packaged size is close to that of a general semiconductor wafer.

However, wafer-level packaging has a number of disadvantages, such as the tendency to bend or warp the package structure, the tendency of semiconductor wafers to be deflected by hot molding, and low typographic use.

As shown in FIG. 2, it is a cross-sectional view of a conventional embedded package structure. The so-called embedded package is another semiconductor wafer package method, which first cuts a wafer into a plurality of semiconductor wafers 21, and then presses them together. The semiconductor wafer 21 is embedded in the substrate 20 by a process.

However, the embedded package structure also has many disadvantages, such as: the semiconductor wafer is easily broken due to pressure during the pressing process, the asymmetric package structure is liable to cause overall bending or warping, and the semiconductor wafer is easy to be pressed in the process. Offset and other issues.

Therefore, how to propose a semiconductor package structure and a manufacturing method thereof to avoid the problem that the conventional semiconductor package structure is easily warped, and the semiconductor wafer inside thereof is easily offset and fragmented, resulting in poor reliability of the product, etc. The problem that is currently being solved.

In view of the above-mentioned various deficiencies of the prior art, the main object of the present invention is to provide a semiconductor package structure of higher quality and a method of fabricating the same.

To achieve the above and other objects, the present invention discloses a semiconductor package structure comprising: a semiconductor wafer having opposite active and non-active surfaces, and a plurality of electrode pads formed on the active surface, the active surface and the same Forming a passivation layer on the electrode pad, the passivation layer having a passivation layer opening exposing each of the electrode pads, wherein the electrode pads in each of the passivation layer openings are formed with metal bumps; the cladding layer is coated on the semiconductor wafer, and Having a first surface and a second surface, each of the metal bumps is exposed on the first surface of the cladding layer; a dielectric layer is formed on the first surface and the metal bump, and has a plurality of exposed a dielectric layer trenching region of the metal bump; a circuit layer formed in each of the dielectric layer trench regions and electrically connected to the metal bump, the circuit layer extending to a range outside the active surface; An insulating protective layer is formed on the dielectric layer and the wiring layer, and is formed with a plurality of insulating protective layer openings, and the circuit layer is exposed.

The invention discloses a method for fabricating a semiconductor package structure, comprising: providing a cladding layer having opposite first and second surfaces, wherein the cladding layer is embedded with a plurality of semiconductor wafers, each of the semiconductors The wafer has opposite active and non-active surfaces, and a plurality of electrode pads formed on the active surface. The active surface and the electrode pad are formed with a passivation layer having a passivation layer opening for exposing each of the electrode pads. Metal bumps are formed on the electrode pads in the openings of the passivation layers, and the metal bumps are exposed on the first surface of the cladding layer; a dielectric layer is formed on the first surface and the metal bumps. The electric layer has a plurality of dielectric layer grooved regions exposing the metal bumps, and a label layer is formed on the second surface, and the label layer is formed with a metal foil; formed in each of the dielectric layer grooved regions Electrically connecting the circuit layer of the metal bump; forming an insulating protective layer on the dielectric layer and the circuit layer, the insulating protective layer is formed with a plurality of insulating protective layer openings, and the exposed portion of the circuit layer; Layering Forming a solder ball on the circuit layer; covering the insulating material layer and the solder ball with the encapsulating material layer; removing the metal foil; and cutting between the two adjacent semiconductor wafers, and removing the encapsulating material layer, To form a plurality of semiconductor package structures.

As can be seen from the above, since the semiconductor package structure of the present invention is close to a symmetric structure, the problem of overall bending or warpage caused by asymmetric stress of the package structure can be effectively solved; secondly, since the present invention re-uses metal foil in the process Therefore, the strength of the overall package structure can be increased to avoid damage or deformation during the process; in addition, the present invention can solve the problem that the semiconductor wafer is easily damaged under high temperature and high pressure without the need of a hot stamping process, thereby improving the final product. Reliability.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

In general, the implementation of the present invention can be divided into two stages. First, a plurality of semiconductor wafers are prepared. Referring to Figures 3A to 3C, there are shown cross-sectional views of a semiconductor wafer of the semiconductor package structure of the present invention and a method of fabricating the same.

As shown in FIG. 3A, a semiconductor wafer 30 having opposing surface 30a and non-active surface 30b and a plurality of electrode pads 31 formed on the active surface 30a is provided. The active surface 30a and the electrode pads 31 are provided. A passivation layer 32 is formed thereon, and the passivation layer 32 has a plurality of passivation layer openings 320 exposing the electrode pads 31.

As shown in FIG. 3B, metal bumps 33 are formed on the electrode pads 31 in each of the passivation layer openings 320.

As shown in Fig. 3C, the semiconductor wafer 30 is thinned from the non-active surface 30b, and the semiconductor wafer 30 is diced to obtain a plurality of semiconductor wafers 30'.

Next, the steps of fabricating the semiconductor package structure, please refer to FIGS. 4A to 4M, which are cross-sectional views of the semiconductor package structure of the present invention and a method of manufacturing the same.

As shown in FIG. 4A, a carrier plate 40 is provided having a release layer 41 formed of a first adhesive layer 411, a plastic film 410 and a second adhesive layer 412 on one surface.

As shown in Fig. 4B, the semiconductor wafers 30' are provided, and the semiconductor wafers 30' are placed on the first adhesive layer 411 with the side of the metal bumps 33.

As shown in Fig. 4C, a cladding layer 42 covering the semiconductor wafers 30' is formed on the first adhesive layer 411 by, for example, printing.

As shown in FIG. 4D, the carrier plate 40 and the release layer 41 are removed. At this time, the cladding layer 42 has a first surface 42a and a second surface 42b opposite to each other, and the metal bumps 33 are exposed to the metal bumps 33. The first surface 42a of the cladding layer 42.

As shown in FIG. 4E, a dielectric layer 43 is formed on the first surface 42a and the metal bumps 33, and a label layer 44 is formed on the second surface 42b, and a metal foil 45 is formed on the label layer 44. The material of the dielectric layer 43 and the label layer 44 may be ABF (Ajinomoto Build-up Film).

As shown in FIG. 4F, a plurality of dielectric layer trench regions 430 are formed in the dielectric layer 43 to expose the metal bumps 33.

As shown in FIG. 4G, a wiring layer 46 electrically connecting the metal bumps 33 is formed in each of the dielectric layer trench regions 430.

As shown in FIG. 4H, an insulating protective layer 47 is formed on the dielectric layer 43 and the wiring layer 46, and the insulating protective layer 47 is formed with a plurality of insulating protective layer openings 470, and the wiring layer 46 is exposed.

As shown in FIG. 4I, solder balls 48 are formed on the wiring layer 46 in each of the insulating protective layer openings 470.

As shown in FIG. 4J, the insulating material layer 47 and the solder balls 48 are covered with the encapsulating material layer 49.

The metal foil 45 is removed as shown in Fig. 4K.

As shown in FIG. 4L, a laser label trench 440 is formed on the label layer 44, and is cut between two adjacent semiconductor wafers 30' to form a label layer 44, a cladding layer 42, and a through layer. The electrical layer 43, the insulating protective layer 47 and the trench 50 of the portion of the encapsulating material layer 49.

The encapsulation material layer 49 is removed as shown in FIG. 4M to form a plurality of semiconductor package structures 4.

The present invention further discloses a semiconductor package structure, comprising: a semiconductor wafer 30' having opposite active and non-active surfaces 30a' and 30b', and a plurality of electrode pads 31 formed on the active surface 30a'. A passivation layer 32 is formed on the surface 30a' and the electrode pads 31. The passivation layer 32 has a passivation layer opening 320 exposing each of the electrode pads 31. Metal is formed on the electrode pads 31 in each of the passivation layer openings 320. a bumper 33 covering the semiconductor wafer 30' and having a first surface 42a and a second surface 42b opposite to each other, each of the metal bumps 33 being exposed on the first surface of the cladding layer 42 42a; a dielectric layer 43 is formed on the first surface 42a and the metal bumps 33, and has a dielectric layer trenching region 430 exposing each of the metal bumps 33; a circuit layer 46 is formed in each of the layers In the dielectric layer trenching region 430, and electrically connecting the metal bumps 33, the wiring layer 46 extends to a range outside the active surface 30a'; and an insulating protective layer 47 is formed on the dielectric layer 43 and the wiring a layer 46 is formed with a plurality of insulating protective layer openings 470, and the exposed portion of the line Layer 46.

In the above semiconductor package structure, the package layer 44 is formed on the second surface 42b, and the surface of the label layer 44 has a laser label trench 440.

In the semiconductor package structure of the embodiment, the material of the dielectric layer 43 and the label layer 44 may be ABF (Ajinomoto Build-up Film).

According to the semiconductor package structure described above, the solder ball 48 may be formed on the circuit layer 46 in each of the insulating protective layer openings 470.

In summary, unlike the conventional technology, since the semiconductor package structure of the present invention is a symmetric structure (for example, the symmetric arrangement of the dielectric layer 43 and the label layer 44), the bending or warpage of the package structure can be effectively solved. Secondly, because the invention re-uses the metal foil in the process, the strength of the overall package structure can be increased to avoid damage during the process; in addition, the invention can solve the high temperature and high pressure of the semiconductor wafer without the hot stamping process. The problem of easy brittleness increases the reliability of the final product.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

11,21,30’. . . Semiconductor wafer

12. . . Packaging material

20. . . Substrate

30. . . Semiconductor wafer

30a, 30a’. . . Action surface

30b, 30b’. . . Non-active surface

31. . . Electrode pad

32. . . Passivation layer

320. . . Passivation layer opening

33. . . Metal bump

40. . . Carrier board

41. . . Release layer

410. . . Plastic film

411. . . First adhesive layer

412. . . Second adhesive layer

42. . . Coating

42a. . . First surface

42b. . . Second surface

43. . . Dielectric layer

430. . . Dielectric layer slotted area

44. . . Label layer

440. . . Laser tag trench

45. . . Metal foil

46. . . Circuit layer

47. . . Insulating protective layer

470. . . Insulating protective layer opening

48. . . Solder ball

49. . . Packaging material layer

50. . . Trench

4. . . Semiconductor package structure

Figure 1 is a cross-sectional view of a conventional wafer level package structure;

Figure 2 is a cross-sectional view of a conventional embedded package structure;

3A to 3C are cross-sectional views showing a semiconductor wafer of a semiconductor package structure of the present invention and a method of manufacturing the same;

4A to 4M are cross-sectional views showing a semiconductor package structure of the present invention and a method of manufacturing the same.

30’. . . Semiconductor wafer

30a’. . . Action surface

30b’. . . Non-active surface

31. . . Electrode pad

32. . . Passivation layer

33. . . Metal bump

42. . . Coating

43. . . Dielectric layer

44. . . Label layer

440. . . Laser tag trench

46. . . Circuit layer

47. . . Insulating protective layer

48. . . Solder ball

4. . . Semiconductor package structure

Claims (9)

A semiconductor package structure comprising: a semiconductor wafer having opposite active and non-active surfaces; and a plurality of electrode pads formed on the active surface, the active surface and the electrode pads are formed with a passivation layer, the passivation layer a passivation layer opening having exposed each of the electrode pads, wherein the electrode pads in each of the passivation layer openings are formed with metal bumps; the cladding layer covers the semiconductor wafer and has opposite first and second surfaces Each of the metal bumps is exposed on the first surface of the cladding layer; the dielectric layer is formed on the first surface and the metal bump, and has a plurality of dielectric layer trenches exposing each of the metal bumps a circuit layer formed in each of the dielectric layer trench regions and electrically connected to the metal bumps, the circuit layer extending to a range outside the active surface; and an insulating protective layer formed on the dielectric layer And a circuit layer, and formed with a plurality of insulating protective layer openings, the exposed portion of the circuit layer; and a label layer formed on the second surface of the cladding layer and having a laser label trench. The semiconductor package structure according to claim 1, wherein the material of the dielectric layer and the label layer is ABF (Ajinomoto Build-up Film). The semiconductor package structure according to claim 1, wherein the solder ball is formed on the circuit layer in each of the openings of the insulating protective layer. A method of fabricating a semiconductor package structure, comprising: providing a cladding layer having a first surface opposite to a plurality of semiconductor wafers embedded in the cladding layer, each of the semiconductor wafers having a working surface and an inactive surface, and a plurality of electrode pads formed on the active surface, the active surface and the electrode pads being formed a passivation layer having a passivation layer opening for exposing each of the electrode pads, wherein the electrode pads in each of the passivation layer openings are formed with metal bumps, and each of the metal bumps is exposed to the first of the cladding layers Forming a dielectric layer on the first surface and the metal bump, the dielectric layer having a plurality of dielectric layer trench regions exposing each of the metal bumps, and forming a label layer on the second surface, and a metal foil is formed on the label layer; a circuit layer electrically connecting the metal bumps is formed in each of the dielectric layer trench regions; an insulating protective layer is formed on the dielectric layer and the circuit layer, and the insulating protective layer is formed a plurality of insulating protective layer openings, the exposed portion of the circuit layer; forming solder balls on the circuit layer in each of the insulating protective layer openings; covering the insulating protective layer and the solder ball with the encapsulating material layer; removing the metal foil And two of the adjacent two Between the donor wafer for cutting and removing the encapsulating material layer to form a plurality of semiconductor package. The method for fabricating a semiconductor package structure according to claim 4, wherein the step of forming the cladding layer comprises: providing a carrier board having a first adhesive layer on one surface; providing the semiconductor wafers, The semiconductor wafers are disposed on the first adhesive layer with their metal bumps on the side; the cladding layer covering the semiconductor wafers is formed on the first adhesive layer; The carrier plate and the first adhesive layer are removed. The method for fabricating a semiconductor package structure according to claim 4, wherein the forming step of the semiconductor wafer comprises: providing a surface having opposite and non-active surfaces, and electrodes formed on the active surface a passivation layer is formed on the active semiconductor surface of the pad, and the passivation layer has an opening of the passivation layer exposing each of the electrode pads; and the electrode pad is formed on each of the passivation layer openings a metal bump; thinning the semiconductor wafer from the inactive surface; and dicing the semiconductor wafer to obtain the semiconductor wafer. The method of fabricating a semiconductor package structure according to claim 4, wherein the laser label trench is formed on the label layer before the cutting. The method of manufacturing a semiconductor package structure according to claim 5, wherein a plastic film and a second adhesive layer are formed between the first adhesive layer and the carrier plate, and the plastic film is formed on the first adhesive layer. Between the layer and the second adhesive layer, and the second adhesive layer is formed between the plastic film and the carrier plate, and the step of removing the carrier plate and the first adhesive layer comprises removing the plastic film and The second adhesive layer. The method of fabricating a semiconductor package structure according to claim 4, wherein the material of the dielectric layer and the label layer is ABF (Ajinomoto Build-up Film).